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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory32/] [blockMemory/] [simulation/] [timing/] [simcmds.tcl] - Blame information for rev 5

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# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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# 
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# This file contains confidential and proprietary information
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# of Xilinx, Inc. and is protected under U.S. and
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# international copyright and other intellectual property
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# laws.
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# 
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# rights to the materials distributed herewith. Except as
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# otherwise provided in a valid license issued to you by
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# Xilinx, and to the maximum extent permitted by applicable
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# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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# (2) Xilinx shall not be liable (whether in contract or tort,
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# including negligence, or under any other theory of
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# liability) for any loss or damage of any kind or nature
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# related to, arising under or in connection with these
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# reasonably foreseeable or Xilinx had been advised of the
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# possibility of the same.
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# 
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# CRITICAL APPLICATIONS
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# Xilinx products are not designed or intended to be fail-
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# safe, or for use in any application requiring fail-safe
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# performance, such as life-support or safety devices or
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# applications related to the deployment of airbags, or any
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# other applications that could lead to death, personal
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# Applications"). Customer assumes the sole risk and
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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# PART OF THIS FILE AT ALL TIMES.
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wcfg new
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isim set radix hex
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wave add /blockMemory_tb/status
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      wave add  /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/RSTA
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      wave add  /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/CLKA
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      wave add  /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/ADDRA
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      wave add  /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DINA
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      wave add  /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/WEA
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      wave add  /blockMemory_tb/blockMemory_synth_inst/BMG_PORT/DOUTA
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run all
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quit

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