URL https://opencores.org/ocsvn/mod_mult_exp/mod_mult_exp/trunk

Subversion Repositories mod_mult_exp

[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [_xmsgs/] [cg.xmsgs] - Blame information for rev 5

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Generating IP...

 
A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten.

 
Component blk_mem_gen_v7_1 does not have a valid model name for VHDL synthesis

 
Pre-processing HDL files for 'blockMemory'...

 
Finished generation of ASY schematic symbol.

 
Finished FLIST file generation.

 

 

Line No.	Rev	Author	Line
1	5	gajos
2
7
8			`Generating IP...`
9
10
11			`A core named 'blockMemory' already exists in the project. Output products for this core may be overwritten.`
12
13
14			`Component blk_mem_gen_v7_1 does not have a valid model name for VHDL synthesis`
15
16
17			`Pre-processing HDL files for 'blockMemory'...`
18
19
20			`Finished generation of ASY schematic symbol.`
21
22
23			`Finished FLIST file generation.`
24
25
26
27

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Subversion Repositories mod_mult_exp

[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory512/] [_xmsgs/] [cg.xmsgs] - Blame information for rev 5