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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_exp/] [blockMemory64/] [blockMemory/] [implement/] [implement.sh] - Blame information for rev 5

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#!/bin/sh
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# Clean up the results directory
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rm -rf results
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mkdir results
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#Synthesize the Wrapper Files
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echo 'Synthesizing example design with XST';
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xst -ifn xst.scr
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cp blockMemory_exdes.ngc ./results/
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# Copy the netlist generated by Coregen
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echo 'Copying files from the netlist directory to the results directory'
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cp ../../blockMemory.ngc results/
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#  Copy the constraints files generated by Coregen
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echo 'Copying files from constraints directory to results directory'
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cp ../example_design/blockMemory_exdes.ucf results/
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cd results
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echo 'Running ngdbuild'
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ngdbuild -p xc3s500e-fg320-5 blockMemory_exdes
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echo 'Running map'
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map blockMemory_exdes -o mapped.ncd -pr i
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echo 'Running par'
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par mapped.ncd routed.ncd
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echo 'Running trce'
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trce -e 10 routed.ncd mapped.pcf -o routed
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echo 'Running design through bitgen'
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bitgen -w routed
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echo 'Running netgen to create gate level VHDL model'
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netgen -ofmt vhdl -sim -tm blockMemory_exdes -pcf mapped.pcf -w routed.ncd routed.vhd

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