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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [mod_mult/] [ModularMultiplierIterative.vhd] - Blame information for rev 6

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1 3 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Montgomery modular multiplier and exponentiator               ----
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----                                                               ----
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---- This file is part of the Montgomery modular multiplier        ----
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---- and exponentiator project                                     ----
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---- http://opencores.org/project,mod_mult_exp                     ----
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----                                                               ----
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---- Description:                                                  ----
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----   Montgomery modular multiplier main module. It combines all  ----
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----   subomponents. It takes two numbers and modulus as the input ----
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----   and returns the Montgomery product A*B*(R^{-1}) mod M       ----
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----   where R^{-1} is the modular multiplicative inverse.         ----
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----   R*R^{-1} == 1 mod M                                         ----
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----   R = 2^word_length mod M                                     ----
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----               and word_length is the binary width of the      ----
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----               operated word (in this case 32, 64 or 512 bit)  ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2019 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.properties.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ModularMultiplierIterative is
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    generic (
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             word_size : integer := WORD_LENGTH
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    );
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    port (
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        A       : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);     -- multiplicand
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                  B       : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);     -- multiplier
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                  M       : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);     -- modulus
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                  start   : in  STD_LOGIC;
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                  product : out STD_LOGIC_VECTOR(word_size - 1 downto 0); -- product
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                  ready   : out STD_LOGIC;
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                  clk     : in  STD_LOGIC
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    );
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end ModularMultiplierIterative;
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architecture Behavioral of ModularMultiplierIterative is
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-- Multiplexer
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component MontMult4inMux is
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    generic (
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             word_size : integer := WORD_LENGTH
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         );
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    port (
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             ctrl   : in  STD_LOGIC_VECTOR(1 downto 0);
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             zero   : in  STD_LOGIC_VECTOR(word_size downto 0);
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        M      : in  STD_LOGIC_VECTOR(word_size downto 0);
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        Y      : in  STD_LOGIC_VECTOR(word_size downto 0);
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        YplusM : in  STD_LOGIC_VECTOR(word_size downto 0);
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                  output : out STD_LOGIC_VECTOR(word_size downto 0)
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    );
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end component MontMult4inMux;
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-- State machine
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component ModMultIter_SM is
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    generic (
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             word_size : integer := WORD_LENGTH
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         );
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    port(
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        x             : in  STD_LOGIC_VECTOR(word_size - 1 downto 0);
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                  start         : in  STD_LOGIC;
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                  clk           : in  STD_LOGIC;
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                  s_0           : in  STD_LOGIC;
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                  y_0           : in  STD_LOGIC;
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                  ready         : out STD_LOGIC;
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                  out_reg_en    : out STD_LOGIC;
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                  mux_mult_ctrl : out STD_LOGIC;
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                  mux_4in_ctrl  : out STD_LOGIC_VECTOR(1 downto 0)
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         );
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end component ModMultIter_SM;
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-- Signals
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signal Mi              : STD_LOGIC_VECTOR(word_size downto 0);
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signal Yi              : STD_LOGIC_VECTOR(word_size downto 0);
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signal sumYM           : STD_LOGIC_VECTOR(word_size downto 0);
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signal zero_sig        : STD_LOGIC_VECTOR(word_size downto 0) := (others => '0');
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signal four_in_mux_out : STD_LOGIC_VECTOR(word_size downto 0);
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signal mux_4in_ctrl_sig  : STD_LOGIC_VECTOR(1 downto 0);
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signal mult_mux_ctrl_sig : STD_LOGIC;
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signal mult_mux_out     : STD_LOGIC_VECTOR(word_size downto 0);
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signal out_reg_sig      : STD_LOGIC_VECTOR(word_size downto 0);
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signal product_sig      : STD_LOGIC_VECTOR(word_size downto 0);
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signal out_en           : STD_LOGIC;
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signal sum_mult_out     : STD_LOGIC_VECTOR(word_size + 1 downto 0);
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signal sum_div_2        : STD_LOGIC_VECTOR(word_size downto 0);
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begin
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     zero_sig <= (others => '0'); -- '0'
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         -- 'widening' to store the intermediate steps
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         Mi <= '0' & M;
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         Yi <= '0' & B;
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         -- Operations needed to compute the Montgomery multiplications
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         sum_div_2 <= sum_mult_out(word_size + 1 downto 1);
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         sum_mult_out <= ('0' & four_in_mux_out) + ('0' & mult_mux_out);
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         sumYM <= ('0' & B) + ('0' & M);
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         -- Multiplexer component
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         four_in_mux : MontMult4inMux port map(
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             ctrl => mux_4in_ctrl_sig, zero => zero_sig, M => Mi, Y => Yi,
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        YplusM => sumYM, output => four_in_mux_out
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         );
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         -- Two input asynchronuos multiplexer for output 'not clear' code due to
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         -- 'historical works'
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         mult_mux_out <= (others => '0') when (mult_mux_ctrl_sig = '0') else
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                   out_reg_sig;
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         -- State machine
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         state_machine : ModMultIter_SM port map(
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        x => A,
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                  start => start,
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                  clk => clk,
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                  s_0 => out_reg_sig(0),
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                  y_0 => B(0),
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                  ready => ready,
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                  out_reg_en => out_en,
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                  mux_mult_ctrl => mult_mux_ctrl_sig,
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                  mux_4in_ctrl => mux_4in_ctrl_sig
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         );
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             -- Register like structure for signal synchronous work
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                 clock : process(clk, start)
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             begin
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                      if (clk = '1' and clk'Event) then
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                                    if (start = '0') then
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                                        out_reg_sig <= (others => '0');
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                                         elsif out_en = '1' then
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                                                  out_reg_sig <= sum_div_2;
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                                        end if;
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                           end if;
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                  end process clock;
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                  -- One additional 'subtract' component which was added after
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                  -- first experiments with Montgomery multiplication. It was
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                  -- observed that sometimes intermediate step can be higher 
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                  -- than modulus. In this situation 'M' substraction is 
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                  -- compulsory
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                  product_proc : process(clk, Mi, out_reg_sig)
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                  begin
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                                if(out_reg_sig < ("0" & Mi)) then
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                                         product_sig <= out_reg_sig;
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                                else
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                                         product_sig <= out_reg_sig - Mi;
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                                end if;
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                  end process product_proc;
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                  product <= product_sig(word_size - 1 downto 0);
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end Behavioral;

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