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----------------------------------------------------------------------
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---- adder_n ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- This file contains the implementation of a n-bit adder ----
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---- using adder_blocks, divides the adder in stages ----
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---- used for the montgommery multiplier pre- and post- ----
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---- computation adder ----
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---- ----
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---- Dependencies: ----
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---- - adder_block ----
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---- ----
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---- Author(s): ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- n-bit adder using adder blocks. works in stages, to prevent large
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-- carry propagation
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-- Result avaiable after (width/block_width) clock cycles
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entity adder_n is
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generic (
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width : integer := 1536; -- adder operands width
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block_width : integer := 8 -- adder blocks size
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);
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port (
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-- clock input
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core_clk : in std_logic;
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-- adder input operands (width)-bit
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a : in std_logic_vector((width-1) downto 0);
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b : in std_logic_vector((width-1) downto 0);
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-- carry in, out
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cin : in std_logic;
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cout : out std_logic;
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-- adder output result (width)-bit
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r : out std_logic_vector((width-1) downto 0)
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);
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end adder_n;
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architecture Structural of adder_n is
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constant nr_of_blocks : integer := width/block_width; -- number of blocks/stages in the adder
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signal carry : std_logic_vector(nr_of_blocks downto 0); -- vector for the carry bits
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begin
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-- report failure if width is not dividable by block_width
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assert (width mod block_width)=0
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report "adder_n: width is not divisible by block_width!!" severity failure;
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-- carry in
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carry(0) <= cin;
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-- structure of (nr_of_blocks) adder_blocks
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adder_block_chain : for i in 0 to (nr_of_blocks-1) generate
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adder_blocks : adder_block
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generic map(
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width => block_width
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)
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port map(
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core_clk => core_clk,
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a => a((((i+1)*block_width)-1) downto (i*block_width)),
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b => b((((i+1)*block_width)-1) downto (i*block_width)),
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cin => carry(i),
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cout => carry(i+1),
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r => r((((i+1)*block_width)-1) downto (i*block_width))
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);
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end generate;
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-- carry out
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cout <= carry(nr_of_blocks);
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end Structural;
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