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JonasDC |
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---- fifo_generic ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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JonasDC |
---- behavorial description of a FIFO, correctly inferred by ----
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---- altera and xilinx. ----
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---- ----
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---- Resources needed (xilinx): ----
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---- - RAM: (depth+1 * 32) bits ----
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---- - 2 adders/substractors ----
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---- - 2 comparators ----
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---- - 2 registers: aw bits (for the address pointers) ----
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---- - 3 registers: 1 bit (for the flags) ----
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---- ----
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JonasDC |
---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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use mod_sim_exp.std_functions.all;
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JonasDC |
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entity fifo_generic is
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generic (
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depth : integer := 32
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);
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port (
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clk : in std_logic; -- clock input
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din : in std_logic_vector (31 downto 0); -- 32 bit input data for push
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dout : out std_logic_vector (31 downto 0); -- 32 bit output data for pop
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empty : out std_logic; -- empty flag, 1 when FIFO is empty
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full : out std_logic; -- full flag, 1 when FIFO is full
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push : in std_logic;
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pop : in std_logic;
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reset : in std_logic;
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nopop : out std_logic;
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nopush : out std_logic
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);
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JonasDC |
end fifo_generic;
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architecture arch of fifo_generic is
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-- calculate the width for the address-pointers
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constant aw : integer := log2(depth+1);
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-- read and write pointer
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signal rd_addr : std_logic_vector(aw-1 downto 0);
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signal wr_addr : std_logic_vector(aw-1 downto 0);
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-- control signals
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signal empty_i : std_logic;
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signal full_i : std_logic;
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signal push_i : std_logic;
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signal push_i_d : std_logic;
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signal pop_i : std_logic;
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begin
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empty <= empty_i;
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full <= full_i;
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-- full flag is 1 when read address is one below write address
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full_i <= '1' when (wr_addr+'1'=rd_addr) or
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(wr_addr=conv_std_logic_vector(depth, aw) and (rd_addr=conv_std_logic_vector(0, aw)))
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else '0';
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-- empty flag is 1 when read and write address are the same
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empty_i <= '1' when (wr_addr=rd_addr) else '0';
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fifo_addr_proc : process (clk)
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begin
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if rising_edge(clk) then
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if reset='1' then -- if reset, both read and write address point to the maximum address (depth)
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wr_addr <= conv_std_logic_vector(depth, aw);
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rd_addr <= conv_std_logic_vector(depth, aw);
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else
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if push_i='1' then -- push
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if (wr_addr=conv_std_logic_vector(depth, aw)) then
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wr_addr <= (others=>'0'); -- if overflow, set to zero
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else
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wr_addr <= wr_addr+'1'; -- else, increase address
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end if;
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end if;
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if pop_i='1' then -- pop
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if (rd_addr=conv_std_logic_vector(depth, aw)) then
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rd_addr <= (others=>'0'); -- if overflow, set to zero
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else
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rd_addr <= rd_addr+'1'; -- else, increase address
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end if;
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end if;
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end if;
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push_i_d <= push_i; -- delayed version of push signal
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nopop <= (pop and empty_i) or (pop and reset);
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nopush <= (push and full_i) or (push and reset);
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end if;
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end process;
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push_i <= push and not full_i;
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pop_i <= pop and not empty_i;
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-- Block RAM
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ramblock: dpram_generic
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generic map(
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depth => depth+1
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)
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port map(
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clk => clk,
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-- write port
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waddr => wr_addr,
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we => push_i_d,
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din => din,
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-- read port
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raddr => rd_addr,
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dout => dout
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);
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end arch;
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