1 |
3 |
JonasDC |
----------------------------------------------------------------------
|
2 |
|
|
---- operand_dp ----
|
3 |
|
|
---- ----
|
4 |
|
|
---- This file is part of the ----
|
5 |
|
|
---- Modular Simultaneous Exponentiation Core project ----
|
6 |
|
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
7 |
|
|
---- ----
|
8 |
|
|
---- Description ----
|
9 |
|
|
---- 4 x 512 bit dual port ram for the operands ----
|
10 |
|
|
---- 32 bit read and write for bus side and 512 bit read and ----
|
11 |
|
|
---- write for multiplier side ----
|
12 |
|
|
---- ----
|
13 |
|
|
---- Dependencies: none ----
|
14 |
|
|
---- ----
|
15 |
|
|
---- Authors: ----
|
16 |
|
|
---- - Geoffrey Ottoy, DraMCo research group ----
|
17 |
|
|
---- - Jonas De Craene, JonasDC@opencores.org ----
|
18 |
|
|
---- ----
|
19 |
|
|
----------------------------------------------------------------------
|
20 |
|
|
---- ----
|
21 |
|
|
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
|
22 |
|
|
---- ----
|
23 |
|
|
---- This source file may be used and distributed without ----
|
24 |
|
|
---- restriction provided that this copyright statement is not ----
|
25 |
|
|
---- removed from the file and that any derivative work contains ----
|
26 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
27 |
|
|
---- ----
|
28 |
|
|
---- This source file is free software; you can redistribute it ----
|
29 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
30 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
31 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
32 |
|
|
---- later version. ----
|
33 |
|
|
---- ----
|
34 |
|
|
---- This source is distributed in the hope that it will be ----
|
35 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
36 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
37 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
38 |
|
|
---- details. ----
|
39 |
|
|
---- ----
|
40 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
41 |
|
|
---- Public License along with this source; if not, download it ----
|
42 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
43 |
|
|
---- ----
|
44 |
|
|
----------------------------------------------------------------------
|
45 |
|
|
----------------------------------------------------------------------
|
46 |
|
|
-- This file is owned and controlled by Xilinx and must be used --
|
47 |
|
|
-- solely for design, simulation, implementation and creation of --
|
48 |
|
|
-- design files limited to Xilinx devices or technologies. Use --
|
49 |
|
|
-- with non-Xilinx devices or technologies is expressly prohibited --
|
50 |
|
|
-- and immediately terminates your license. --
|
51 |
|
|
-- --
|
52 |
|
|
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
53 |
|
|
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
54 |
|
|
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
55 |
|
|
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
56 |
|
|
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
57 |
|
|
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
58 |
|
|
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
59 |
|
|
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
60 |
|
|
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
61 |
|
|
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
62 |
|
|
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
63 |
|
|
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
64 |
|
|
-- FOR A PARTICULAR PURPOSE. --
|
65 |
|
|
-- --
|
66 |
|
|
-- Xilinx products are not intended for use in life support --
|
67 |
|
|
-- appliances, devices, or systems. Use in such applications are --
|
68 |
|
|
-- expressly prohibited. --
|
69 |
|
|
-- --
|
70 |
|
|
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
71 |
|
|
-- All rights reserved. --
|
72 |
|
|
----------------------------------------------------------------------
|
73 |
2 |
JonasDC |
-- You must compile the wrapper file operand_dp.vhd when simulating
|
74 |
|
|
-- the core, operand_dp. When compiling the wrapper file, be sure to
|
75 |
|
|
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
76 |
|
|
-- instructions, please refer to the "CORE Generator Help".
|
77 |
|
|
|
78 |
|
|
-- The synthesis directives "translate_off/translate_on" specified
|
79 |
|
|
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
80 |
|
|
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
81 |
|
|
|
82 |
3 |
JonasDC |
|
83 |
|
|
library ieee;
|
84 |
|
|
use ieee.std_logic_1164.ALL;
|
85 |
2 |
JonasDC |
-- synthesis translate_off
|
86 |
3 |
JonasDC |
library XilinxCoreLib;
|
87 |
2 |
JonasDC |
-- synthesis translate_on
|
88 |
|
|
|
89 |
3 |
JonasDC |
|
90 |
|
|
entity operand_dp is
|
91 |
|
|
port (
|
92 |
|
|
clka : in std_logic;
|
93 |
|
|
wea : in std_logic_vector(0 downto 0);
|
94 |
|
|
addra : in std_logic_vector(5 downto 0);
|
95 |
|
|
dina : in std_logic_vector(31 downto 0);
|
96 |
|
|
douta : out std_logic_vector(511 downto 0);
|
97 |
|
|
clkb : in std_logic;
|
98 |
|
|
web : in std_logic_vector(0 downto 0);
|
99 |
|
|
addrb : in std_logic_vector(5 downto 0);
|
100 |
|
|
dinb : in std_logic_vector(511 downto 0);
|
101 |
|
|
doutb : out std_logic_vector(31 downto 0)
|
102 |
|
|
);
|
103 |
|
|
end operand_dp;
|
104 |
|
|
|
105 |
|
|
|
106 |
|
|
architecture operand_dp_a of operand_dp is
|
107 |
2 |
JonasDC |
-- synthesis translate_off
|
108 |
3 |
JonasDC |
component wrapped_operand_dp
|
109 |
|
|
port (
|
110 |
|
|
clka : in std_logic;
|
111 |
|
|
wea : in std_logic_vector(0 downto 0);
|
112 |
|
|
addra : in std_logic_vector(5 downto 0);
|
113 |
|
|
dina : in std_logic_vector(31 downto 0);
|
114 |
|
|
douta : out std_logic_vector(511 downto 0);
|
115 |
|
|
clkb : in std_logic;
|
116 |
|
|
web : in std_logic_vector(0 downto 0);
|
117 |
|
|
addrb : in std_logic_vector(5 downto 0);
|
118 |
|
|
dinb : in std_logic_vector(511 downto 0);
|
119 |
|
|
doutb : out std_logic_vector(31 downto 0)
|
120 |
|
|
);
|
121 |
|
|
end component;
|
122 |
2 |
JonasDC |
|
123 |
|
|
-- Configuration specification
|
124 |
|
|
for all : wrapped_operand_dp use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
|
125 |
|
|
generic map(
|
126 |
|
|
c_has_regceb => 0,
|
127 |
|
|
c_has_regcea => 0,
|
128 |
|
|
c_mem_type => 2,
|
129 |
|
|
c_rstram_b => 0,
|
130 |
|
|
c_rstram_a => 0,
|
131 |
|
|
c_has_injecterr => 0,
|
132 |
|
|
c_rst_type => "SYNC",
|
133 |
|
|
c_prim_type => 1,
|
134 |
|
|
c_read_width_b => 32,
|
135 |
|
|
c_initb_val => "0",
|
136 |
|
|
c_family => "virtex6",
|
137 |
|
|
c_read_width_a => 512,
|
138 |
|
|
c_disable_warn_bhv_coll => 0,
|
139 |
|
|
c_write_mode_b => "WRITE_FIRST",
|
140 |
|
|
c_init_file_name => "no_coe_file_loaded",
|
141 |
|
|
c_write_mode_a => "WRITE_FIRST",
|
142 |
|
|
c_mux_pipeline_stages => 0,
|
143 |
|
|
c_has_mem_output_regs_b => 0,
|
144 |
|
|
c_has_mem_output_regs_a => 0,
|
145 |
|
|
c_load_init_file => 0,
|
146 |
|
|
c_xdevicefamily => "virtex6",
|
147 |
|
|
c_write_depth_b => 4,
|
148 |
|
|
c_write_depth_a => 64,
|
149 |
|
|
c_has_rstb => 0,
|
150 |
|
|
c_has_rsta => 0,
|
151 |
|
|
c_has_mux_output_regs_b => 0,
|
152 |
|
|
c_inita_val => "0",
|
153 |
|
|
c_has_mux_output_regs_a => 0,
|
154 |
|
|
c_addra_width => 6,
|
155 |
|
|
c_addrb_width => 6,
|
156 |
|
|
c_default_data => "0",
|
157 |
|
|
c_use_ecc => 0,
|
158 |
|
|
c_algorithm => 1,
|
159 |
|
|
c_disable_warn_bhv_range => 0,
|
160 |
|
|
c_write_width_b => 512,
|
161 |
|
|
c_write_width_a => 32,
|
162 |
|
|
c_read_depth_b => 64,
|
163 |
|
|
c_read_depth_a => 4,
|
164 |
|
|
c_byte_size => 9,
|
165 |
|
|
c_sim_collision_check => "ALL",
|
166 |
|
|
c_common_clk => 0,
|
167 |
|
|
c_wea_width => 1,
|
168 |
|
|
c_has_enb => 0,
|
169 |
|
|
c_web_width => 1,
|
170 |
|
|
c_has_ena => 0,
|
171 |
|
|
c_use_byte_web => 0,
|
172 |
|
|
c_use_byte_wea => 0,
|
173 |
|
|
c_rst_priority_b => "CE",
|
174 |
|
|
c_rst_priority_a => "CE",
|
175 |
3 |
JonasDC |
c_use_default_data => 0
|
176 |
|
|
);
|
177 |
2 |
JonasDC |
-- synthesis translate_on
|
178 |
3 |
JonasDC |
begin
|
179 |
2 |
JonasDC |
-- synthesis translate_off
|
180 |
3 |
JonasDC |
U0 : wrapped_operand_dp
|
181 |
|
|
port map (
|
182 |
|
|
clka => clka,
|
183 |
|
|
wea => wea,
|
184 |
|
|
addra => addra,
|
185 |
|
|
dina => dina,
|
186 |
|
|
douta => douta,
|
187 |
|
|
clkb => clkb,
|
188 |
|
|
web => web,
|
189 |
|
|
addrb => addrb,
|
190 |
|
|
dinb => dinb,
|
191 |
|
|
doutb => doutb
|
192 |
|
|
);
|
193 |
2 |
JonasDC |
-- synthesis translate_on
|
194 |
|
|
|
195 |
3 |
JonasDC |
end operand_dp_a;
|