OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [doc/] [src/] [axi_interface.tex] - Blame information for rev 104

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 87 JonasDC 
\chapter{AXI4-Lite interface}
2 
\section{Structure}
3 
The AXI4-Lite interface for this core acts as a slave to the AXI bus. It only supports the AXI-Lite procotol since there
4 
is no ID reflection of the data transfer and only a 32-bit wide bus is supported. The AXI4-Lite IPcore block contains the
5 
exponentiation core and a control register for the core its control inputs and outputs.
6 
 
7 
\section{Parameters}
8 
This section describes the parameters used to configure the core, only the relevant parameters are discussed. AXI
9 
specific parameters are left to the user to configure. The IP core specific parameters and their respective use are
10 
listed in the table below.
11 
\begin{center}
12 
        \begin{tabular}{|l|p{6.5cm}|c|l|}
13 
                \hline
14 
                \rowcolor{Gray}
15 
                \textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
16 
                \hline
17 
                \multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
18 
                \hline
19 103 JonasDC 
                \verb|C_FIFO_AW| & address width of the generic FIFO pointers, FIFO size is equal to $2^{C\_FIFO\_AW} $. & integer &    7 \bigstrut\\
20 
                                                 & only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"|  & & \\
21 87 JonasDC 
                \hline
22 
                \verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
23 
                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
24 
                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
25 
                                                & \verb|"asym"| : use asymmetric RAMs & & \\
26 
                                                & (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
27 
                \hline
28 
                \verb|C_FPGA_MAN| & device manufacturer: & string & \verb|"xilinx"| \\
29 
                                                & \verb|"xilinx"| or \verb|"altera"| &  &  \bigstrut\\
30 
                \hline
31 
                \verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
32 
                \hline
33 
                \verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
34 
                \hline
35 
                \multicolumn{4}{|l|}{\textit{\textbf{Multiplier configuration}}} \\
36 
                \hline
37 
                \verb|C_NR_BITS_TOTAL| & total width of the multiplier in bits & integer & 1536\bigstrut\\
38 
                \hline
39 
                \verb|C_NR_STAGES_TOTAL| & total number of stages in the pipeline & integer & 96\bigstrut\\
40 
                \hline
41 
                \verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
42 
                \hline
43 
                \verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
44 
                \hline
45 
        \end{tabular}%
46 
\end{center}
47 
%\newline
48 
\newpage
49 
The IP core's memory space is organised in a fixed structure as show in Figure~\ref{AXImemstructure}. Only the upper 17
50 
bits (31:15) of the base address can be chosen freely, the lower bits must be 0. So the \verb|C_BASEADDR| parameter must end
51 
in 0xXXXX0000 or 0xXXXX8000 in hexadecimal representation. The core's memory space must have a minimum width of 28K byte for
52 
all registers to be accessible.
53 
\begin{figure}[H]
54 
\centering
55 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=5cm]{pictures/axi_mem.pdf}
56 
\caption{AXI4-Lite IP core memory structure}
57 
\label{AXImemstructure}
58 
\end{figure}
59 
 
60 
There are 4 parameters to configure the multiplier. These values define the width of the multiplier operands and the
61 
number of pipeline stages. If \verb|C_SPLIT_PIPELINE| is false, only operands with a width of\\\verb|C_NR_BITS_TOTAL| are
62 
valid. Else if \verb|C_SPLIT_PIPELINE| is true, 3 operand widths can be supported:
63 
\begin{itemize}
64 
  \item the length of the full pipeline ($C\_NR\_BITS\_TOTAL$)
65 
  \item the length of the lower pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot C\_NR\_STAGES\_LOW $)
66 
  \item the length of the higher pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot (C\_NR\_STAGES\_TOTAL - C\_NR\_STAGES\_LOW$)
67 
\end{itemize}
68 
 
69 
\section{IO ports}
70 
\begin{tabular}{|l|c|c|l|}
71 
        \hline
72 
        \rowcolor{Gray}
73 
        \textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \\
74 
        \hline
75 
        \multicolumn{4}{|l|}{\textit{\textbf{AXI4-Lite bus connections}}} \\
76 
        \hline
77 
        \verb|S_AXI_ACLK| & 1     & in & see note 1 \\
78 
        \hline
79 
        \verb|S_AXI_ARESETN| & 1     & in & see note 1 \\
80 
        \hline
81 
        \verb|S_AXI_AWADDR| & 32    & in & see note 1 \\
82 
        \hline
83 
        \verb|S_AXI_AWVALID| & 1     & in & see note 1 \\
84 
        \hline
85 
        \verb|S_AXI_AWREADY| & 1     & out & see note 1 \\
86 
        \hline
87 
        \verb|S_AXI_WDATA| & 32     & in & see note 1 \\
88 
        \hline
89 
        \verb|S_AXI_WVALID| & 1     & in & see note 1 \\
90 
        \hline
91 
        \verb|S_AXI_WREADY| & 1     & out & see note 1 \\
92 
        \hline
93 
        \verb|S_AXI_WSTRB| & 4     & in & see note 1 \\
94 
        \hline
95 
        \verb|S_AXI_BVALID| & 1    & out & see note 1 \\
96 
        \hline
97 
        \verb|S_AXI_BREADY| & 1     & in & see note 1 \\
98 
        \hline
99 
        \verb|S_AXI_BRESP| & 2     & out & see note 1 \\
100 
        \hline
101 
        \verb|S_AXI_ARADDR| & 32     & in & see note 1 \\
102 
        \hline
103 
        \verb|S_AXI_ARVALID| & 1     & in & see note 1 \\
104 
        \hline
105 
        \verb|S_AXI_ARREADY| & 1     & out & see note 1 \\
106 
        \hline
107 
        \verb|S_AXI_RDATA| & 32     & out & see note 1 \\
108 
        \hline
109 
        \verb|S_AXI_RVALID| & 1    & out & see note 1 \\
110 
        \hline
111 
        \verb|S_AXI_RREADY| & 1     & in & see note 1 \\
112 
        \hline
113 
        \verb|S_AXI_RRESP| & 2     & out & see note 1 \\
114 
        \hline
115 
        \multicolumn{4}{|l|}{\textit{\textbf{Core signals}}} \\
116 
        \hline
117 
        \verb|IntrEvent| & 1     & out   & core interrupt signal \\
118 
        \hline
119 
        \verb|calc_time| & 1     & out   & is high when core is performing a multiplication, for monitoring \\
120 
        \hline
121 
\end{tabular}%
122 
\newline \newline
123 
\textbf{Note 1:} The function and timing of this signal is defined in the AMBA\textsuperscript{\textregistered} AXI Protocol Version: 2.0 Specification.
124 
 
125 
\section{Registers}
126 
This section specifies the IP core internal registers as seen from the software. These registers allow to control and
127 
configure the modular exponentiation core and to read out its state. All addresses given in this table are relative to the
128 
IP core's base address.\\
129 
\newline
130 
% Table generated by Excel2LaTeX
131 
\begin{tabular}{|l|c|c|c|l|}
132 
\hline
133 
\rowcolor{Gray}
134 
\textbf{Name} & \textbf{Width} & \textbf{Address} & \textbf{Access} & \textbf{Description} \bigstrut\\
135 
\hline
136 
control register                & 32 & 0x6000 & RW      & multiplier core control signals and \bigstrut[t]\\
137 
                                                &       &               &               & interrupt flags register\bigstrut[b]\\
138 
\hline
139 
\end{tabular}%
140 
\newpage
141 
\subsection{Control register (offset = 0x6000)}
142 
This registers holds the control inputs to the multiplier core and the interrupt flags.\\
143 
\begin{figure}[H]
144 
\centering
145 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/axi_control_reg.pdf}
146 
\caption{control register}
147 
\end{figure}
148 
 
149 
\begin{tabular}{ll}
150 
bits 31-30      & P\_SEL : selects which pipeline part to be active\\
151 
                        & $\bullet$  "01" lower pipeline part\\
152 
                        & $\bullet$  "10" higher pipeline part\\
153 
                        & $\bullet$  "11" full pipeline\\
154 
                        & $\bullet$  "00" invalid selection\\
155 
                        &\\
156 
bits 29-28      & DEST\_OP : selects the operand (0-3) to store the result in for a single\\
157 
                        & Montgomery multiplication\footnotemark\\
158 
                        &\\
159 
bits 27-26      & X\_OP : selects the x operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
160 
                        &\\
161 
bits 25-24      & Y\_OP : selects the y operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
162 
                        &\\
163 
bit 23          & START : starts the multiplication/exponentiation\\
164 
                        &\\
165 
bit 22          & EXP/M : selects the operating mode\\
166 
                        & $\bullet$  "0" single Montgomery multiplications\\
167 
                        & $\bullet$  "1" simultaneous exponentiations\\
168 
                        &\\
169 88 JonasDC 
bit 21          & unimplemented\\
170 
                        &\\
171 
bit 20          & RESET : active high reset for the core\footnotemark[2]\\
172 87 JonasDC 
                        &\\
173 88 JonasDC 
bits 19-16      & unimplemented\\
174 87 JonasDC 
                        &\\
175 
bit 15          & READY : ready flag, "1" when multiplication is done\\
176 
                        & must be cleared in software\\
177 
                        &\\
178 
bit 14          & MEM\_ERR : memory collision error flag, "1" when write error occurred\\
179 
                        & must be cleared in software\\
180 
                        &\\
181 
bit 13          & FIFO\_FULL : FIFO full error flag, "1" when FIFO is full\\
182 
                        & must be cleared in software\\
183 
                        &\\
184 
bit 12          & FIFO\_ERR : FIFO write/push error flag, "1" when push error occurred\\
185 
                        & must be cleared in software\\
186 
                        &\\
187 
bits 11-0       & unimplemented\\
188 
                        &\\
189 
\end{tabular}
190 
\newline
191 
\newline
192 
\footnotetext[1]{when the core is running in exponentiation mode, the parameters DEST\_OP, X\_OP and Y\_OP have no effect.}
193 
\footnotetext[2]{The reset affects the full IP core, thus resetting the control register, interrupt controller,
194 
the multiplier pipeline, FIFO and control logic of the core.}
195 
\newpage
196 
\section{Interfacing the core's RAM}
197 
Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
198 
address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
199 
supported due to the structure of the RAM.
200 
 
201 
\section{Handling interrupts}
202 92 JonasDC 
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to determine the source of the interrupt by reading out the interrupt flags of the control register. After handling the interrupt, the appropriate flag must be cleared by user. A reset or core start operation also resets the flags. The interrupt signal is high level sensitive.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.