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\chapter{AXI4-Lite interface}
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\section{Structure}
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The AXI4-Lite interface for this core acts as a slave to the AXI bus. It only supports the AXI-Lite procotol since there
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is no ID reflection of the data transfer and only a 32-bit wide bus is supported. The AXI4-Lite IPcore block contains the
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exponentiation core and a control register for the core its control inputs and outputs.
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\section{Parameters}
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This section describes the parameters used to configure the core, only the relevant parameters are discussed. AXI
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specific parameters are left to the user to configure. The IP core specific parameters and their respective use are
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listed in the table below.
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\begin{center}
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        \begin{tabular}{|l|p{6.5cm}|c|l|}
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                \hline
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                \rowcolor{Gray}
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                \textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
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                \hline
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                \multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
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                \hline
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                \verb|C_FIFO_DEPTH| & depth of the generic FIFO, only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"|  & integer & 32 \bigstrut\\
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                \hline
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                \verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
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                                                        & \verb|"xil_prim"| : use xilinx primitives & & \\
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                                                & \verb|"generic"| : use general 32-bit RAMs & & \\
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                                                & \verb|"asym"| : use asymmetric RAMs & & \\
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                                                & (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
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                \hline
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                \verb|C_FPGA_MAN| & device manufacturer: & string & \verb|"xilinx"| \\
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                                                & \verb|"xilinx"| or \verb|"altera"| &  &  \bigstrut\\
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                \hline
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                \verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
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                \hline
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                \verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
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                \hline
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                \multicolumn{4}{|l|}{\textit{\textbf{Multiplier configuration}}} \\
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                \hline
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                \verb|C_NR_BITS_TOTAL| & total width of the multiplier in bits & integer & 1536\bigstrut\\
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                \hline
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                \verb|C_NR_STAGES_TOTAL| & total number of stages in the pipeline & integer & 96\bigstrut\\
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                \hline
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                \verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
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                \hline
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                \verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
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                \hline
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        \end{tabular}%
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\end{center}
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%\newline
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\newpage
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The IP core's memory space is organised in a fixed structure as show in Figure~\ref{AXImemstructure}. Only the upper 17
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bits (31:15) of the base address can be chosen freely, the lower bits must be 0. So the \verb|C_BASEADDR| parameter must end
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in 0xXXXX0000 or 0xXXXX8000 in hexadecimal representation. The core's memory space must have a minimum width of 28K byte for
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all registers to be accessible.
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\begin{figure}[H]
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\centering
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=5cm]{pictures/axi_mem.pdf}
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\caption{AXI4-Lite IP core memory structure}
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\label{AXImemstructure}
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\end{figure}
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There are 4 parameters to configure the multiplier. These values define the width of the multiplier operands and the
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number of pipeline stages. If \verb|C_SPLIT_PIPELINE| is false, only operands with a width of\\\verb|C_NR_BITS_TOTAL| are
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valid. Else if \verb|C_SPLIT_PIPELINE| is true, 3 operand widths can be supported:
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\begin{itemize}
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  \item the length of the full pipeline ($C\_NR\_BITS\_TOTAL$)
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  \item the length of the lower pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot C\_NR\_STAGES\_LOW $)
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  \item the length of the higher pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot (C\_NR\_STAGES\_TOTAL - C\_NR\_STAGES\_LOW$)
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\end{itemize}
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\section{IO ports}
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\begin{tabular}{|l|c|c|l|}
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        \hline
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        \rowcolor{Gray}
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        \textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \\
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        \hline
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        \multicolumn{4}{|l|}{\textit{\textbf{AXI4-Lite bus connections}}} \\
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        \hline
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        \verb|S_AXI_ACLK| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_ARESETN| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_AWADDR| & 32    & in & see note 1 \\
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        \hline
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        \verb|S_AXI_AWVALID| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_AWREADY| & 1     & out & see note 1 \\
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        \hline
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        \verb|S_AXI_WDATA| & 32     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_WVALID| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_WREADY| & 1     & out & see note 1 \\
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        \hline
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        \verb|S_AXI_WSTRB| & 4     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_BVALID| & 1    & out & see note 1 \\
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        \hline
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        \verb|S_AXI_BREADY| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_BRESP| & 2     & out & see note 1 \\
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        \hline
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        \verb|S_AXI_ARADDR| & 32     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_ARVALID| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_ARREADY| & 1     & out & see note 1 \\
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        \hline
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        \verb|S_AXI_RDATA| & 32     & out & see note 1 \\
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        \hline
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        \verb|S_AXI_RVALID| & 1    & out & see note 1 \\
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        \hline
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        \verb|S_AXI_RREADY| & 1     & in & see note 1 \\
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        \hline
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        \verb|S_AXI_RRESP| & 2     & out & see note 1 \\
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        \hline
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        \multicolumn{4}{|l|}{\textit{\textbf{Core signals}}} \\
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        \hline
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        \verb|IntrEvent| & 1     & out   & core interrupt signal \\
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        \hline
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        \verb|calc_time| & 1     & out   & is high when core is performing a multiplication, for monitoring \\
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        \hline
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\end{tabular}%
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\newline \newline
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\textbf{Note 1:} The function and timing of this signal is defined in the AMBA\textsuperscript{\textregistered} AXI Protocol Version: 2.0 Specification.
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\section{Registers}
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This section specifies the IP core internal registers as seen from the software. These registers allow to control and
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configure the modular exponentiation core and to read out its state. All addresses given in this table are relative to the
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IP core's base address.\\
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\newline
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% Table generated by Excel2LaTeX
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\begin{tabular}{|l|c|c|c|l|}
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\hline
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\rowcolor{Gray}
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\textbf{Name} & \textbf{Width} & \textbf{Address} & \textbf{Access} & \textbf{Description} \bigstrut\\
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\hline
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control register                & 32 & 0x6000 & RW      & multiplier core control signals and \bigstrut[t]\\
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                                                &       &               &               & interrupt flags register\bigstrut[b]\\
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\hline
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\end{tabular}%
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\newpage
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\subsection{Control register (offset = 0x6000)}
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This registers holds the control inputs to the multiplier core and the interrupt flags.\\
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\begin{figure}[H]
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\centering
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\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/axi_control_reg.pdf}
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\caption{control register}
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\end{figure}
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\begin{tabular}{ll}
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bits 31-30      & P\_SEL : selects which pipeline part to be active\\
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                        & $\bullet$  "01" lower pipeline part\\
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                        & $\bullet$  "10" higher pipeline part\\
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                        & $\bullet$  "11" full pipeline\\
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                        & $\bullet$  "00" invalid selection\\
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                        &\\
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bits 29-28      & DEST\_OP : selects the operand (0-3) to store the result in for a single\\
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                        & Montgomery multiplication\footnotemark\\
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                        &\\
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bits 27-26      & X\_OP : selects the x operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
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                        &\\
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bits 25-24      & Y\_OP : selects the y operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
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                        &\\
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bit 23          & START : starts the multiplication/exponentiation\\
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                        &\\
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bit 22          & EXP/M : selects the operating mode\\
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                        & $\bullet$  "0" single Montgomery multiplications\\
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                        & $\bullet$  "1" simultaneous exponentiations\\
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                        &\\
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bit 21          & RESET : active high reset for the core\footnotemark[2]\\
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                        &\\
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bits 20-16      & unimplemented\\
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                        &\\
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bit 15          & READY : ready flag, "1" when multiplication is done\\
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                        & must be cleared in software\\
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                        &\\
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bit 14          & MEM\_ERR : memory collision error flag, "1" when write error occurred\\
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                        & must be cleared in software\\
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                        &\\
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bit 13          & FIFO\_FULL : FIFO full error flag, "1" when FIFO is full\\
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                        & must be cleared in software\\
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                        &\\
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bit 12          & FIFO\_ERR : FIFO write/push error flag, "1" when push error occurred\\
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                        & must be cleared in software\\
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                        &\\
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bits 11-0       & unimplemented\\
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                        &\\
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\end{tabular}
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\newline
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\newline
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\footnotetext[1]{when the core is running in exponentiation mode, the parameters DEST\_OP, X\_OP and Y\_OP have no effect.}
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\footnotetext[2]{The reset affects the full IP core, thus resetting the control register, interrupt controller,
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the multiplier pipeline, FIFO and control logic of the core.}
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\newpage
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\section{Interfacing the core's RAM}
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Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
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address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
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supported due to the structure of the RAM.
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\section{Handling interrupts}
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When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to
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determine the source of the interrupt by reading out the interrupt flag of the control register.

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