| 1 |
47 |
JonasDC |
\chapter{PLB interface}
|
| 2 |
|
|
\section{Structure}
|
| 3 |
|
|
The Processor Local Bus interface for this core is structured as in Figure~\ref{PLBstructure}. The core acts as a slave
|
| 4 |
|
|
to the PLB bus. The PLB v4.6 Slave\cite{XilinxPLB} logic translates the interface to a lower level IP Interconnect
|
| 5 |
|
|
Interface (IPIC).
|
| 6 |
|
|
This is then used to connect the core internal components to. The user logic contains the exponentiation core and the
|
| 7 |
|
|
control register for the core its control inputs and outputs. An internal interrupt controller\cite{XilinxIntr} handles
|
| 8 |
|
|
the outgoing interrupt requests and a software reset module is provided to be able to reset the IP core at runtime. This
|
| 9 |
|
|
bus interface is created using the ``Create or Import Peripheral'' wizard from Xilinx Platform Studio.\\
|
| 10 |
|
|
\begin{figure}[H]
|
| 11 |
|
|
\centering
|
| 12 |
|
|
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=7cm]{pictures/plb_interface.pdf}
|
| 13 |
|
|
\caption{PLB IP core structure}
|
| 14 |
|
|
\label{PLBstructure}
|
| 15 |
|
|
\end{figure}
|
| 16 |
|
|
|
| 17 |
|
|
\newpage
|
| 18 |
|
|
\section{Parameters}
|
| 19 |
|
|
This section describes the parameters used to configure the core, only the relevant parameters are discussed. PLB
|
| 20 |
|
|
specific parameters are left to the user to configure. The IP core specific parameters and their respective use are
|
| 21 |
|
|
listed in the table below.
|
| 22 |
|
|
\begin{center}
|
| 23 |
|
|
\begin{tabular}{|l|p{6.5cm}|c|l|}
|
| 24 |
|
|
\hline
|
| 25 |
|
|
\rowcolor{Gray}
|
| 26 |
|
|
\textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
|
| 27 |
|
|
\hline
|
| 28 |
78 |
JonasDC |
\multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
|
| 29 |
47 |
JonasDC |
\hline
|
| 30 |
103 |
JonasDC |
\verb|C_FIFO_AW| & address width of the generic FIFO pointers, FIFO size is equal to $2^{C\_FIFO\_AW} $. & integer & 7 \bigstrut\\
|
| 31 |
|
|
& only applicable if \verb|C_MEM_STYLE| = \verb|"generic"| or \verb|"asym"| & & \\
|
| 32 |
78 |
JonasDC |
\hline
|
| 33 |
|
|
\verb|C_MEM_STYLE| & the memory structure to use for the RAM, choice between 3 options: & string & \verb|"generic"| \bigstrut\\
|
| 34 |
|
|
& \verb|"xil_prim"| : use xilinx primitives & & \\
|
| 35 |
|
|
& \verb|"generic"| : use general 32-bit RAMs & & \\
|
| 36 |
|
|
& \verb|"asym"| : use asymmetric RAMs & & \\
|
| 37 |
|
|
& (For more information see \ref{subsec:RAM_and_FIFO}) & & \bigstrut[b] \\
|
| 38 |
|
|
\hline
|
| 39 |
87 |
JonasDC |
\verb|C_FPGA_MAN| & device manufacturer: & string & \verb|"xilinx"| \\
|
| 40 |
78 |
JonasDC |
& \verb|"xilinx"| or \verb|"altera"| & & \bigstrut\\
|
| 41 |
|
|
\hline
|
| 42 |
47 |
JonasDC |
\verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 43 |
|
|
\hline
|
| 44 |
|
|
\verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 45 |
|
|
\hline
|
| 46 |
|
|
\verb|C_M_BASEADDR| & base address for the modulus memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 47 |
|
|
\hline
|
| 48 |
|
|
\verb|C_M_HIGHADDR| & high address for the modulus memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 49 |
|
|
\hline
|
| 50 |
|
|
\verb|C_OP0_BASEADDR| & base address for the operand 0 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 51 |
|
|
\hline
|
| 52 |
|
|
\verb|C_OP0_HIGHADDR| & high address for the operand 0 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 53 |
|
|
\hline
|
| 54 |
|
|
\verb|C_OP1_BASEADDR| & base address for the operand 1 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 55 |
|
|
\hline
|
| 56 |
|
|
\verb|C_OP1_HIGHADDR| & high address for the operand 1 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 57 |
|
|
\hline
|
| 58 |
|
|
\verb|C_OP2_BASEADDR| & base address for the operand 2 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 59 |
|
|
\hline
|
| 60 |
|
|
\verb|C_OP2_HIGHADDR| & high address for the operand 2 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 61 |
|
|
\hline
|
| 62 |
|
|
\verb|C_OP3_BASEADDR| & base address for the operand 3 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 63 |
|
|
\hline
|
| 64 |
|
|
\verb|C_OP3_HIGHADDR| & high address for the operand 3 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 65 |
|
|
\hline
|
| 66 |
|
|
\verb|C_FIFO_BASEADDR| & base address for the FIFO memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
|
| 67 |
|
|
\hline
|
| 68 |
|
|
\verb|C_FIFO_HIGHADDR| & high address for the FIFO memory space & std\_logic\_vector & X"00000000" \bigstrut\\
|
| 69 |
|
|
\hline
|
| 70 |
|
|
\multicolumn{4}{|l|}{\textit{\textbf{Multiplier configuration}}} \\
|
| 71 |
|
|
\hline
|
| 72 |
|
|
\verb|C_NR_BITS_TOTAL| & total width of the multiplier in bits & integer & 1536\bigstrut\\
|
| 73 |
|
|
\hline
|
| 74 |
|
|
\verb|C_NR_STAGES_TOTAL| & total number of stages in the pipeline & integer & 96\bigstrut\\
|
| 75 |
|
|
\hline
|
| 76 |
|
|
\verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
|
| 77 |
|
|
\hline
|
| 78 |
|
|
\verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
|
| 79 |
|
|
\hline
|
| 80 |
|
|
\end{tabular}%
|
| 81 |
|
|
\end{center}
|
| 82 |
|
|
%\newline
|
| 83 |
|
|
|
| 84 |
|
|
The complete IP core's memory space can be controlled. As can be seen, the operand, modulus and FIFO memory space can be
|
| 85 |
|
|
chosen separately from the IP core's memory space which hold the registers for control, software reset and interrupt
|
| 86 |
|
|
control. The core's memory space must have a minimum width of 1K byte for all registers to be accessible. For the FIFO
|
| 87 |
|
|
memory space, a minimum width of 4 byte is needed, since the FIFO is only 32 bit wide. The memory space width for the
|
| 88 |
|
|
operands and the modulus need a minimum width equal to the total multiplier width.\\
|
| 89 |
|
|
|
| 90 |
|
|
There are 4 parameters to configure the multiplier. These values define the width of the multiplier operands and the
|
| 91 |
|
|
number of pipeline stages. If \verb|C_SPLIT_PIPELINE| is false, only operands with a width of\\\verb|C_NR_BITS_TOTAL| are
|
| 92 |
|
|
valid. Else if \verb|C_SPLIT_PIPELINE| is true, 3 operand widths can be supported:
|
| 93 |
|
|
\begin{itemize}
|
| 94 |
|
|
\item the length of the full pipeline ($C\_NR\_BITS\_TOTAL$)
|
| 95 |
|
|
\item the length of the lower pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot C\_NR\_STAGES\_LOW $)
|
| 96 |
|
|
\item the length of the higher pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot (C\_NR\_STAGES\_TOTAL - C\_NR\_STAGES\_LOW$)
|
| 97 |
|
|
\end{itemize}
|
| 98 |
|
|
|
| 99 |
|
|
\section{IO ports}
|
| 100 |
|
|
\begin{tabular}{|l|c|c|l|}
|
| 101 |
|
|
\hline
|
| 102 |
|
|
\rowcolor{Gray}
|
| 103 |
|
|
\textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \\
|
| 104 |
|
|
\hline
|
| 105 |
|
|
\multicolumn{4}{|l|}{\textit{\textbf{PLB bus connections}}} \\
|
| 106 |
|
|
\hline
|
| 107 |
|
|
\verb|SPLB_Clk| & 1 & in & see note 1 \\
|
| 108 |
|
|
\hline
|
| 109 |
|
|
\verb|SPLB_Rst| & 1 & in & see note 1 \\
|
| 110 |
|
|
\hline
|
| 111 |
|
|
\verb|PLB_ABus| & 32 & in & see note 1 \\
|
| 112 |
|
|
\hline
|
| 113 |
|
|
\verb|PLB_PAValid| & 1 & in & see note 1 \\
|
| 114 |
|
|
\hline
|
| 115 |
|
|
\verb|PLB_masterID| & 3 & in & see note 1 \\
|
| 116 |
|
|
\hline
|
| 117 |
|
|
\verb|PLB_RNW| & 1 & in & see note 1 \\
|
| 118 |
|
|
\hline
|
| 119 |
|
|
\verb|PLB_BE| & 4 & in & see note 1 \\
|
| 120 |
|
|
\hline
|
| 121 |
|
|
\verb|PLB_size| & 4 & in & see note 1 \\
|
| 122 |
|
|
\hline
|
| 123 |
|
|
\verb|PLB_type| & 3 & in & see note 1 \\
|
| 124 |
|
|
\hline
|
| 125 |
|
|
\verb|PLB_wrDBus| & 32 & in & see note 1 \\
|
| 126 |
|
|
\hline
|
| 127 |
|
|
\verb|Sl_addrAck| & 1 & out & see note 1 \\
|
| 128 |
|
|
\hline
|
| 129 |
|
|
\verb|Sl_SSize| & 2 & out & see note 1 \\
|
| 130 |
|
|
\hline
|
| 131 |
|
|
\verb|Sl_wait| & 1 & out & see note 1 \\
|
| 132 |
|
|
\hline
|
| 133 |
|
|
\verb|Sl_rearbitrate| & 1 & out & see note 1 \\
|
| 134 |
|
|
\hline
|
| 135 |
|
|
\verb|Sl_wrDack| & 1 & out & see note 1 \\
|
| 136 |
|
|
\hline
|
| 137 |
|
|
\verb|Sl_wrComp| & 1 & out & see note 1 \\
|
| 138 |
|
|
\hline
|
| 139 |
|
|
\verb|Sl_rdBus| & 32 & out & see note 1 \\
|
| 140 |
|
|
\hline
|
| 141 |
|
|
\verb|Sl_MBusy| & 8 & out & see note 1 \\
|
| 142 |
|
|
\hline
|
| 143 |
|
|
\verb|Sl_MWrErr| & 8 & out & see note 1 \\
|
| 144 |
|
|
\hline
|
| 145 |
|
|
\verb|Sl_MRdErr| & 8 & out & see note 1 \\
|
| 146 |
|
|
\hline
|
| 147 |
|
|
\multicolumn{4}{|l|}{\textit{\textbf{unused PLB signals}}} \\
|
| 148 |
|
|
\hline
|
| 149 |
|
|
\verb|PLB_UABus| & 32 & in & see note 1 \\
|
| 150 |
|
|
\hline
|
| 151 |
|
|
\verb|PLB_SAValid| & 1 & in & see note 1 \\
|
| 152 |
|
|
\hline
|
| 153 |
|
|
\verb|PLB_rdPrim| & 1 & in & see note 1 \\
|
| 154 |
|
|
\hline
|
| 155 |
|
|
\verb|PLB_wrPrim| & 1 & in & see note 1 \\
|
| 156 |
|
|
\hline
|
| 157 |
|
|
\verb|PLB_abort| & 1 & in & see note 1 \\
|
| 158 |
|
|
\hline
|
| 159 |
|
|
\verb|PLB_busLock| & 1 & in & see note 1 \\
|
| 160 |
|
|
\hline
|
| 161 |
|
|
\verb|PLB_MSize| & 2 & in & see note 1 \\
|
| 162 |
|
|
\hline
|
| 163 |
|
|
\verb|PLB_TAttribute| & 16 & in & see note 1 \\
|
| 164 |
|
|
\hline
|
| 165 |
|
|
\verb|PLB_lockerr| & 1 & in & see note 1 \\
|
| 166 |
|
|
\hline
|
| 167 |
|
|
\verb|PLB_wrBurst| & 1 & in & see note 1 \\
|
| 168 |
|
|
\hline
|
| 169 |
|
|
\verb|PLB_rdBurst| & 1 & in & see note 1 \\
|
| 170 |
|
|
\hline
|
| 171 |
|
|
\verb|PLB_wrPendReq| & 1 & in & see note 1 \\
|
| 172 |
|
|
\hline
|
| 173 |
|
|
\verb|PLB_rdPendReq| & 1 & in & see note 1 \\
|
| 174 |
|
|
\hline
|
| 175 |
|
|
\verb|PLB_rdPendPri| & 2 & in & see note 1 \\
|
| 176 |
|
|
\hline
|
| 177 |
|
|
\verb|PLB_wrPendPri| & 2 & in & see note 1 \\
|
| 178 |
|
|
\hline
|
| 179 |
|
|
\verb|PLB_reqPri| & 2 & in & see note 1 \\
|
| 180 |
|
|
\hline
|
| 181 |
|
|
\verb|Sl_wrBTerm| & 1 & out & see note 1 \\
|
| 182 |
|
|
\hline
|
| 183 |
|
|
\verb|Sl_rdWdAddr| & 4 & out & see note 1 \\
|
| 184 |
|
|
\hline
|
| 185 |
|
|
\verb|Sl_rdBTerm| & 1 & out & see note 1 \\
|
| 186 |
|
|
\hline
|
| 187 |
|
|
\verb|Sl_MIRQ| & 8 & out & see note 1 \\
|
| 188 |
|
|
\hline
|
| 189 |
|
|
\multicolumn{4}{|l|}{\textit{\textbf{Core signals}}} \\
|
| 190 |
|
|
\hline
|
| 191 |
|
|
\verb|IP2INTC_Irpt| & 1 & out & core interrupt signal \\
|
| 192 |
|
|
\hline
|
| 193 |
|
|
\verb|calc_time| & 1 & out & is high when core is performing a multiplication, for monitoring \\
|
| 194 |
|
|
\hline
|
| 195 |
|
|
\end{tabular}%
|
| 196 |
|
|
\newline \newline
|
| 197 |
|
|
\textbf{Note 1:} The function and timing of this signal is defined in the IBM\textsuperscript{\textregistered} 128-Bit Processor Local Bus Architecture Specification
|
| 198 |
|
|
Version 4.6.
|
| 199 |
|
|
|
| 200 |
|
|
\section{Registers}
|
| 201 |
|
|
This section specifies the IP core internal registers as seen from the software. These registers allow to control and
|
| 202 |
|
|
configure the modular exponentiation core and to read out its state. All addresses given in this table are relative to the
|
| 203 |
|
|
IP core's base address.\\
|
| 204 |
|
|
\newline
|
| 205 |
|
|
% Table generated by Excel2LaTeX
|
| 206 |
|
|
\begin{tabular}{|l|c|c|c|l|}
|
| 207 |
|
|
\hline
|
| 208 |
|
|
\rowcolor{Gray}
|
| 209 |
|
|
\textbf{Name} & \textbf{Width} & \textbf{Address} & \textbf{Access} & \textbf{Description} \bigstrut\\
|
| 210 |
|
|
\hline
|
| 211 |
|
|
control register & 32 & 0x0000 & RW & multiplier core control signals and \bigstrut[t]\\
|
| 212 |
|
|
& & & & interrupt flags register\bigstrut[b]\\
|
| 213 |
|
|
\hline
|
| 214 |
|
|
software reset & 32 & 0x0100 & W & soft reset for the IP core \bigstrut\\
|
| 215 |
|
|
\hline
|
| 216 |
|
|
\multicolumn{5}{|l|}{\textbf{\textit{Interrupt controller registers}}} \bigstrut\\
|
| 217 |
|
|
\hline
|
| 218 |
|
|
global interrupt enable register & 32 & 0x021C & RW & global interrupt enable for the IP core \bigstrut[t]\\
|
| 219 |
|
|
interrupt status register & 32 & 0x0220 & R & register for interrupt status flags\\
|
| 220 |
|
|
interrupt enable register & 32 & 0x0228 & RW & register to enable individual IP core interrupts \bigstrut[b]\\
|
| 221 |
|
|
\hline
|
| 222 |
|
|
\end{tabular}%
|
| 223 |
|
|
|
| 224 |
|
|
\newpage
|
| 225 |
|
|
\subsection{Control register (offset = 0x0000)}
|
| 226 |
|
|
This registers holds the control inputs to the multiplier core and the interrupt flags.\\
|
| 227 |
|
|
\begin{figure}[H]
|
| 228 |
|
|
\centering
|
| 229 |
|
|
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_control_reg.pdf}
|
| 230 |
|
|
\caption{control register}
|
| 231 |
|
|
\end{figure}
|
| 232 |
|
|
|
| 233 |
|
|
|
| 234 |
|
|
\begin{tabular}{ll}
|
| 235 |
|
|
bits 0-1 & P\_SEL : selects which pipeline part to be active\\
|
| 236 |
|
|
& $\bullet$ "01" lower pipeline part\\
|
| 237 |
|
|
& $\bullet$ "10" higher pipeline part\\
|
| 238 |
|
|
& $\bullet$ "11" full pipeline\\
|
| 239 |
|
|
& $\bullet$ "00" invalid selection\\
|
| 240 |
|
|
&\\
|
| 241 |
|
|
bits 2-3 & DEST\_OP : selects the operand (0-3) to store the result in for a single\\
|
| 242 |
|
|
& Montgomery multiplication\footnotemark\\
|
| 243 |
|
|
&\\
|
| 244 |
|
|
bits 4-5 & X\_OP : selects the x operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
|
| 245 |
|
|
&\\
|
| 246 |
|
|
bits 6-7 & Y\_OP : selects the y operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
|
| 247 |
|
|
&\\
|
| 248 |
|
|
bit 8 & START : starts the multiplication/exponentiation\\
|
| 249 |
|
|
&\\
|
| 250 |
|
|
bit 9 & EXP/M : selects the operating mode\\
|
| 251 |
|
|
& $\bullet$ "0" single Montgomery multiplications\\
|
| 252 |
|
|
& $\bullet$ "1" simultaneous exponentiations\\
|
| 253 |
|
|
&\\
|
| 254 |
|
|
bits 10-15 & unimplemented\\
|
| 255 |
|
|
&\\
|
| 256 |
|
|
bit 16 & READY : ready flag, "1" when multiplication is done\\
|
| 257 |
|
|
& must be cleared in software\\
|
| 258 |
|
|
&\\
|
| 259 |
|
|
bit 17 & MEM\_ERR : memory collision error flag, "1" when write error occurred\\
|
| 260 |
|
|
& must be cleared in software\\
|
| 261 |
|
|
&\\
|
| 262 |
|
|
bit 18 & FIFO\_FULL : FIFO full error flag, "1" when FIFO is full\\
|
| 263 |
|
|
& must be cleared in software\\
|
| 264 |
|
|
&\\
|
| 265 |
|
|
bit 19 & FIFO\_ERR : FIFO write/push error flag, "1" when push error occurred\\
|
| 266 |
|
|
& must be cleared in software\\
|
| 267 |
|
|
&\\
|
| 268 |
|
|
bits 20-31 & unimplemented\\
|
| 269 |
|
|
&\\
|
| 270 |
|
|
\end{tabular}
|
| 271 |
|
|
\newline
|
| 272 |
|
|
\newline
|
| 273 |
|
|
\footnotetext{when the core is running in exponentiation mode, the parameters DEST\_OP, X\_OP and Y\_OP have no effect.}
|
| 274 |
|
|
|
| 275 |
|
|
\newpage
|
| 276 |
|
|
\subsection{Software reset register (offset = 0x0100)}
|
| 277 |
|
|
This is a register with write only access, and provides the possibility to reset the IP core from software by writing
|
| 278 |
|
|
0x0000000A to this address. The reset affects the full IP core, thus resetting the control register, interrupt controller,
|
| 279 |
|
|
the multiplier pipeline, FIFO and control logic of the core.
|
| 280 |
|
|
|
| 281 |
|
|
\subsection{Global interrupt enable register (offset = 0x021C)}
|
| 282 |
|
|
This register contains a single defined bit in the high-order position. The GIE bit enables or disables all interrupts
|
| 283 |
|
|
form the IP core.\\
|
| 284 |
|
|
\begin{figure}[H]
|
| 285 |
|
|
\centering
|
| 286 |
|
|
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_gie_reg.pdf}
|
| 287 |
|
|
\caption{Global interrupt enable register}
|
| 288 |
|
|
\end{figure}
|
| 289 |
|
|
|
| 290 |
|
|
\begin{tabular}{ll}
|
| 291 |
|
|
bit 0 & GIE : Global interrupt enable\\
|
| 292 |
|
|
& $\bullet$ "0" disables all core interrupts\\
|
| 293 |
|
|
& $\bullet$ "1" enables all core interrupts\\
|
| 294 |
|
|
&\\
|
| 295 |
|
|
bits 1-31 & unimplemented\\
|
| 296 |
|
|
&\\
|
| 297 |
|
|
\end{tabular}
|
| 298 |
|
|
|
| 299 |
|
|
\subsection{Interrupt status register (offset = 0x0220)}
|
| 300 |
|
|
Read-only register that contains the status of the core interrupts. Currently there is only one common interrupt from
|
| 301 |
|
|
the core that is asserted when a multiplication/exponentiation is done, FIFO is full, on FIFO push error or memory write
|
| 302 |
|
|
collision.\\
|
| 303 |
|
|
\begin{figure}[H]
|
| 304 |
|
|
\centering
|
| 305 |
|
|
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_is_reg.pdf}
|
| 306 |
|
|
\caption{Interrupt status register}
|
| 307 |
|
|
\end{figure}
|
| 308 |
|
|
|
| 309 |
|
|
\begin{tabular}{ll}
|
| 310 |
|
|
bits 0-30 & unimplemented\\
|
| 311 |
|
|
&\\
|
| 312 |
|
|
bit 31 & CIS : Core interrupt status\\
|
| 313 |
|
|
& is high when interrupt is requested from core\\
|
| 314 |
|
|
&\\
|
| 315 |
|
|
\end{tabular}
|
| 316 |
|
|
|
| 317 |
|
|
\subsection{interrupt enable register (offset = 0x0228)}
|
| 318 |
|
|
This register contains the interrupt enable bits for the respective interrupt bits of the interrupt status register.\\
|
| 319 |
|
|
\begin{figure}[H]
|
| 320 |
|
|
\centering
|
| 321 |
|
|
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_ie_reg.pdf}
|
| 322 |
|
|
\caption{Interrupt enable register}
|
| 323 |
|
|
\end{figure}
|
| 324 |
|
|
\begin{tabular}{ll}
|
| 325 |
|
|
bits 0-30 & unimplemented\\
|
| 326 |
|
|
&\\
|
| 327 |
|
|
bit 31 & CIE : Core interrupt enable\\
|
| 328 |
|
|
& $\bullet$ "0" disable core interrupt\\
|
| 329 |
|
|
& $\bullet$ "1" enable core interrupt\\
|
| 330 |
|
|
&\\
|
| 331 |
|
|
\end{tabular}
|
| 332 |
|
|
|
| 333 |
|
|
\section{Interfacing the core's RAM}
|
| 334 |
|
|
Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
|
| 335 |
|
|
address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
|
| 336 |
|
|
supported due to the structure of the RAM.
|
| 337 |
|
|
|
| 338 |
|
|
\section{Handling interrupts}
|
| 339 |
|
|
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to
|
| 340 |
|
|
determine the source of the interrupt by reading out the interrupt flag of the control register.
|
