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1 47 JonasDC 
\chapter{PLB interface}
2 
\section{Structure}
3 
The Processor Local Bus interface for this core is structured as in Figure~\ref{PLBstructure}. The core acts as a slave
4 
to the PLB bus. The PLB v4.6 Slave\cite{XilinxPLB} logic translates the interface to a lower level IP Interconnect
5 
Interface (IPIC).
6 
This is then used to connect the core internal components to. The user logic contains the exponentiation core and the
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control register for the core its control inputs and outputs. An internal interrupt controller\cite{XilinxIntr} handles
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the outgoing interrupt requests and a software reset module is provided to be able to reset the IP core at runtime. This
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bus interface is created using the ``Create or Import Peripheral'' wizard from Xilinx Platform Studio.\\
10 
\begin{figure}[H]
11 
\centering
12 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=7cm]{pictures/plb_interface.pdf}
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\caption{PLB IP core structure}
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\label{PLBstructure}
15 
\end{figure}
16 
 
17 
\newpage
18 
\section{Parameters}
19 
This section describes the parameters used to configure the core, only the relevant parameters are discussed. PLB
20 
specific parameters are left to the user to configure. The IP core specific parameters and their respective use are
21 
listed in the table below.
22 
\begin{center}
23 
        \begin{tabular}{|l|p{6.5cm}|c|l|}
24 
                \hline
25 
                \rowcolor{Gray}
26 
                \textbf{Name} & \textbf{Description} & \textbf{VHDL Type} &\textbf{Default Value} \bigstrut\\
27 
                \hline
28 
                \multicolumn{4}{|l|}{\textit{\textbf{Memory configuration}}} \\
29 
                \hline
30 
                \verb|C_BASEADDR| & base address for the IP core's memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
31 
                \hline
32 
                \verb|C_HIGHADDR| & high address for the IP core's memory space & std\_logic\_vector & X"00000000" \bigstrut\\
33 
                \hline
34 
                \verb|C_M_BASEADDR| & base address for the modulus memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
35 
                \hline
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                \verb|C_M_HIGHADDR| & high address for the modulus memory space & std\_logic\_vector & X"00000000" \bigstrut\\
37 
                \hline
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                \verb|C_OP0_BASEADDR| & base address for the operand 0 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
39 
                \hline
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                \verb|C_OP0_HIGHADDR| & high address for the operand 0 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
41 
                \hline
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                \verb|C_OP1_BASEADDR| & base address for the operand 1 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
43 
                \hline
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                \verb|C_OP1_HIGHADDR| & high address for the operand 1 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
45 
                \hline
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                \verb|C_OP2_BASEADDR| & base address for the operand 2 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
47 
                \hline
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                \verb|C_OP2_HIGHADDR| & high address for the operand 2 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
49 
                \hline
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                \verb|C_OP3_BASEADDR| & base address for the operand 3 memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
51 
                \hline
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                \verb|C_OP3_HIGHADDR| & high address for the operand 3 memory space & std\_logic\_vector & X"00000000" \bigstrut\\
53 
                \hline
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                \verb|C_FIFO_BASEADDR| & base address for the FIFO memory space & std\_logic\_vector & X"FFFFFFFF" \bigstrut\\
55 
                \hline
56 
                \verb|C_FIFO_HIGHADDR| & high address for the FIFO memory space & std\_logic\_vector & X"00000000" \bigstrut\\
57 
                \hline
58 
                \multicolumn{4}{|l|}{\textit{\textbf{Multiplier configuration}}} \\
59 
                \hline
60 
                \verb|C_NR_BITS_TOTAL| & total width of the multiplier in bits & integer & 1536\bigstrut\\
61 
                \hline
62 
                \verb|C_NR_STAGES_TOTAL| & total number of stages in the pipeline & integer & 96\bigstrut\\
63 
                \hline
64 
                \verb|C_NR_STAGES_LOW| & number of lower stages in the pipeline, defines the bit-width of the lower pipeline part & integer & 32 \bigstrut\\
65 
                \hline
66 
                \verb|C_SPLIT_PIPELINE| & option to split the pipeline in 2 parts & boolean & true \bigstrut\\
67 
                \hline
68 
        \end{tabular}%
69 
\end{center}
70 
%\newline
71 
 
72 
The complete IP core's memory space can be controlled. As can be seen, the operand, modulus and FIFO memory space can be
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chosen separately from the IP core's memory space which hold the registers for control, software reset and interrupt
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control. The core's memory space must have a minimum width of 1K byte for all registers to be accessible. For the FIFO
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memory space, a minimum width of 4 byte is needed, since the FIFO is only 32 bit wide. The memory space width for the
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operands and the modulus need a minimum width equal to the total multiplier width.\\
77 
 
78 
There are 4 parameters to configure the multiplier. These values define the width of the multiplier operands and the
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number of pipeline stages. If \verb|C_SPLIT_PIPELINE| is false, only operands with a width of\\\verb|C_NR_BITS_TOTAL| are
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valid. Else if \verb|C_SPLIT_PIPELINE| is true, 3 operand widths can be supported:
81 
\begin{itemize}
82 
  \item the length of the full pipeline ($C\_NR\_BITS\_TOTAL$)
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  \item the length of the lower pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot C\_NR\_STAGES\_LOW $)
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  \item the length of the higher pipeline ($\frac{C\_NR\_BITS\_TOTAL}{C\_NR\_STAGES\_TOTAL} \cdot (C\_NR\_STAGES\_TOTAL - C\_NR\_STAGES\_LOW$)
85 
\end{itemize}
86 
 
87 
\section{IO ports}
88 
\begin{tabular}{|l|c|c|l|}
89 
        \hline
90 
        \rowcolor{Gray}
91 
        \textbf{Port} & \textbf{Width} & \textbf{Direction} & \textbf{Description} \\
92 
        \hline
93 
        \multicolumn{4}{|l|}{\textit{\textbf{PLB bus connections}}} \\
94 
        \hline
95 
        \verb|SPLB_Clk| & 1     & in & see note 1 \\
96 
        \hline
97 
        \verb|SPLB_Rst| & 1     & in & see note 1 \\
98 
        \hline
99 
        \verb|PLB_ABus| & 32    & in & see note 1 \\
100 
        \hline
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        \verb|PLB_PAValid| & 1     & in & see note 1 \\
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        \hline
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        \verb|PLB_masterID| & 3     & in & see note 1 \\
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        \hline
105 
        \verb|PLB_RNW| & 1     & in & see note 1 \\
106 
        \hline
107 
        \verb|PLB_BE| & 4     & in & see note 1 \\
108 
        \hline
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        \verb|PLB_size| & 4     & in & see note 1 \\
110 
        \hline
111 
        \verb|PLB_type| & 3     & in & see note 1 \\
112 
        \hline
113 
        \verb|PLB_wrDBus| & 32    & in & see note 1 \\
114 
        \hline
115 
        \verb|Sl_addrAck| & 1     & out & see note 1 \\
116 
        \hline
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        \verb|Sl_SSize| & 2     & out & see note 1 \\
118 
        \hline
119 
        \verb|Sl_wait| & 1     & out & see note 1 \\
120 
        \hline
121 
        \verb|Sl_rearbitrate| & 1     & out & see note 1 \\
122 
        \hline
123 
        \verb|Sl_wrDack| & 1     & out & see note 1 \\
124 
        \hline
125 
        \verb|Sl_wrComp| & 1     & out & see note 1 \\
126 
        \hline
127 
        \verb|Sl_rdBus| & 32    & out & see note 1 \\
128 
        \hline
129 
        \verb|Sl_MBusy| & 8     & out & see note 1 \\
130 
        \hline
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        \verb|Sl_MWrErr| & 8     & out & see note 1 \\
132 
        \hline
133 
        \verb|Sl_MRdErr| & 8     & out & see note 1 \\
134 
        \hline
135 
        \multicolumn{4}{|l|}{\textit{\textbf{unused PLB signals}}} \\
136 
        \hline
137 
        \verb|PLB_UABus| & 32    & in & see note 1 \\
138 
        \hline
139 
        \verb|PLB_SAValid| & 1     & in & see note 1 \\
140 
        \hline
141 
        \verb|PLB_rdPrim| & 1     & in & see note 1 \\
142 
        \hline
143 
        \verb|PLB_wrPrim| & 1     & in & see note 1 \\
144 
        \hline
145 
        \verb|PLB_abort| & 1     & in & see note 1 \\
146 
        \hline
147 
        \verb|PLB_busLock| & 1     & in & see note 1 \\
148 
        \hline
149 
        \verb|PLB_MSize| & 2     & in & see note 1 \\
150 
        \hline
151 
        \verb|PLB_TAttribute| & 16    & in & see note 1 \\
152 
        \hline
153 
        \verb|PLB_lockerr| & 1     & in & see note 1 \\
154 
        \hline
155 
        \verb|PLB_wrBurst| & 1     & in & see note 1 \\
156 
        \hline
157 
        \verb|PLB_rdBurst| & 1     & in & see note 1 \\
158 
        \hline
159 
        \verb|PLB_wrPendReq| & 1     & in & see note 1 \\
160 
        \hline
161 
        \verb|PLB_rdPendReq| & 1     & in & see note 1 \\
162 
        \hline
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        \verb|PLB_rdPendPri| & 2     & in & see note 1 \\
164 
        \hline
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        \verb|PLB_wrPendPri| & 2     & in & see note 1 \\
166 
        \hline
167 
        \verb|PLB_reqPri| & 2     & in & see note 1 \\
168 
        \hline
169 
        \verb|Sl_wrBTerm| & 1     & out & see note 1 \\
170 
        \hline
171 
        \verb|Sl_rdWdAddr| & 4     & out & see note 1 \\
172 
        \hline
173 
        \verb|Sl_rdBTerm| & 1     & out & see note 1 \\
174 
        \hline
175 
        \verb|Sl_MIRQ| & 8     & out & see note 1 \\
176 
        \hline
177 
        \multicolumn{4}{|l|}{\textit{\textbf{Core signals}}} \\
178 
        \hline
179 
        \verb|IP2INTC_Irpt| & 1     & out   & core interrupt signal \\
180 
        \hline
181 
        \verb|calc_time| & 1     & out   & is high when core is performing a multiplication, for monitoring \\
182 
        \hline
183 
\end{tabular}%
184 
\newline \newline
185 
\textbf{Note 1:} The function and timing of this signal is defined in the IBM\textsuperscript{\textregistered} 128-Bit Processor Local Bus Architecture Specification
186 
Version 4.6.
187 
 
188 
\section{Registers}
189 
This section specifies the IP core internal registers as seen from the software. These registers allow to control and
190 
configure the modular exponentiation core and to read out its state. All addresses given in this table are relative to the
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IP core's base address.\\
192 
\newline
193 
% Table generated by Excel2LaTeX
194 
\begin{tabular}{|l|c|c|c|l|}
195 
\hline
196 
\rowcolor{Gray}
197 
\textbf{Name} & \textbf{Width} & \textbf{Address} & \textbf{Access} & \textbf{Description} \bigstrut\\
198 
\hline
199 
control register                & 32 & 0x0000 & RW      & multiplier core control signals and \bigstrut[t]\\
200 
                                                &       &               &               & interrupt flags register\bigstrut[b]\\
201 
\hline
202 
software reset                  & 32 & 0x0100 & W       & soft reset for the IP core  \bigstrut\\
203 
\hline
204 
\multicolumn{5}{|l|}{\textbf{\textit{Interrupt controller registers}}} \bigstrut\\
205 
\hline
206 
global interrupt enable register        & 32 & 0x021C & RW & global interrupt enable for the IP core \bigstrut[t]\\
207 
interrupt status register                       & 32 & 0x0220 & R  & register for interrupt status flags\\
208 
interrupt enable register                       & 32 & 0x0228 & RW & register to enable individual IP core interrupts \bigstrut[b]\\
209 
\hline
210 
\end{tabular}%
211 
 
212 
\newpage
213 
\subsection{Control register (offset = 0x0000)}
214 
This registers holds the control inputs to the multiplier core and the interrupt flags.\\
215 
\begin{figure}[H]
216 
\centering
217 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_control_reg.pdf}
218 
\caption{control register}
219 
\end{figure}
220 
 
221 
 
222 
\begin{tabular}{ll}
223 
bits 0-1        & P\_SEL : selects which pipeline part to be active\\
224 
                        & $\bullet$  "01" lower pipeline part\\
225 
                        & $\bullet$  "10" higher pipeline part\\
226 
                        & $\bullet$  "11" full pipeline\\
227 
                        & $\bullet$  "00" invalid selection\\
228 
                        &\\
229 
bits 2-3        & DEST\_OP : selects the operand (0-3) to store the result in for a single\\
230 
                        & Montgomery multiplication\footnotemark\\
231 
                        &\\
232 
bits 4-5        & X\_OP : selects the x operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
233 
                        &\\
234 
bits 6-7        & Y\_OP : selects the y operand (0-3) for a single Montgomery multiplication\footnotemark[\value{footnote}]\\
235 
                        &\\
236 
bit 8           & START : starts the multiplication/exponentiation\\
237 
                        &\\
238 
bit 9           & EXP/M : selects the operating mode\\
239 
                        & $\bullet$  "0" single Montgomery multiplications\\
240 
                        & $\bullet$  "1" simultaneous exponentiations\\
241 
                        &\\
242 
bits 10-15      & unimplemented\\
243 
                        &\\
244 
bit 16          & READY : ready flag, "1" when multiplication is done\\
245 
                        & must be cleared in software\\
246 
                        &\\
247 
bit 17          & MEM\_ERR : memory collision error flag, "1" when write error occurred\\
248 
                        & must be cleared in software\\
249 
                        &\\
250 
bit 18          & FIFO\_FULL : FIFO full error flag, "1" when FIFO is full\\
251 
                        & must be cleared in software\\
252 
                        &\\
253 
bit 19          & FIFO\_ERR : FIFO write/push error flag, "1" when push error occurred\\
254 
                        & must be cleared in software\\
255 
                        &\\
256 
bits 20-31      & unimplemented\\
257 
                        &\\
258 
\end{tabular}
259 
\newline
260 
\newline
261 
\footnotetext{when the core is running in exponentiation mode, the parameters DEST\_OP, X\_OP and Y\_OP have no effect.}
262 
 
263 
\newpage
264 
\subsection{Software reset register (offset = 0x0100)}
265 
This is a register with write only access, and provides the possibility to reset the IP core from software by writing
266 
0x0000000A to this address. The reset affects the full IP core, thus resetting the control register, interrupt controller,
267 
the multiplier pipeline, FIFO and control logic of the core.
268 
 
269 
\subsection{Global interrupt enable register (offset = 0x021C)}
270 
This register contains a single defined bit in the high-order position. The GIE bit enables or disables all interrupts
271 
form the IP core.\\
272 
\begin{figure}[H]
273 
\centering
274 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_gie_reg.pdf}
275 
\caption{Global interrupt enable register}
276 
\end{figure}
277 
 
278 
\begin{tabular}{ll}
279 
bit 0           & GIE : Global interrupt enable\\
280 
                        & $\bullet$  "0" disables all core interrupts\\
281 
                        & $\bullet$  "1" enables all core interrupts\\
282 
                        &\\
283 
bits 1-31       & unimplemented\\
284 
                        &\\
285 
\end{tabular}
286 
 
287 
\subsection{Interrupt status register (offset = 0x0220)}
288 
Read-only register that contains the status of the core interrupts. Currently there is only one common interrupt from
289 
the core that is asserted when a multiplication/exponentiation is done, FIFO is full, on FIFO push error or memory write
290 
collision.\\
291 
\begin{figure}[H]
292 
\centering
293 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_is_reg.pdf}
294 
\caption{Interrupt status register}
295 
\end{figure}
296 
 
297 
\begin{tabular}{ll}
298 
bits 0-30       & unimplemented\\
299 
                        &\\
300 
bit 31          & CIS : Core interrupt status\\
301 
                        & is high when interrupt is requested from core\\
302 
                        &\\
303 
\end{tabular}
304 
 
305 
\subsection{interrupt enable register (offset = 0x0228)}
306 
This register contains the interrupt enable bits for the respective interrupt bits of the interrupt status register.\\
307 
\begin{figure}[H]
308 
\centering
309 
\includegraphics[trim=1.2cm 1.2cm 1.2cm 1.2cm, width=15cm]{pictures/plb_ie_reg.pdf}
310 
\caption{Interrupt enable register}
311 
\end{figure}
312 
\begin{tabular}{ll}
313 
bits 0-30       & unimplemented\\
314 
                        &\\
315 
bit 31          & CIE : Core interrupt enable\\
316 
                        & $\bullet$  "0" disable core interrupt\\
317 
                        & $\bullet$  "1" enable core interrupt\\
318 
                        &\\
319 
\end{tabular}
320 
 
321 
\section{Interfacing the core's RAM}
322 
Special attention must be taken when writing data to the operands and modulus. The least significant bit of the data has be on the lowest
323 
address and the most significant bit on the highest address. A write to the RAM has to happen 1 word at a time, byte writes are not
324 
supported due to the structure of the RAM.
325 
 
326 
\section{Handling interrupts}
327 
When the embedded processor receives an interrupt signal from this core, it is up to the controlling software to
328 
determine the source of the interrupt by reading out the interrupt flag of the control register.

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