1 |
63 |
JonasDC |
----------------------------------------------------------------------
|
2 |
69 |
JonasDC |
---- operand_mem ----
|
3 |
63 |
JonasDC |
---- ----
|
4 |
|
|
---- This file is part of the ----
|
5 |
|
|
---- Modular Simultaneous Exponentiation Core project ----
|
6 |
|
|
---- http://www.opencores.org/cores/mod_sim_exp/ ----
|
7 |
|
|
---- ----
|
8 |
|
|
---- Description ----
|
9 |
69 |
JonasDC |
---- RAM memory and logic to the store operands and the ----
|
10 |
|
|
---- modulus for the montgomery multiplier, the user has a ----
|
11 |
|
|
---- choise between 3 memory styles, more detail in the ----
|
12 |
|
|
---- documentation ----
|
13 |
|
|
---- ----
|
14 |
63 |
JonasDC |
---- Dependencies: ----
|
15 |
69 |
JonasDC |
---- - operand_ram ----
|
16 |
|
|
---- - modulus_ram ----
|
17 |
63 |
JonasDC |
---- - operand_ram_gen ----
|
18 |
|
|
---- - modulus_ram_gen ----
|
19 |
69 |
JonasDC |
---- - operand_ram_asym ----
|
20 |
|
|
---- - modulus_ram_asym ----
|
21 |
63 |
JonasDC |
---- ----
|
22 |
|
|
---- Authors: ----
|
23 |
|
|
---- - Geoffrey Ottoy, DraMCo research group ----
|
24 |
|
|
---- - Jonas De Craene, JonasDC@opencores.org ----
|
25 |
|
|
---- ----
|
26 |
|
|
----------------------------------------------------------------------
|
27 |
|
|
---- ----
|
28 |
|
|
---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
|
29 |
|
|
---- ----
|
30 |
|
|
---- This source file may be used and distributed without ----
|
31 |
|
|
---- restriction provided that this copyright statement is not ----
|
32 |
|
|
---- removed from the file and that any derivative work contains ----
|
33 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
34 |
|
|
---- ----
|
35 |
|
|
---- This source file is free software; you can redistribute it ----
|
36 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
37 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
38 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
39 |
|
|
---- later version. ----
|
40 |
|
|
---- ----
|
41 |
|
|
---- This source is distributed in the hope that it will be ----
|
42 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
43 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
44 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
45 |
|
|
---- details. ----
|
46 |
|
|
---- ----
|
47 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
48 |
|
|
---- Public License along with this source; if not, download it ----
|
49 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
50 |
|
|
---- ----
|
51 |
|
|
----------------------------------------------------------------------
|
52 |
|
|
|
53 |
|
|
library ieee;
|
54 |
|
|
use ieee.std_logic_1164.all;
|
55 |
|
|
use ieee.std_logic_arith.all;
|
56 |
|
|
use ieee.std_logic_unsigned.all;
|
57 |
|
|
|
58 |
|
|
library mod_sim_exp;
|
59 |
|
|
use mod_sim_exp.mod_sim_exp_pkg.all;
|
60 |
|
|
use mod_sim_exp.std_functions.all;
|
61 |
|
|
|
62 |
|
|
-- address structure:
|
63 |
|
|
-- bit: highest -> '1': modulus
|
64 |
|
|
-- '0': operands
|
65 |
|
|
-- bits: (highest-1)-log2(width/32) -> operand_in_sel in case of highest bit = '0'
|
66 |
|
|
-- modulus_in_sel in case of highest bit = '1'
|
67 |
|
|
-- bits: (log2(width/32)-1)-0 -> modulus_addr / operand_addr resp.
|
68 |
|
|
--
|
69 |
69 |
JonasDC |
entity operand_mem is
|
70 |
63 |
JonasDC |
generic(
|
71 |
69 |
JonasDC |
width : integer := 1536; -- width of the operands
|
72 |
|
|
nr_op : integer := 4; -- nr of operand storages, has to be greater than nr_m
|
73 |
|
|
nr_m : integer := 2; -- nr of modulus storages
|
74 |
|
|
mem_style : string := "asym"; -- xil_prim, generic, asym are valid options
|
75 |
|
|
device : string := "altera" -- xilinx, altera are valid options
|
76 |
63 |
JonasDC |
);
|
77 |
|
|
port(
|
78 |
|
|
-- system clock
|
79 |
|
|
clk : in std_logic;
|
80 |
|
|
-- data interface (plb side)
|
81 |
|
|
data_in : in std_logic_vector(31 downto 0);
|
82 |
|
|
data_out : out std_logic_vector(31 downto 0);
|
83 |
|
|
rw_address : in std_logic_vector(log2(nr_op)+log2(width/32) downto 0);
|
84 |
|
|
write_enable : in std_logic;
|
85 |
|
|
-- operand interface (multiplier side)
|
86 |
|
|
op_sel : in std_logic_vector(log2(nr_op)-1 downto 0);
|
87 |
|
|
xy_out : out std_logic_vector((width-1) downto 0);
|
88 |
|
|
m : out std_logic_vector((width-1) downto 0);
|
89 |
|
|
result_in : in std_logic_vector((width-1) downto 0);
|
90 |
|
|
-- control signals
|
91 |
|
|
load_result : in std_logic;
|
92 |
|
|
result_dest_op : in std_logic_vector(log2(nr_op)-1 downto 0);
|
93 |
|
|
collision : out std_logic;
|
94 |
|
|
modulus_sel : in std_logic_vector(log2(nr_m)-1 downto 0)
|
95 |
|
|
);
|
96 |
69 |
JonasDC |
end operand_mem;
|
97 |
63 |
JonasDC |
|
98 |
69 |
JonasDC |
architecture structural of operand_mem is
|
99 |
|
|
-- constants
|
100 |
63 |
JonasDC |
constant wordaddr_aw : integer := log2(width/32);
|
101 |
|
|
constant opaddr_aw : integer := log2(nr_op);
|
102 |
69 |
JonasDC |
constant maddr_aw : integer := log2(nr_m);
|
103 |
63 |
JonasDC |
constant total_aw : integer := 1+opaddr_aw+wordaddr_aw;
|
104 |
|
|
|
105 |
69 |
JonasDC |
-- internal signals
|
106 |
63 |
JonasDC |
signal xy_data_i : std_logic_vector(31 downto 0);
|
107 |
|
|
signal xy_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
|
108 |
|
|
signal operand_in_sel_i : std_logic_vector(opaddr_aw-1 downto 0);
|
109 |
|
|
signal modulus_in_sel_i : std_logic_vector(maddr_aw-1 downto 0);
|
110 |
|
|
|
111 |
|
|
signal load_op : std_logic;
|
112 |
|
|
|
113 |
69 |
JonasDC |
signal m_addr_i : std_logic_vector(wordaddr_aw-1 downto 0);
|
114 |
|
|
signal load_m : std_logic;
|
115 |
|
|
signal m_data_i : std_logic_vector(31 downto 0);
|
116 |
63 |
JonasDC |
|
117 |
|
|
begin
|
118 |
|
|
|
119 |
|
|
-- map inputs
|
120 |
|
|
xy_addr_i <= rw_address(wordaddr_aw-1 downto 0);
|
121 |
|
|
m_addr_i <= rw_address(wordaddr_aw-1 downto 0);
|
122 |
|
|
operand_in_sel_i <= rw_address(total_aw-2 downto wordaddr_aw);
|
123 |
|
|
modulus_in_sel_i <= rw_address(wordaddr_aw+maddr_aw-1 downto wordaddr_aw);
|
124 |
|
|
xy_data_i <= data_in;
|
125 |
|
|
m_data_i <= data_in;
|
126 |
|
|
|
127 |
69 |
JonasDC |
-- select right memory with highest address bit
|
128 |
63 |
JonasDC |
load_op <= write_enable when (rw_address(total_aw-1) = '0') else '0';
|
129 |
|
|
load_m <= write_enable when (rw_address(total_aw-1) = '1') else '0';
|
130 |
|
|
|
131 |
69 |
JonasDC |
xil_prim_RAM : if mem_style="xil_prim" generate
|
132 |
|
|
-- xy operand storage
|
133 |
|
|
xy_ram_xil : operand_ram
|
134 |
|
|
port map(
|
135 |
|
|
clk => clk,
|
136 |
|
|
collision => collision,
|
137 |
|
|
operand_addr => xy_addr_i,
|
138 |
|
|
operand_in => xy_data_i,
|
139 |
|
|
operand_in_sel => operand_in_sel_i,
|
140 |
|
|
result_out => data_out,
|
141 |
|
|
write_operand => load_op,
|
142 |
|
|
operand_out => xy_out,
|
143 |
|
|
operand_out_sel => op_sel,
|
144 |
|
|
result_dest_op => result_dest_op,
|
145 |
|
|
write_result => load_result,
|
146 |
|
|
result_in => result_in
|
147 |
|
|
);
|
148 |
|
|
|
149 |
|
|
-- modulus storage
|
150 |
|
|
m_ram_xil : modulus_ram
|
151 |
|
|
port map(
|
152 |
|
|
clk => clk,
|
153 |
|
|
modulus_addr => m_addr_i,
|
154 |
|
|
write_modulus => load_m,
|
155 |
|
|
modulus_in => m_data_i,
|
156 |
|
|
modulus_out => m
|
157 |
|
|
);
|
158 |
|
|
end generate;
|
159 |
63 |
JonasDC |
|
160 |
69 |
JonasDC |
gen_RAM : if mem_style="generic" generate
|
161 |
|
|
-- xy operand storage
|
162 |
|
|
xy_ram_gen : operand_ram_gen
|
163 |
|
|
generic map(
|
164 |
|
|
width => width,
|
165 |
|
|
depth => nr_op
|
166 |
|
|
)
|
167 |
|
|
port map(
|
168 |
|
|
clk => clk,
|
169 |
|
|
collision => collision,
|
170 |
|
|
operand_addr => xy_addr_i,
|
171 |
|
|
operand_in => xy_data_i,
|
172 |
|
|
operand_in_sel => operand_in_sel_i,
|
173 |
|
|
result_out => data_out,
|
174 |
|
|
write_operand => load_op,
|
175 |
|
|
operand_out => xy_out,
|
176 |
|
|
operand_out_sel => op_sel,
|
177 |
|
|
result_dest_op => result_dest_op,
|
178 |
|
|
write_result => load_result,
|
179 |
|
|
result_in => result_in
|
180 |
|
|
);
|
181 |
63 |
JonasDC |
|
182 |
69 |
JonasDC |
-- modulus storage
|
183 |
|
|
m_ram_gen : modulus_ram_gen
|
184 |
|
|
generic map(
|
185 |
|
|
width => width,
|
186 |
|
|
depth => nr_m
|
187 |
|
|
)
|
188 |
|
|
port map(
|
189 |
|
|
clk => clk,
|
190 |
|
|
modulus_in_sel => modulus_in_sel_i,
|
191 |
|
|
modulus_addr => m_addr_i,
|
192 |
|
|
write_modulus => load_m,
|
193 |
|
|
modulus_in => m_data_i,
|
194 |
|
|
modulus_out => m,
|
195 |
|
|
modulus_sel => modulus_sel
|
196 |
|
|
);
|
197 |
|
|
end generate;
|
198 |
|
|
|
199 |
|
|
asym_RAM : if mem_style="asym" generate
|
200 |
|
|
-- xy operand storage
|
201 |
|
|
xy_ram_asym : operand_ram_asym
|
202 |
|
|
generic map(
|
203 |
|
|
width => width,
|
204 |
|
|
depth => nr_op,
|
205 |
|
|
device => device
|
206 |
|
|
)
|
207 |
|
|
port map(
|
208 |
|
|
clk => clk,
|
209 |
|
|
collision => collision,
|
210 |
|
|
operand_addr => xy_addr_i,
|
211 |
|
|
operand_in => xy_data_i,
|
212 |
|
|
operand_in_sel => operand_in_sel_i,
|
213 |
|
|
result_out => data_out,
|
214 |
|
|
write_operand => load_op,
|
215 |
|
|
operand_out => xy_out,
|
216 |
|
|
operand_out_sel => op_sel,
|
217 |
|
|
result_dest_op => result_dest_op,
|
218 |
|
|
write_result => load_result,
|
219 |
|
|
result_in => result_in
|
220 |
|
|
);
|
221 |
|
|
|
222 |
|
|
-- modulus storage
|
223 |
|
|
m_ram_asym : modulus_ram_asym
|
224 |
|
|
generic map(
|
225 |
|
|
width => width,
|
226 |
|
|
depth => nr_m,
|
227 |
|
|
device => device
|
228 |
|
|
)
|
229 |
|
|
port map(
|
230 |
|
|
clk => clk,
|
231 |
|
|
modulus_in_sel => modulus_in_sel_i,
|
232 |
|
|
modulus_addr => m_addr_i,
|
233 |
|
|
write_modulus => load_m,
|
234 |
|
|
modulus_in => m_data_i,
|
235 |
|
|
modulus_out => m,
|
236 |
|
|
modulus_sel => modulus_sel
|
237 |
|
|
);
|
238 |
|
|
end generate;
|
239 |
|
|
|
240 |
|
|
end structural;
|