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JonasDC |
----------------------------------------------------------------------
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---- sys_pipeline ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- the pipelined systolic array for a montgommery multiplier ----
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---- ----
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---- Dependencies: ----
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---- - sys_stage ----
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---- - register_n ----
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---- - d_flip_flop ----
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---- - cell_1b_adder ----
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---- - cell_1b_mux ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.mod_sim_exp_pkg.all;
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-- the pipelined systolic array for a montgommery multiplier
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-- contains a structural description of the pipeline using the systolic stages
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entity sys_pipeline is
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generic(
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n : integer := 1536; -- width of the operands (# bits)
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JonasDC |
t : integer := 192; -- total number of stages (minimum 2)
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tl : integer := 64; -- lower number of stages (minimum 1)
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split : boolean := true -- if true the pipeline wil be split in 2 parts,
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-- if false there are no lower stages, only t counts
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JonasDC |
);
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port(
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-- clock input
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core_clk : in std_logic;
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-- modulus and y opperand input (n)-bit
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y : in std_logic_vector((n-1) downto 0);
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m : in std_logic_vector((n-1) downto 0);
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-- x operand input (serial)
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xi : in std_logic;
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next_x : out std_logic; -- next x operand bit
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-- control signals
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start : in std_logic; -- start multiplier
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reset : in std_logic;
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p_sel : in std_logic_vector(1 downto 0); -- select which piece of the pipeline will be used
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-- result out
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r : out std_logic_vector((n-1) downto 0)
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);
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end sys_pipeline;
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architecture Structural of sys_pipeline is
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constant s : integer := n/t;
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signal m_i : std_logic_vector(n downto 0);
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signal y_i : std_logic_vector(n downto 0);
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JonasDC |
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-- systolic stages signals
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signal my_cin_stage : std_logic_vector((t-1) downto 0);
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signal my_cout_stage : std_logic_vector((t-1) downto 0);
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signal xin_stage : std_logic_vector((t-1) downto 0);
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signal qin_stage : std_logic_vector((t-1) downto 0);
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signal xout_stage : std_logic_vector((t-1) downto 0);
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signal qout_stage : std_logic_vector((t-1) downto 0);
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signal a_msb_stage : std_logic_vector((t-1) downto 0);
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signal a_0_stage : std_logic_vector((t-1) downto 0);
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signal cin_stage : std_logic_vector((t-1) downto 0);
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signal cout_stage : std_logic_vector((t-1) downto 0);
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signal red_cin_stage : std_logic_vector((t-1) downto 0);
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signal red_cout_stage : std_logic_vector((t-1) downto 0);
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signal start_stage : std_logic_vector((t-1) downto 0);
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signal done_stage : std_logic_vector((t-1) downto 0);
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signal r_sel_stage : std_logic_vector((t-1) downto 0);
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-- end logic signals
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signal r_sel_end : std_logic;
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-- signals needed if pipeline is split
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---------------------------------------
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signal r_sel_l : std_logic;
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signal r_sel_h : std_logic;
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-- mid end logic signals
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signal a_0_midend : std_logic;
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signal r_sel_midend : std_logic;
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JonasDC |
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-- mid start logic signals
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signal my_cout_midstart : std_logic;
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signal xout_midstart : std_logic;
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signal qout_midstart : std_logic;
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signal cout_midstart : std_logic;
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signal red_cout_midstart : std_logic;
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JonasDC |
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JonasDC |
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JonasDC |
begin
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m_i <= '0' & m;
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y_i <= '0' & y;
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-- generate the stages for the full pipeline
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pipeline_stages : for i in 0 to (t-1) generate
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stage : sys_stage
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generic map(
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width => s
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)
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port map(
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core_clk => core_clk,
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y => y_i((i+1)*s downto (i*s)+1),
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m => m_i((i+1)*s downto (i*s)),
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my_cin => my_cin_stage(i),
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my_cout => my_cout_stage(i),
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xin => xin_stage(i),
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qin => qin_stage(i),
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xout => xout_stage(i),
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qout => qout_stage(i),
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a_0 => a_0_stage(i),
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a_msb => a_msb_stage(i),
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cin => cin_stage(i),
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cout => cout_stage(i),
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red_cin => red_cin_stage(i),
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red_cout => red_cout_stage(i),
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start => start_stage(i),
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reset => reset,
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done => done_stage(i),
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r_sel => r_sel_stage(i),
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r => r(((i+1)*s)-1 downto (i*s))
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);
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end generate;
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-- first cell logic
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--------------------
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first_cell : sys_first_cell_logic
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port map (
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m0 => m_i(0),
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y0 => y_i(0),
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my_cout => my_cin_stage(0),
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xi => xi,
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xout => xin_stage(0),
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qout => qin_stage(0),
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cout => cin_stage(0),
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a_0 => a_0_stage(0),
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red_cout => red_cin_stage(0)
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);
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-- last cell logic
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-------------------
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last_cell : sys_last_cell_logic
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port map (
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core_clk => core_clk,
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reset => reset,
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a_0 => a_msb_stage(t-1),
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cin => cout_stage(t-1),
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red_cin => red_cout_stage(t-1),
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r_sel => r_sel_end,
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start => done_stage(t-1)
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);
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------------------------------------
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-- SINGLE PART PIPELINE CONNECTIONS
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------------------------------------
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single_pipeline : if split=false generate
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-- link stages to eachother
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stage_connect : for i in 1 to (t-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
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cin_stage(i) <= cout_stage(i-1);
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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r_sel_stage(i) <= r_sel_end;
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end generate;
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r_sel_stage(0) <= r_sel_end;
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start_stage(0) <= start;
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next_x <= done_stage(0);
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end generate;
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----------------------------------------
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-- SPLIT PIPELINE CONNECTIONS AND LOGIC
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----------------------------------------
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split_pipeline : if split=true generate
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JonasDC |
-- only start first stage if lower part is used
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with p_sel select
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start_stage(0) <= '0' when "10",
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start when others;
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JonasDC |
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JonasDC |
-- select start or midstart stage for requesting new xi bit
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JonasDC |
with p_sel select
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next_x <= done_stage(tl) when "10",
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done_stage(0) when others;
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-- link lower stages to eachother
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stage_connect_l : for i in 1 to (tl-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
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cin_stage(i) <= cout_stage(i-1);
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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r_sel_stage(i) <= r_sel_l;
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JonasDC |
end generate;
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JonasDC |
r_sel_stage(0) <= r_sel_l;
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JonasDC |
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-- mid end logic
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-----------------
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mid_end_cell : sys_last_cell_logic
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port map (
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core_clk => core_clk,
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reset => reset,
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a_0 => a_0_midend,
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cin => cout_stage(tl-1),
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red_cin => red_cout_stage(tl-1),
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r_sel => r_sel_midend,
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start => done_stage(tl-1)
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);
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--muxes for midend signals
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with p_sel select
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a_msb_stage(tl-1) <= a_0_midend when "01",
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a_0_stage(tl) when others;
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-- mid start logic
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-------------------
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mid_start_logic : sys_first_cell_logic
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port map (
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m0 => m_i(tl*s),
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y0 => y_i(tl*s),
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my_cout => my_cout_midstart,
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xi => xi,
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xout => xout_midstart,
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qout => qout_midstart,
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cout => cout_midstart,
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a_0 => a_0_stage(tl),
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red_cout => red_cout_midstart
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);
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-- only start stage tl if only higher part is used
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with p_sel select
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start_stage(tl) <= start when "10",
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done_stage(tl-1) when "11",
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'0' when others;
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with p_sel select
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my_cin_stage(tl) <= my_cout_midstart when "10",
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my_cout_stage(tl-1) when others;
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with p_sel select
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xin_stage(tl) <= xout_midstart when "10",
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xout_stage(tl-1) when others;
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with p_sel select
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qin_stage(tl) <= qout_midstart when "10",
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qout_stage(tl-1) when others;
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with p_sel select
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cin_stage(tl) <= cout_midstart when "10",
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cout_stage(tl-1) when others;
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with p_sel select
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red_cin_stage(tl) <= red_cout_midstart when "10",
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red_cout_stage(tl-1) when others;
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-- link higher stages to eachother
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stage_connect_h : for i in (tl+1) to (t-1) generate
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my_cin_stage(i) <= my_cout_stage(i-1);
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cin_stage(i) <= cout_stage(i-1);
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xin_stage(i) <= xout_stage(i-1);
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qin_stage(i) <= qout_stage(i-1);
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red_cin_stage(i) <= red_cout_stage(i-1);
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start_stage(i) <= done_stage(i-1);
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a_msb_stage(i-1) <= a_0_stage(i);
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36 |
JonasDC |
r_sel_stage(i) <= r_sel_h;
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32 |
JonasDC |
end generate;
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36 |
JonasDC |
r_sel_stage(tl) <= r_sel_h;
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25 |
JonasDC |
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32 |
JonasDC |
with p_sel select
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36 |
JonasDC |
r_sel_l <= r_sel_midend when "01",
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r_sel_end when "11",
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'0' when others;
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with p_sel select
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r_sel_h <= '0' when "01",
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r_sel_end when others;
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37 |
JonasDC |
end generate;
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JonasDC |
end Structural;
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