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1 2 JonasDC
------------------------------------------------------------------------------
2
-- user_logic.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
--
5
-- ***************************************************************************
6
-- ** Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.            **
7
-- **                                                                       **
8
-- ** Xilinx, Inc.                                                          **
9
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
10
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
11
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
12
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
13
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
14
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
15
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
16
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
17
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
18
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
19
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
20
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
21
-- ** FOR A PARTICULAR PURPOSE.                                             **
22
-- **                                                                       **
23
-- ***************************************************************************
24
--
25
------------------------------------------------------------------------------
26
-- Filename:          user_logic.vhd
27
-- Version:           2.00.a
28
-- Description:       User logic.
29
-- Date:              Thu May 03 09:53:36 2012 (by Create and Import Peripheral Wizard)
30
-- VHDL Standard:     VHDL'93
31
------------------------------------------------------------------------------
32
-- Naming Conventions:
33
--   active low signals:                    "*_n"
34
--   clock signals:                         "clk", "clk_div#", "clk_#x"
35
--   reset signals:                         "rst", "rst_n"
36
--   generics:                              "C_*"
37
--   user defined types:                    "*_TYPE"
38
--   state machine next state:              "*_ns"
39
--   state machine current state:           "*_cs"
40
--   combinatorial signals:                 "*_com"
41
--   pipelined or register delay signals:   "*_d#"
42
--   counter signals:                       "*cnt*"
43
--   clock enable signals:                  "*_ce"
44
--   internal version of output port:       "*_i"
45
--   device pins:                           "*_pin"
46
--   ports:                                 "- Names begin with Uppercase"
47
--   processes:                             "*_PROCESS"
48
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
49
------------------------------------------------------------------------------
50
 
51
-- DO NOT EDIT BELOW THIS LINE --------------------
52
library ieee;
53
use ieee.std_logic_1164.all;
54
use ieee.std_logic_arith.all;
55
use ieee.std_logic_unsigned.all;
56
 
57
library proc_common_v3_00_a;
58
use proc_common_v3_00_a.proc_common_pkg.all;
59
 
60
-- DO NOT EDIT ABOVE THIS LINE --------------------
61
 
62
--USER libraries added here
63
 
64
------------------------------------------------------------------------------
65
-- Entity section
66
------------------------------------------------------------------------------
67
-- Definition of Generics:
68
--   C_SLV_AWIDTH                 -- Slave interface address bus width
69
--   C_SLV_DWIDTH                 -- Slave interface data bus width
70
--   C_NUM_REG                    -- Number of software accessible registers
71
--   C_NUM_MEM                    -- Number of memory spaces
72
--   C_NUM_INTR                   -- Number of interrupt event
73
--
74
-- Definition of Ports:
75
--   Bus2IP_Clk                   -- Bus to IP clock
76
--   Bus2IP_Reset                 -- Bus to IP reset
77
--   Bus2IP_Addr                  -- Bus to IP address bus
78
--   Bus2IP_CS                    -- Bus to IP chip select for user logic memory selection
79
--   Bus2IP_RNW                   -- Bus to IP read/not write
80
--   Bus2IP_Data                  -- Bus to IP data bus
81
--   Bus2IP_BE                    -- Bus to IP byte enables
82
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
83
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
84
--   IP2Bus_Data                  -- IP to Bus data bus
85
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
86
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
87
--   IP2Bus_Error                 -- IP to Bus error response
88
--   IP2Bus_IntrEvent             -- IP to Bus interrupt event
89
------------------------------------------------------------------------------
90
 
91
entity user_logic is
92
  generic
93
  (
94
    -- ADD USER GENERICS BELOW THIS LINE ---------------
95
    --USER generics added here
96
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
97
 
98
    -- DO NOT EDIT BELOW THIS LINE ---------------------
99
    -- Bus protocol parameters, do not add to or delete
100
    C_SLV_AWIDTH                   : integer              := 32;
101
    C_SLV_DWIDTH                   : integer              := 32;
102
    C_NUM_REG                      : integer              := 1;
103
    C_NUM_MEM                      : integer              := 6;
104
    C_NUM_INTR                     : integer              := 1
105
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
106
  );
107
  port
108
  (
109
    -- ADD USER PORTS BELOW THIS LINE ------------------
110
    --USER ports added here
111
         calc_time                      : out std_logic;
112
        -- ctrl_sigs                      : out std_logic_vector( downto );
113
    -- ADD USER PORTS ABOVE THIS LINE ------------------
114
 
115
    -- DO NOT EDIT BELOW THIS LINE ---------------------
116
    -- Bus protocol ports, do not add to or delete
117
    Bus2IP_Clk                     : in  std_logic;
118
    Bus2IP_Reset                   : in  std_logic;
119
    Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
120
    Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
121
    Bus2IP_RNW                     : in  std_logic;
122
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
123
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
124
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
125
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
126
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
127
    IP2Bus_RdAck                   : out std_logic;
128
    IP2Bus_WrAck                   : out std_logic;
129
    IP2Bus_Error                   : out std_logic;
130
    IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
131
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
132
  );
133
 
134
  attribute SIGIS : string;
135
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
136
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";
137
 
138
end entity user_logic;
139
 
140
------------------------------------------------------------------------------
141
-- Architecture section
142
------------------------------------------------------------------------------
143
 
144
architecture IMP of user_logic is
145
 
146
  --USER signal declarations added here, as needed for user logic
147
  component multiplier_core
148
    port(          clk : in  std_logic;
149
                      reset : in  std_logic;
150
                        -- operand memory interface (plb shared memory)
151
                         write_enable : in  std_logic;
152
               data_in : in  std_logic_vector (31 downto 0);
153
            rw_address : in  std_logic_vector (8 downto 0);
154
              data_out : out std_logic_vector (31 downto 0);
155
                                 collision : out std_logic;
156
                        -- op_sel fifo interface
157
                             fifo_din : in  std_logic_vector (31 downto 0);
158
                            fifo_push : in  std_logic;
159
                            fifo_full : out std_logic;
160
                          fifo_nopush : out std_logic;
161
                        -- ctrl signals
162
                                start : in  std_logic;
163
                             run_auto : in  std_logic;
164
                                ready : out std_logic;
165
                    x_sel_single : in  std_logic_vector (1 downto 0);
166
                    y_sel_single : in  std_logic_vector (1 downto 0);
167
                  dest_op_single : in  std_logic_vector (1 downto 0);
168
                 p_sel : in  std_logic_vector (1 downto 0);
169
                                 calc_time : out std_logic
170
        );
171
  end component;
172
 
173
  ------------------------------------------------------------------
174
  -- Signals for multiplier core slave model s/w accessible register
175
  ------------------------------------------------------------------
176
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
177
  signal slv_reg_write_sel              : std_logic_vector(0 to 0);
178
  signal slv_reg_read_sel               : std_logic_vector(0 to 0);
179
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
180
  signal slv_read_ack                   : std_logic;
181
  signal slv_write_ack                  : std_logic;
182
 
183
  signal load_flags                     : std_logic;
184
 
185
  ------------------------------------------------------------------
186
  -- Signals for multiplier core interrupt
187
  ------------------------------------------------------------------
188
  signal core_interrupt                 : std_logic_vector(0 to 0);
189
  signal core_fifo_full                : std_logic;
190
  signal core_fifo_nopush               : std_logic;
191
  signal core_ready                     : std_logic;
192
  signal core_mem_collision             : std_logic;
193
 
194
  ------------------------------------------------------------------
195
  -- Signals for multiplier core control
196
  ------------------------------------------------------------------
197
  signal core_start                     : std_logic;
198
  signal core_run_auto                  : std_logic;
199
  signal core_p_sel                     : std_logic_vector(1 downto 0);
200
  signal core_dest_op_single            : std_logic_vector(1 downto 0);
201
  signal core_x_sel_single              : std_logic_vector(1 downto 0);
202
  signal core_y_sel_single              : std_logic_vector(1 downto 0);
203
  signal core_flags                     : std_logic_vector(15 downto 0);
204
 
205
  ------------------------------------------------------------------
206
  -- Signals for multiplier core memory space
207
  ------------------------------------------------------------------
208
  signal mem_address                    : std_logic_vector(0 to 5);
209
  signal mem_select                     : std_logic_vector(0 to 5);
210
  signal mem_read_enable                : std_logic;
211
  signal mem_read_enable_dly1           : std_logic;
212
  signal mem_read_req                   : std_logic;
213
  signal mem_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
214
  signal mem_read_ack_dly1              : std_logic;
215
  signal mem_read_ack                   : std_logic;
216
  signal mem_write_ack                  : std_logic;
217
 
218
  signal core_rw_address                : std_logic_vector (8 downto 0);
219
  signal core_data_in                   : std_logic_vector(31 downto 0);
220
  signal core_fifo_din                  : std_logic_vector(31 downto 0);
221
  signal sel_mno                        : std_logic;
222
  signal sel_op                         : std_logic_vector(1 downto 0);
223
  signal core_data_out                  : std_logic_vector(31 downto 0);
224
  signal core_write_enable              : std_logic;
225
  signal core_fifo_push                 : std_logic;
226
begin
227
 
228
  --USER logic implementation added here
229
  --ctrl_sigs <= 
230
 
231
  ------------------------------------------
232
  -- Example code to read/write user logic slave model s/w accessible registers
233
  -- 
234
  -- Note:
235
  -- The example code presented here is to show you one way of reading/writing
236
  -- software accessible registers implemented in the user logic slave model.
237
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
238
  -- to one software accessible register by the top level template. For example,
239
  -- if you have four 32 bit software accessible registers in the user logic,
240
  -- you are basically operating on the following memory mapped registers:
241
  -- 
242
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
243
  --                     "1000"   C_BASEADDR + 0x0
244
  --                     "0100"   C_BASEADDR + 0x4
245
  --                     "0010"   C_BASEADDR + 0x8
246
  --                     "0001"   C_BASEADDR + 0xC
247
  -- 
248
  ------------------------------------------
249
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
250
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 0);
251
  slv_write_ack     <= Bus2IP_WrCE(0);
252
  slv_read_ack      <= Bus2IP_RdCE(0);
253
 
254
  -- implement slave model software accessible register(s)
255
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
256
  begin
257
    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
258
      if Bus2IP_Reset = '1' then
259
        slv_reg0 <= (others => '0');
260
      elsif load_flags = '1' then
261
                  slv_reg0 <= slv_reg0(0 to 15) & core_flags;
262
                else
263
        case slv_reg_write_sel is
264
          when "1" =>
265
            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
266
              if ( Bus2IP_BE(byte_index) = '1' ) then
267
                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
268
              end if;
269
            end loop;
270
          when others => null;
271
        end case;
272
      end if;
273
    end if;
274
 
275
  end process SLAVE_REG_WRITE_PROC;
276
 
277
  -- implement slave model software accessible register(s) read mux
278
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
279
  begin
280
 
281
    case slv_reg_read_sel is
282
      when "1" => slv_ip2bus_data <= slv_reg0;
283
      when others => slv_ip2bus_data <= (others => '0');
284
    end case;
285
 
286
  end process SLAVE_REG_READ_PROC;
287
 
288
  ------------------------------------------
289
  -- Multiplier core interrupts form IP core interrupt
290
  ------------------------------------------
291
 
292
  core_interrupt(0) <= core_ready or core_mem_collision or core_fifo_full or core_fifo_nopush;
293
  IP2Bus_IntrEvent <= core_interrupt;
294
 
295
  FLAGS_CNTRL_PROC: process(Bus2IP_Clk, Bus2IP_Reset) is
296
  begin
297
    if Bus2IP_Reset = '1' then
298
           core_flags <= (others => '0');
299
                load_flags <= '0';
300
    elsif rising_edge(Bus2IP_Clk) then
301
           if core_start = '1' then
302
                  core_flags <= (others => '0');
303
                else
304
                  if core_ready = '1' then
305
                    core_flags(15) <= '1';
306
                  else
307
                    core_flags(15) <= core_flags(15);
308
                  end if;
309
                  if core_mem_collision = '1' then
310
                    core_flags(14) <= '1';
311
                  else
312
                    core_flags(14) <= core_flags(14);
313
                  end if;
314
                  if core_fifo_full = '1' then
315
                         core_flags(13) <= '1';
316
                  else
317
                    core_flags(13) <= core_flags(13);
318
                  end if;
319
                  if core_fifo_nopush = '1' then
320
                         core_flags(12) <= '1';
321
                  else
322
                    core_flags(12) <= core_flags(12);
323
                  end if;
324
                end if;
325
                --
326
                load_flags <= core_interrupt(0);
327
         end if;
328
  end process FLAGS_CNTRL_PROC;
329
 
330
  ------------------------------------------
331
  -- Example code to access user logic memory region
332
  -- 
333
  -- Note:
334
  -- The example code presented here is to show you one way of using
335
  -- the user logic memory space features. The Bus2IP_Addr, Bus2IP_CS,
336
  -- and Bus2IP_RNW IPIC signals are dedicated to these user logic
337
  -- memory spaces. Each user logic memory space has its own address
338
  -- range and is allocated one bit on the Bus2IP_CS signal to indicated
339
  -- selection of that memory space. Typically these user logic memory
340
  -- spaces are used to implement memory controller type cores, but it
341
  -- can also be used in cores that need to access additional address space
342
  -- (non C_BASEADDR based), s.t. bridges. This code snippet infers
343
  -- 6 256x32-bit (byte accessible) single-port Block RAM by XST.
344
  ------------------------------------------
345
  mem_select      <= Bus2IP_CS;
346
  mem_read_enable <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and Bus2IP_RNW;
347
  mem_read_ack    <= mem_read_ack_dly1;
348
  mem_write_ack   <= ( Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4) or Bus2IP_CS(5) ) and not(Bus2IP_RNW);
349
  mem_address     <= Bus2IP_Addr(C_SLV_AWIDTH-8 to C_SLV_AWIDTH-3);
350
 
351
  -- implement single clock wide read request
352
  mem_read_req    <= mem_read_enable and not(mem_read_enable_dly1);
353
  BRAM_RD_REQ_PROC : process( Bus2IP_Clk ) is
354
  begin
355
 
356
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
357
      if ( Bus2IP_Reset = '1' ) then
358
        mem_read_enable_dly1 <= '0';
359
      else
360
        mem_read_enable_dly1 <= mem_read_enable;
361
      end if;
362
    end if;
363
 
364
  end process BRAM_RD_REQ_PROC;
365
 
366
  -- this process generates the read acknowledge 1 clock after read enable
367
  -- is presented to the BRAM block. The BRAM block has a 1 clock delay
368
  -- from read enable to data out.
369
  BRAM_RD_ACK_PROC : process( Bus2IP_Clk ) is
370
  begin
371
 
372
    if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
373
      if ( Bus2IP_Reset = '1' ) then
374
        mem_read_ack_dly1 <= '0';
375
      else
376
        mem_read_ack_dly1 <= mem_read_req;
377
      end if;
378
    end if;
379
 
380
  end process BRAM_RD_ACK_PROC;
381
 
382
    -- address logic
383
  Sel_MNO <= mem_select(0);
384
  with mem_select(1 to 4) select
385
    Sel_Op <= "00" when "1000",
386
                   "01" when "0100",
387
                                  "10" when "0010",
388
                                  "11" when others;
389
 
390
 
391
  core_rw_address <= Sel_MNO & Sel_Op & mem_address;
392
 
393
  -- data-in
394
  core_data_in <= Bus2IP_Data;
395
  core_fifo_din <= Bus2IP_Data;
396
  core_write_enable <= (Bus2IP_CS(0) or Bus2IP_CS(1) or Bus2IP_CS(2) or Bus2IP_CS(3) or Bus2IP_CS(4)) and (not Bus2IP_RNW);
397
  core_fifo_push <= Bus2IP_CS(5) and (not Bus2IP_RNW);
398
  -- no read mux required, we can only read from core_data_out
399
  mem_ip2bus_data <= core_data_out;
400
 
401
  ------------------------------------------
402
  -- Map slv_reg0 bits to core control signals 
403
  ------------------------------------------
404
  core_start <= slv_reg0(8);
405
  core_run_auto <= slv_reg0(9);
406
  core_p_sel <= slv_reg0(0 to 1);
407
  core_dest_op_single <= slv_reg0(2 to 3);
408
  core_x_sel_single <= slv_reg0(4 to 5);
409
  core_y_sel_single <= slv_reg0(6 to 7);
410
 
411
  ------------------------------------------
412
  -- Multiplier core instance
413
  ------------------------------------------
414
  the_multiplier: multiplier_core
415
  port map(        clk => Bus2IP_Clk, -- v
416
                      reset => Bus2IP_Reset, -- v
417
                        -- operand memory interface (plb shared memory)
418
                         write_enable => core_write_enable,
419
               data_in => core_data_in,
420
            rw_address => core_rw_address,
421
              data_out => core_data_out,
422
                                 collision => core_mem_collision, -- v
423
                        -- op_sel fifo interface
424
                             fifo_din => core_fifo_din,
425
                            fifo_push => core_fifo_push,
426
                            fifo_full => core_fifo_full, -- v
427
                          fifo_nopush => core_fifo_nopush, -- v
428
                        -- ctrl signals
429
                                start => core_start, -- v
430
                             run_auto => core_run_auto, -- v
431
                                ready => core_ready, -- v
432
                    x_sel_single => core_x_sel_single, -- v
433
                    y_sel_single => core_y_sel_single, -- v
434
                  dest_op_single => core_dest_op_single, -- v
435
                 p_sel => core_p_sel, -- v
436
                                 calc_time => calc_time -- v
437
  );
438
 
439
  ------------------------------------------
440
  -- Drive IP to Bus signals
441
  ------------------------------------------
442
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
443
                  mem_ip2bus_data when mem_read_ack = '1' else
444
                  (others => '0');
445
 
446
  IP2Bus_WrAck <= slv_write_ack or mem_write_ack;
447
  IP2Bus_RdAck <= slv_read_ack or mem_read_ack;
448
  IP2Bus_Error <= '0';
449
 
450
end IMP;

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