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---- dpram_generic ----
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---- ----
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---- This file is part of the ----
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---- Modular Simultaneous Exponentiation Core project ----
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---- http://www.opencores.org/cores/mod_sim_exp/ ----
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---- ----
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---- Description ----
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---- behovorial description of a dual port ram with one 32-bit ----
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---- write port and one 32-bit read port ----
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---- ----
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---- Dependencies: none ----
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---- ----
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---- Authors: ----
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---- - Geoffrey Ottoy, DraMCo research group ----
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---- - Jonas De Craene, JonasDC@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2011 DraMCo research group and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library mod_sim_exp;
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use mod_sim_exp.std_functions.all;
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-- altera infers ramblocks from a depth of 9
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-- xilinx infers ramblocks from a depth of 2
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entity tdpram_generic is
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generic (
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depth : integer := 9
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);
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port (
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-- port A
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clkA : in std_logic;
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addrA : in std_logic_vector(log2(depth)-1 downto 0);
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weA : in std_logic;
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dinA : in std_logic_vector(31 downto 0);
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doutA : out std_logic_vector(31 downto 0);
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-- port B
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clkB : in std_logic;
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addrB : in std_logic_vector(log2(depth)-1 downto 0);
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weB : in std_logic;
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dinB : in std_logic_vector(31 downto 0);
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doutB : out std_logic_vector(31 downto 0)
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);
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end tdpram_generic;
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architecture behavorial of tdpram_generic is
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-- the memory
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type ram_type is array (depth-1 downto 0) of std_logic_vector (31 downto 0);
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shared variable RAM: ram_type;
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-- xilinx constraint to use blockram resources
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attribute ram_style : string;
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attribute ram_style of RAM:variable is "block";
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-- altera constraint
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--attribute ramstyle : string;
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--attribute ramstyle of RAM:variable is "M9K, no_rw_check";
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begin
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-- port A
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process (clkA)
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begin
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if (clkA'event and clkA = '1') then
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if ( weA = '1') then
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RAM(conv_integer(addrA)) := dinA ;
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end if;
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doutA <= RAM(conv_integer(addrA));
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end if;
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end process;
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-- port B
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process (clkB)
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begin
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if (clkB'event and clkB = '1') then
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if ( weB = '1') then
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RAM(conv_integer(addrB)) := dinB ;
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end if;
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doutB <= RAM(conv_integer(addrB));
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end if;
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end process;
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end behavorial;
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