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JonasDC |
##############################################################
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#
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# Xilinx Core Generator version 14.4
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# Date: Tue Jul 2 16:44:14 2013
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc7z020
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SET devicefamily = zynq
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = clg484
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -1
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
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# END Select
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# BEGIN Parameters
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CSET additional_inputs_for_power_estimation=false
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CSET algorithm=Minimum_Area
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CSET assume_synchronous_clk=false
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CSET axi_id_width=4
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CSET axi_slave_type=Memory_Slave
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CSET axi_type=AXI4_Full
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CSET byte_size=9
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CSET coe_file=no_coe_file_loaded
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CSET collision_warnings=ALL
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CSET component_name=operands_sp
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CSET disable_collision_warnings=false
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CSET disable_out_of_range_warnings=false
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CSET ecc=false
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CSET ecctype=No_ECC
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CSET enable_32bit_address=false
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CSET enable_a=Always_Enabled
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CSET enable_b=Always_Enabled
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CSET error_injection_type=Single_Bit_Error_Injection
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CSET fill_remaining_memory_locations=false
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CSET interface_type=Native
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CSET load_init_file=false
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CSET mem_file=no_Mem_file_loaded
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CSET memory_type=Single_Port_RAM
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CSET operating_mode_a=WRITE_FIRST
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CSET operating_mode_b=WRITE_FIRST
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CSET output_reset_value_a=0
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CSET output_reset_value_b=0
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CSET pipeline_stages=0
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CSET port_a_clock=100
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CSET port_a_enable_rate=100
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CSET port_a_write_rate=50
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CSET port_b_clock=100
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CSET port_b_enable_rate=100
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CSET port_b_write_rate=50
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CSET primitive=8kx2
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CSET read_width_a=512
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CSET read_width_b=32
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CSET register_porta_input_of_softecc=false
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CSET register_porta_output_of_memory_core=false
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CSET register_porta_output_of_memory_primitives=false
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CSET register_portb_output_of_memory_core=false
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CSET register_portb_output_of_memory_primitives=false
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CSET register_portb_output_of_softecc=false
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CSET remaining_memory_locations=0
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CSET reset_memory_latch_a=false
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CSET reset_memory_latch_b=false
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CSET reset_priority_a=CE
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CSET reset_priority_b=CE
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CSET reset_type=SYNC
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CSET softecc=false
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CSET use_axi_id=false
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CSET use_bram_block=Stand_Alone
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CSET use_byte_write_enable=false
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CSET use_error_injection_pins=false
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CSET use_regcea_pin=false
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CSET use_regceb_pin=false
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CSET use_rsta_pin=false
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CSET use_rstb_pin=false
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CSET write_depth_a=32
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CSET write_width_a=32
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CSET write_width_b=32
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-11-19T16:22:25Z
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# END Extra information
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GENERATE
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# CRC: 1a5b155a
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