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[/] [modbus/] [trunk/] [enlace/] [bin_ascii.vhd] - Blame information for rev 3

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1 3 guanucolui 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--  Uncomment the following lines to use the declarations that are
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--  provided for instantiating Xilinx primitive components.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity bin_ascii is
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        port(
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                clk             :in std_logic;
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                reset   :in std_logic;
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                bin             :in std_logic_vector(7 downto 0);
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                ascii_h :out std_logic_vector(7 downto 0);
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                ascii_l :out std_logic_vector(7 downto 0));
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end bin_ascii;
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architecture Behavioral of bin_ascii is
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signal  Sa_L                            :std_logic;
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signal  Sb_L                            :std_logic;
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signal  Sc_L                            :std_logic;
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signal  Sd_L                            :std_logic;
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signal  Sconvinacional_L        :std_logic;
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signal  Ssuma_L                 :std_logic_vector(7 downto 0);
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signal  Sa_H                            :std_logic;
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signal  Sb_H                            :std_logic;
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signal  Sc_H                            :std_logic;
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signal  Sd_H                            :std_logic;
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signal  Sconvinacional_H        :std_logic;
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signal  Ssuma_H                 :std_logic_vector(7 downto 0);
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begin
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--**************************************************************
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-- Obtención código ascii de la parte baja
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--**************************************************************
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mayor_cero_L:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(3 downto 0) >= "0000" ) then --si es mayor que 0 binario
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         Sa_L <= '1';
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      else
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         Sa_L <= '0';
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      end if;
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   end if;
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end process;
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menor_nueve_L:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(3 downto 0) <= "1001" ) then --si es menor que 9  binario
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         Sb_L <= '1';
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      else
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         Sb_L <= '0';
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      end if;
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   end if;
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end process;
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mayor_10_L:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(3 downto 0) >= "1010" ) then --si es mayor que 10 binario
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         Sc_L <= '1';
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      else
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         Sc_L <= '0';
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      end if;
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   end if;
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end process;
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menor_F_L:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(3 downto 0) <= "1111" ) then --si es menor que 15 binario
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         Sd_L <= '1';
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      else
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         Sd_L <= '0';
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      end if;
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   end if;
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end process;
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--**************************************************************
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-- Obtención código ascii de la parte alta
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--**************************************************************
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mayor_cero_H:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(7 downto 4) >= "0000" ) then --si es mayor que 0 binario
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         Sa_H <= '1';
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      else
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         Sa_H <= '0';
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      end if;
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   end if;
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end process;
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menor_nueve_H:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(7 downto 4) <= "1001" ) then --si es menor que 9  binario
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         Sb_H <= '1';
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      else
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         Sb_H <= '0';
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      end if;
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   end if;
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end process;
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mayor_10_H:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(7 downto 4) >= "1010" ) then --si es mayor que 10 binario
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         Sc_H <= '1';
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      else
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         Sc_H <= '0';
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      end if;
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   end if;
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end process;
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menor_15_H:process(clk)
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begin
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   if (clk'event and clk ='1') then
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      if ( bin(7 downto 4) <= "1111" ) then --si es menor que 15 binario
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         Sd_H <= '1';
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      else
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         Sd_H <= '0';
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      end if;
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   end if;
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end process;
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--**************************************************************
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-- Logica convinacional para la obtención del código ascii bajo
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--**************************************************************
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Sconvinacional_L<= (not(Sa_L and not Sb_L and Sc_L and Sd_L)) or (Sa_L and Sb_L and not Sc_L and Sd_L); --controla cual es el sustraendo (0 o A-10)
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Ssuma_L <= "00110000" WHEN Sconvinacional_L ='1' ELSE --es el mutiplexor controlado por Sconvinacional para definir lo sumado
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             "00110111";  -- valor equivalente a el ascii 'A'
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ascii_L <= bin(3 downto 0) + Ssuma_L;
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--**************************************************************
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-- Logica convinacional para la obtención del código ascii alto
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--**************************************************************
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Sconvinacional_H<= (not(Sa_H and not Sb_H and Sc_H and Sd_H)) or (Sa_H and Sb_H and not Sc_H and Sd_H); --controla cual es el sustraendo (0 o A-10)
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Ssuma_H <= "00110000" WHEN Sconvinacional_H ='1' ELSE --es el mutiplexor controlado por Sconvinacional para definir lo sumado
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             "00110111";  -- valor equivalente a el ascii 'A'
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ascii_H <= bin(7 downto 4) + Ssuma_H;
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end Behavioral;

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