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guanucolui |
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-- Company: University of Vigo
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-- Engineer: L. Jacobo Alvarez Ruiz de Ojeda
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--
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-- Create Date: 10:07:16 10/20/06
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-- Design Name:
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-- Module Name: clock_generator_for_uart_rs232 - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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-- This is a clock generator useful for the RS232 UART
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-- The uart_clock must have a frequency of eight times faster than the desired baud rate
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-- This clock generator obtains the uart_clock from a 50 MHz clock input
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-- Below are some values for the constant "divide_by", which allow to obtain some of the RS232 standard
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-- baud rates. Put the desired value in the definition of the constant or adapt this value if
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-- you need another baud rate or if your clock input frequency is other than 50 MHz.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity clock_generator_for_uart_rs232 is
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Port ( clk : in std_logic;
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reset : in std_logic;
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uart_clk : out std_logic);
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end clock_generator_for_uart_rs232;
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architecture Behavioral of clock_generator_for_uart_rs232 is
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constant divide_by: integer := 651;
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-- For 1200 bps, divide_by = 5208;
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-- For 2400 bps, divide_by = 2604;
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-- For 4800 bps, divide_by = 1302;
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-- For 9600 bps, divide_by = 651;
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-- For 19200 bps, divide_by = 325;
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-- For 38400 bps, divide_by = 163;
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-- For 57600 bps, divide_by = 108;
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-- For 115200 bps, divide_by = 54;
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-- For 230400 bps, divide_by = 27;
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-- For 460800 bps, divide_by = 13;
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-- For 921600 bps, divide_by = 7;
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-- For 1 Mbps, divide_by = 6;
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-- At the higher frequencies, the resulting frequency of the clock output has less accuracy, so maybe
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-- there will be some problems with bit snchronization. If this is the case, it is recommended to obtain
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-- the needed frequency through another tupe of circuit, like a DLL or PLL
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signal count: integer range 0 to ((divide_by / 2) - 1);
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signal clk_out: std_logic;
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begin
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uart_clk <= clk_out;
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process (clk, reset, count, clk_out)
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begin
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if reset = '1' then
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clk_out <='0';
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count <= 0;
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elsif
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clk='1' and clk'event then
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if count = ((divide_by / 2) - 1) then
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clk_out <= not clk_out;
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count <= 0;
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else count <= count+1;
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end if;
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end if;
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end process;
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end Behavioral;
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