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guanucolui |
-- C:\USER\XILINX_2006\UART_RS232\RX_CTRL.vhd
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-- VHDL code created by Xilinx's StateCAD 7.1i
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-- Thu Oct 19 16:59:23 2006
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-- This VHDL code (for use with Xilinx XST) was generated using:
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-- enumerated state assignment with structured code format.
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-- Minimization is enabled, implied else is disabled,
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-- and outputs are area optimized.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY RX_CTRL IS
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PORT (CLK,ctr_bits_eq_9,fd_rxd,last_sample,RESET,sampled_bit: IN std_logic;
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incr_ctr_bits,ld_parity_error,load_data,load_discrepancy,new_data,
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reset_busy,reset_capture,reset_ctr_bits,reset_ctr_clock,rst_ce_ctr_clock,
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rst_discrepancy,set_busy,set_capture,set_ce_ctr_clock,shift_enable,
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start_error,stop_error : OUT std_logic);
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END;
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ARCHITECTURE BEHAVIOR OF RX_CTRL IS
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TYPE type_sreg IS (IDLE,CHECK_9_BITS,CHECK_START_BIT,CHECK_STOP_BIT,END_RECEIVING,
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SHIFT_BIT,START_BIT_ERROR,START_RECEIVING,STOP_BIT_ERROR,STORE_DATA,
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WAIT_NEXT_BIT,WAIT_STOP_BIT);
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SIGNAL sreg, next_sreg : type_sreg;
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BEGIN
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PROCESS (CLK, RESET, next_sreg)
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BEGIN
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IF ( RESET='1' ) THEN
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sreg <= IDLE;
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ELSIF CLK='1' AND CLK'event THEN
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sreg <= next_sreg;
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END IF;
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END PROCESS;
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PROCESS (sreg,ctr_bits_eq_9,fd_rxd,last_sample,sampled_bit)
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BEGIN
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incr_ctr_bits <= '0'; ld_parity_error <= '0'; load_data <= '0';
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load_discrepancy <= '0'; new_data <= '0'; reset_busy <= '0'; reset_capture <=
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'0'; reset_ctr_bits <= '0'; reset_ctr_clock <= '0'; rst_ce_ctr_clock <= '0';
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rst_discrepancy <= '0'; set_busy <= '0'; set_capture <= '0';
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set_ce_ctr_clock <= '0'; shift_enable <= '0'; start_error <= '0'; stop_error
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<= '0';
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next_sreg<=IDLE;
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IF NOT ( (sreg=CHECK_9_BITS) OR (sreg=CHECK_START_BIT) OR (
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sreg=CHECK_STOP_BIT) OR (sreg=END_RECEIVING) OR (sreg=IDLE) OR (
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sreg=SHIFT_BIT) OR (sreg=START_BIT_ERROR) OR (sreg=START_RECEIVING) OR (
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sreg=STOP_BIT_ERROR) OR (sreg=STORE_DATA) OR (sreg=WAIT_NEXT_BIT) OR (
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sreg=WAIT_STOP_BIT)) THEN next_sreg<=IDLE;
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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ELSE
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CASE sreg IS
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WHEN CHECK_9_BITS =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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rst_discrepancy<='1';
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IF ( ctr_bits_eq_9='1' ) THEN
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next_sreg<=STORE_DATA;
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ELSE
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next_sreg<=WAIT_NEXT_BIT;
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END IF;
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WHEN CHECK_START_BIT =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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IF ( sampled_bit='0' ) THEN
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next_sreg<=WAIT_NEXT_BIT;
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ELSE
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next_sreg<=START_BIT_ERROR;
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END IF;
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WHEN CHECK_STOP_BIT =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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IF ( sampled_bit='1' ) THEN
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next_sreg<=END_RECEIVING;
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ELSE
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next_sreg<=STOP_BIT_ERROR;
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END IF;
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WHEN END_RECEIVING =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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reset_capture<='1';
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rst_ce_ctr_clock<='1';
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reset_ctr_clock<='1';
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reset_ctr_bits<='1';
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new_data<='1';
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reset_busy<='1';
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next_sreg<=IDLE;
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WHEN IDLE =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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IF ( fd_rxd='1' ) THEN
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next_sreg<=START_RECEIVING;
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ELSE
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next_sreg<=IDLE;
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END IF;
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WHEN SHIFT_BIT =>
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ld_parity_error<='0';
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load_data<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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start_error<='0';
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stop_error<='0';
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shift_enable<='1';
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incr_ctr_bits<='1';
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load_discrepancy<='1';
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next_sreg<=CHECK_9_BITS;
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WHEN START_BIT_ERROR =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_ctr_bits<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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stop_error<='0';
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reset_capture<='1';
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rst_ce_ctr_clock<='1';
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reset_ctr_clock<='1';
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start_error<='1';
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reset_busy<='1';
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next_sreg<=IDLE;
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WHEN START_RECEIVING =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='0';
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set_capture<='1';
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set_ce_ctr_clock<='1';
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set_busy<='1';
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IF ( last_sample='1' ) THEN
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next_sreg<=CHECK_START_BIT;
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ELSE
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next_sreg<=START_RECEIVING;
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END IF;
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WHEN STOP_BIT_ERROR =>
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incr_ctr_bits<='0';
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ld_parity_error<='0';
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load_data<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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start_error<='0';
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stop_error<='1';
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next_sreg<=END_RECEIVING;
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WHEN STORE_DATA =>
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incr_ctr_bits<='0';
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load_discrepancy<='0';
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new_data<='0';
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reset_busy<='0';
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reset_capture<='0';
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| 268 |
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reset_ctr_bits<='0';
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reset_ctr_clock<='0';
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rst_ce_ctr_clock<='0';
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| 271 |
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rst_discrepancy<='0';
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set_busy<='0';
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set_capture<='0';
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| 274 |
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set_ce_ctr_clock<='0';
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shift_enable<='0';
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| 276 |
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start_error<='0';
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| 277 |
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stop_error<='0';
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| 278 |
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ld_parity_error<='1';
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| 279 |
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load_data<='1';
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next_sreg<=WAIT_STOP_BIT;
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WHEN WAIT_NEXT_BIT =>
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| 282 |
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incr_ctr_bits<='0';
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| 283 |
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ld_parity_error<='0';
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| 284 |
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load_data<='0';
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| 285 |
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load_discrepancy<='0';
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| 286 |
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new_data<='0';
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| 287 |
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reset_busy<='0';
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| 288 |
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reset_capture<='0';
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| 289 |
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reset_ctr_bits<='0';
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| 290 |
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reset_ctr_clock<='0';
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| 291 |
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rst_ce_ctr_clock<='0';
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| 292 |
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rst_discrepancy<='0';
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| 293 |
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set_busy<='0';
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| 294 |
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set_capture<='0';
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| 295 |
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set_ce_ctr_clock<='0';
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| 296 |
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shift_enable<='0';
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start_error<='0';
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| 298 |
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stop_error<='0';
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| 299 |
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IF ( last_sample='1' ) THEN
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next_sreg<=SHIFT_BIT;
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ELSE
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next_sreg<=WAIT_NEXT_BIT;
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END IF;
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| 304 |
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WHEN WAIT_STOP_BIT =>
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incr_ctr_bits<='0';
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| 306 |
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ld_parity_error<='0';
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| 307 |
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load_data<='0';
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| 308 |
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load_discrepancy<='0';
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| 309 |
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new_data<='0';
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| 310 |
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reset_busy<='0';
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| 311 |
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reset_capture<='0';
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| 312 |
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reset_ctr_bits<='0';
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| 313 |
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reset_ctr_clock<='0';
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| 314 |
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rst_ce_ctr_clock<='0';
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| 315 |
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rst_discrepancy<='0';
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| 316 |
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set_busy<='0';
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| 317 |
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set_capture<='0';
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| 318 |
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set_ce_ctr_clock<='0';
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| 319 |
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shift_enable<='0';
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| 320 |
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start_error<='0';
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| 321 |
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stop_error<='0';
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| 322 |
|
|
IF ( last_sample='1' ) THEN
|
| 323 |
|
|
next_sreg<=CHECK_STOP_BIT;
|
| 324 |
|
|
ELSE
|
| 325 |
|
|
next_sreg<=WAIT_STOP_BIT;
|
| 326 |
|
|
END IF;
|
| 327 |
|
|
WHEN OTHERS =>
|
| 328 |
|
|
END CASE;
|
| 329 |
|
|
END IF;
|
| 330 |
|
|
END PROCESS;
|
| 331 |
|
|
END BEHAVIOR;
|
