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[/] [modbus/] [trunk/] [enlace/] [uart_TB.vhd] - Blame information for rev 3

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1 3 guanucolui 
 
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-- VHDL Test Bench Created from source file uart_rs232.vhd -- 21:28:36 07/21/2010
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY uart_rs232_uart_TB_vhd_tb IS
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END uart_rs232_uart_TB_vhd_tb;
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ARCHITECTURE behavior OF uart_rs232_uart_TB_vhd_tb IS
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        COMPONENT uart_rs232
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        PORT(
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                clk : IN std_logic;
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                reset : IN std_logic;
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                send_data : IN std_logic;
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                data_in : IN std_logic_vector(7 downto 0);
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                even_odd : IN std_logic;
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                rxd : IN std_logic;
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                txd : OUT std_logic;
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                transmitter_busy : OUT std_logic;
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                send_done : OUT std_logic;
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                data_out : OUT std_logic_vector(7 downto 0);
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                parity_error : OUT std_logic;
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                start_error : OUT std_logic;
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                stop_error : OUT std_logic;
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                discrepancy_error : OUT std_logic;
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                receiver_busy : OUT std_logic;
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                new_data : OUT std_logic
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                );
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        END COMPONENT;
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        SIGNAL clk :  std_logic;
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        SIGNAL reset :  std_logic;
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        SIGNAL send_data :  std_logic;
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        SIGNAL data_in :  std_logic_vector(7 downto 0);
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        SIGNAL even_odd :  std_logic;
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        SIGNAL rxd :  std_logic;
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        SIGNAL txd :  std_logic:='1';
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        SIGNAL transmitter_busy :  std_logic;
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        SIGNAL send_done :  std_logic;
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        SIGNAL data_out :  std_logic_vector(7 downto 0);
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        SIGNAL parity_error :  std_logic;
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        SIGNAL start_error :  std_logic;
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        SIGNAL stop_error :  std_logic;
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        SIGNAL discrepancy_error :  std_logic;
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        SIGNAL receiver_busy :  std_logic;
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        SIGNAL new_data :  std_logic;
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58 
 
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        signal comiezo  :       std_logic_vector(7 downto 0):= "01010101";
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        signal segundo :        std_logic_vector(7 downto 0):= "11100111";
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     signal dospuntos : std_logic_vector(7 downto 0):= "00111010";               --: ascii
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     signal cero         :      std_logic_vector(7 downto 0):= "00110000";               --0 ascii
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        signal siete     :      std_logic_vector(7 downto 0):="00110111";                --7 ascii
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        signal uno      :       std_logic_vector(7 downto 0):="00110001";                --1 ascii
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        signal ocho     :std_logic_vector(7 downto 0):= "00111000";              --8 ascii
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        signal la_a     :std_logic_vector(7 downto 0):=  "01000001";             --A ascii
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        signal cinco   :std_logic_vector(7 downto 0):=   "00110101";             --5 ascii
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        signal la_f     :std_logic_vector(7 downto 0):= "01000110";              --F ascii
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        signal cr               :std_logic_vector(7 downto 0):= "00001101";              --CR ascii
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        signal lf               :std_logic_vector(7 downto 0):= "00001010";              --LF ascii
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           -- Clock period definitions
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   constant clk_period : time := 20ns;
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BEGIN
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        uut: uart_rs232 PORT MAP(
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                clk => clk,
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                reset => reset,
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                send_data => send_data,
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                data_in => data_in,
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                even_odd => even_odd,
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                rxd => rxd,
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                txd => txd,
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                transmitter_busy => transmitter_busy,
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                send_done => send_done,
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                data_out => data_out,
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                parity_error => parity_error,
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                start_error => start_error,
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                stop_error => stop_error,
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                discrepancy_error => discrepancy_error,
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                receiver_busy => receiver_busy,
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                new_data => new_data
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        );
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            -- Clock process definitions
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   clk_process :process
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   begin
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                clk <= '0';
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                wait for clk_period/2;
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                clk <= '1';
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                wait for clk_period/2;
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   end process;
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-- *** Test Bench - User Defined Section ***
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   tb : PROCESS
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   BEGIN
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                wait for 100ns;
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                reset <= '1';
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                send_data <='0';
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                data_in <= "00000000";
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                even_odd <= '1';
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                wait for 100ns;
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                reset <= '0';
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--trama 1
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                wait for 300us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= comiezo(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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--trama 2
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= segundo(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dos puntos
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= dospuntos(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dire alto       0 ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= cero(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dire bajo       7 ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= siete(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama función alto    0 ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= cero(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama función bajo    1 ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= uno(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dato1 alto      8 ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= ocho(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dato1 bajo      A ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <= la_a(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dato2 alto      5 ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <=  cinco(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama dato2 bajo      f ascii
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <=  la_f(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama cr
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
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                rxd <=  cr(i);
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                        wait for 104us;
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                end loop;
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                rxd <= '0';
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                wait for 104us;
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                rxd <= '1';
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 --trama lf
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                wait for 500us;
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                rxd <= '0';
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                wait for  104us;
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                for i in 0 to 7 loop
273 
                rxd <=  lf(i);
274 
                        wait for 104us;
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                end loop;
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                rxd <= '0';
277 
                wait for 104us;
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                rxd <= '1';
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281 
        data_in <= "10101101";
282 
        wait for 200us;
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        send_data <= '1';
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        wait for 120us;
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        send_data <= '0';
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289 
      wait; -- will wait forever
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   END PROCESS;
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-- *** End Test Bench - User Defined Section ***
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END;

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