URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [design/] [RVI/] [modular_oscilloscope/] [simulation/] [modelsim.ini.sav] - Blame information for rev 62

Details | Compare with Previous | View Log


[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3e = C:/Actel/Libero_v8.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e
 
 
 
 
 
postsynth = postsynth
presynth = presynth
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
postlayout = ../designer/impl3/simulation/postlayout
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
syncad_vhdl_lib = C:\Actel\Libero_v8.5\Designer/lib/actel/syncad_vhdl_lib
 
[vcom]
VHDL93 = 1
 
[vsim]
IterationLimit = 5000

Line No.	Rev	Author	Line
1	62	budinero	`[Library]`
2			`others = $MODEL_TECH/../modelsim.ini`
3			`proasic3e = C:/Actel/Libero_v8.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e`
4
5
6
7
8
9			`postsynth = postsynth`
10			`presynth = presynth`
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27			`postlayout = ../designer/impl3/simulation/postlayout`
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76			`syncad_vhdl_lib = C:\Actel\Libero_v8.5\Designer/lib/actel/syncad_vhdl_lib`
77
78			`[vcom]`
79			`VHDL93 = 1`
80
81			`[vsim]`
82			`IterationLimit = 5000`

Browse

Tools

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [design/] [RVI/] [modular_oscilloscope/] [simulation/] [modelsim.ini.sav] - Blame information for rev 62