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[/] [modular_oscilloscope/] [trunk/] [hdl/] [ctrl/] [generic_counter.vhd] - Blame information for rev 33

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-------------------------------------------------------------------------------------------------100
--| Modular Oscilloscope
--| UNSL - Argentine
--|
--| File: generic_counter.vhd
--| Version: 0.1
--| Tested in: Actel A3PE1500
--|   Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   CONTROL - Counter
--|   This is a simple counter
--|   
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.1   | jul-2009 | First release
----------------------------------------------------------------------------------------------------
--| Copyright � 2009, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
 
 
 
--==================================================================================================
-- TODO
-- � ...
--==================================================================================================
 
 
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
--use ieee.math_real.all
 
 
 
 
 
entity generic_counter is
  generic(
    OUTPUT_WIDTH: integer := 32 -- Output width for counter.
  );
  port(
    clk_I:    in  std_logic;
    count_O:  out std_logic_vector( OUTPUT_WIDTH-1  downto 0);
    reset_I:  in  std_logic;
    enable_I: in  std_logic
  );
end entity generic_counter;
 
 
 
 
architecture arch01 of generic_counter is
  signal count: std_logic_vector( OUTPUT_WIDTH-1  downto 0);
begin
 
  count_O <= count;
 
  P_count: process(clk_I, reset_I, count, enable_I)
  begin
    if clk_I'event and clk_I = '1' and clk_I'LAST_VALUE = '0' then
      if reset_I = '1' then
        count <= (others => '0');
      elsif enable_I = '1' then
        count <= count + 1;
      end if;
    end if;
  end process;
 
end architecture;
 
 
 
 
 
 
-- Report for cell generic_counter.arch01
--   Core Cell usage:
--               cell count     area count*area
--               AOI1     2      1.0        2.0
--               BUFF     1      1.0        1.0
--                GND     1      0.0        0.0
--               NOR2     1      1.0        1.0
--              NOR2A     1      1.0        1.0
--              NOR2B    11      1.0       11.0
--               NOR3     2      1.0        2.0
--              NOR3B     2      1.0        2.0
--              NOR3C    15      1.0       15.0
--               OR2A    19      1.0       19.0
--               OR2B     3      1.0        3.0
--               OR3B     1      1.0        1.0
--               OR3C     2      1.0        2.0
--                VCC     1      0.0        0.0
--               XA1B     6      1.0        6.0
--               XA1C    24      1.0       24.0
-- 
-- 
--               DFN1    33      1.0       33.0
--                    -----          ----------
--              TOTAL   125               123.0
-- 
-- 
--   IO Cell usage:
--               cell count
--             CLKBUF     1
--              INBUF     1
--             OUTBUF    33
--                    -----
--              TOTAL    35
-- 
-- 
-- Core Cells         : 123 of 38400 (0%)
-- IO Cells           : 35
 
--                           Requested     Estimated     Requested     Estimated               Clock        Clock              
-- Starting Clock            Frequency     Frequency     Period        Period        Slack     Type         Group              
-- ----------------------------------------------------------------------------------------------------------------------------
-- generic_counter|clk_I     100.0 MHz     110.8 MHz     10.000        9.026         0.974     inferred     Inferred_clkgroup_0
-- ============================================================================================================================
 
 
 
 
 
 
 
-- -- Version: 8.5 SP1 8.5.1.13
-- 
-- library ieee;
-- use ieee.std_logic_1164.all;
-- library proasic3e;
-- use proasic3e.all;
-- 
-- entity counter is
-- 
--     port( Sload  : in    std_logic;
--           Clock  : in    std_logic;
--           Data   : in    std_logic_vector(14 downto 0);
--           Enable : in    std_logic;
--           Q      : out   std_logic_vector(14 downto 0)
--         );
-- 
-- end counter;
-- 
-- architecture DEF_ARCH of counter is 
-- 
--   component AND2
--     port( A : in    std_logic := 'U';
--           B : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component MX2
--     port( A : in    std_logic := 'U';
--           B : in    std_logic := 'U';
--           S : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component XOR2
--     port( A : in    std_logic := 'U';
--           B : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component AND3
--     port( A : in    std_logic := 'U';
--           B : in    std_logic := 'U';
--           C : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component DFN1E1
--     port( D   : in    std_logic := 'U';
--           CLK : in    std_logic := 'U';
--           E   : in    std_logic := 'U';
--           Q   : out   std_logic
--         );
--   end component;
-- 
--   component INV
--     port( A : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component BUFF
--     port( A : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component OR2
--     port( A : in    std_logic := 'U';
--           B : in    std_logic := 'U';
--           Y : out   std_logic
--         );
--   end component;
-- 
--   component DFN1
--     port( D   : in    std_logic := 'U';
--           CLK : in    std_logic := 'U';
--           Q   : out   std_logic
--         );
--   end component;
-- 
--     signal N_Sload_0, N_Sload_1, N_Q_0, N_Q_1, N_Q_2, N_Q_3, 
--         N_Q_4, N_Q_5, N_Q_6, N_Q_7, N_Q_8, N_INV_Q0_Y, N_LA_0_LA, 
--         N_Q_9, N_Q_10, N_Q_11, N_Q_12, N_Q_13, N_Q_14, AND3_3_Y, 
--         OR2_0_Y, AND3_9_Y, AND2_4_Y, AND2_8_Y, AND2_9_Y, 
--         AND3_11_Y, MX2_6_Y, XOR2_8_Y, MX2_12_Y, XOR2_11_Y, 
--         MX2_10_Y, INV_0_Y, MX2_11_Y, XOR2_0_Y, MX2_8_Y, XOR2_2_Y, 
--         MX2_0_Y, XOR2_6_Y, AND2_2_Y, MX2_9_Y, XOR2_12_Y, 
--         AND2_10_Y, MX2_7_Y, XOR2_5_Y, AND2_6_Y, MX2_1_Y, XOR2_4_Y, 
--         AND2_1_Y, AND3_4_Y, OR2_1_Y, AND3_10_Y, AND2_5_Y, 
--         AND2_0_Y, MX2_2_Y, XOR2_7_Y, MX2_13_Y, INV_1_Y, MX2_15_Y, 
--         XOR2_10_Y, MX2_5_Y, XOR2_1_Y, MX2_14_Y, XOR2_3_Y, 
--         AND2_3_Y, MX2_4_Y, XOR2_9_Y, AND2_7_Y, OR2_2_Y, AND3_5_Y, 
--         MX2_3_Y, AND3_1_Y, AND3_6_Y, AND3_7_Y, AND3_2_Y, AND3_0_Y, 
--         AND3_12_Y, AND3_8_Y : std_logic;
-- 
-- begin 
-- 
--     Q(14) <= N_Q_14;
--     Q(13) <= N_Q_13;
--     Q(12) <= N_Q_12;
--     Q(11) <= N_Q_11;
--     Q(10) <= N_Q_10;
--     Q(9) <= N_Q_9;
--     Q(8) <= N_Q_8;
--     Q(7) <= N_Q_7;
--     Q(6) <= N_Q_6;
--     Q(5) <= N_Q_5;
--     Q(4) <= N_Q_4;
--     Q(3) <= N_Q_3;
--     Q(2) <= N_Q_2;
--     Q(1) <= N_Q_1;
--     Q(0) <= N_Q_0;
-- 
--     AND2_9 : AND2
--       port map(A => N_Q_5, B => N_Q_6, Y => AND2_9_Y);
--     
--     MX2_12 : MX2
--       port map(A => XOR2_11_Y, B => Data(1), S => N_Sload_0, Y
--          => MX2_12_Y);
--     
--     XOR2_9 : XOR2
--       port map(A => N_Q_14, B => AND2_7_Y, Y => XOR2_9_Y);
--     
--     AND3_5 : AND3
--       port map(A => AND3_6_Y, B => AND3_7_Y, C => AND3_2_Y, Y => 
--         AND3_5_Y);
--     
--     AND3_10 : AND3
--       port map(A => N_Q_10, B => N_Q_11, C => N_Q_12, Y => 
--         AND3_10_Y);
--     
--     MX2_10 : MX2
--       port map(A => INV_0_Y, B => Data(2), S => N_Sload_0, Y => 
--         MX2_10_Y);
--     
--     DFN1E1_N_Q_2 : DFN1E1
--       port map(D => MX2_10_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_2);
--     
--     MX2_7 : MX2
--       port map(A => XOR2_5_Y, B => Data(7), S => N_Sload_0, Y => 
--         MX2_7_Y);
--     
--     MX2_15 : MX2
--       port map(A => XOR2_10_Y, B => Data(11), S => N_Sload_1, Y
--          => MX2_15_Y);
--     
--     DFN1E1_N_Q_6 : DFN1E1
--       port map(D => MX2_9_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_6);
--     
--     XOR2_1 : XOR2
--       port map(A => N_Q_12, B => AND2_0_Y, Y => XOR2_1_Y);
--     
--     XOR2_10 : XOR2
--       port map(A => N_Q_11, B => N_Q_10, Y => XOR2_10_Y);
--     
--     DFN1E1_N_LA_0_LA : DFN1E1
--       port map(D => MX2_3_Y, CLK => Clock, E => OR2_2_Y, Q => 
--         N_LA_0_LA);
--     
--     AND3_2 : AND3
--       port map(A => Data(6), B => Data(7), C => Data(8), Y => 
--         AND3_2_Y);
--     
--     AND2_0 : AND2
--       port map(A => N_Q_10, B => N_Q_11, Y => AND2_0_Y);
--     
--     XOR2_7 : XOR2
--       port map(A => N_Q_9, B => AND2_5_Y, Y => XOR2_7_Y);
--     
--     MX2_2 : MX2
--       port map(A => XOR2_7_Y, B => Data(9), S => N_Sload_0, Y => 
--         MX2_2_Y);
--     
--     AND3_9 : AND3
--       port map(A => N_Q_2, B => N_Q_3, C => N_Q_4, Y => AND3_9_Y);
--     
--     DFN1E1_N_Q_3 : DFN1E1
--       port map(D => MX2_11_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_3);
--     
--     INV_1 : INV
--       port map(A => N_Q_10, Y => INV_1_Y);
--     
--     U_BUFF_ld_1 : BUFF
--       port map(A => Sload, Y => N_Sload_1);
--     
--     AND2_2 : AND2
--       port map(A => N_Q_4, B => AND2_8_Y, Y => AND2_2_Y);
--     
--     MX2_1 : MX2
--       port map(A => XOR2_4_Y, B => Data(8), S => N_Sload_0, Y => 
--         MX2_1_Y);
--     
--     AND2_8 : AND2
--       port map(A => N_Q_2, B => N_Q_3, Y => AND2_8_Y);
--     
--     AND2_5 : AND2
--       port map(A => Enable, B => N_LA_0_LA, Y => AND2_5_Y);
--     
--     AND3_7 : AND3
--       port map(A => Data(3), B => Data(4), C => Data(5), Y => 
--         AND3_7_Y);
--     
--     AND3_6 : AND3
--       port map(A => Data(0), B => Data(1), C => Data(2), Y => 
--         AND3_6_Y);
--     
--     AND2_4 : AND2
--       port map(A => Enable, B => N_Q_0, Y => AND2_4_Y);
--     
--     AND2_1 : AND2
--       port map(A => AND3_11_Y, B => AND3_9_Y, Y => AND2_1_Y);
--     
--     AND3_11 : AND3
--       port map(A => N_Q_5, B => N_Q_6, C => N_Q_7, Y => AND3_11_Y);
--     
--     AND2_3 : AND2
--       port map(A => N_Q_12, B => AND2_0_Y, Y => AND2_3_Y);
--     
--     MX2_0 : MX2
--       port map(A => XOR2_6_Y, B => Data(5), S => N_Sload_0, Y => 
--         MX2_0_Y);
--     
--     AND2_7 : AND2
--       port map(A => N_Q_13, B => AND3_10_Y, Y => AND2_7_Y);
--     
--     AND3_0 : AND3
--       port map(A => N_INV_Q0_Y, B => N_Q_1, C => N_Q_2, Y => 
--         AND3_0_Y);
--     
--     AND3_12 : AND3
--       port map(A => N_Q_3, B => N_Q_4, C => N_Q_5, Y => AND3_12_Y);
--     
--     AND3_8 : AND3
--       port map(A => N_Q_6, B => N_Q_7, C => N_Q_8, Y => AND3_8_Y);
--     
--     OR2_0 : OR2
--       port map(A => N_Sload_0, B => AND3_3_Y, Y => OR2_0_Y);
--     
--     XOR2_12 : XOR2
--       port map(A => N_Q_6, B => AND2_10_Y, Y => XOR2_12_Y);
--     
--     DFN1E1_N_Q_7 : DFN1E1
--       port map(D => MX2_7_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_7);
--     
--     U_BUFF_ld_0 : BUFF
--       port map(A => Sload, Y => N_Sload_0);
--     
--     XOR2_3 : XOR2
--       port map(A => N_Q_13, B => AND2_3_Y, Y => XOR2_3_Y);
--     
--     MX2_5 : MX2
--       port map(A => XOR2_1_Y, B => Data(12), S => N_Sload_1, Y
--          => MX2_5_Y);
--     
--     MX2_14 : MX2
--       port map(A => XOR2_3_Y, B => Data(13), S => N_Sload_1, Y
--          => MX2_14_Y);
--     
--     AND2_6 : AND2
--       port map(A => AND2_9_Y, B => AND3_9_Y, Y => AND2_6_Y);
--     
--     MX2_9 : MX2
--       port map(A => XOR2_12_Y, B => Data(6), S => N_Sload_0, Y
--          => MX2_9_Y);
--     
--     DFN1E1_N_Q_12 : DFN1E1
--       port map(D => MX2_5_Y, CLK => Clock, E => OR2_1_Y, Q => 
--         N_Q_12);
--     
--     DFN1_N_Q_9 : DFN1
--       port map(D => MX2_2_Y, CLK => Clock, Q => N_Q_9);
--     
--     MX2_4 : MX2
--       port map(A => XOR2_9_Y, B => Data(14), S => N_Sload_1, Y
--          => MX2_4_Y);
--     
--     DFN1E1_N_Q_4 : DFN1E1
--       port map(D => MX2_8_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_4);
--     
--     DFN1E1_N_Q_11 : DFN1E1
--       port map(D => MX2_15_Y, CLK => Clock, E => OR2_1_Y, Q => 
--         N_Q_11);
--     
--     XOR2_0 : XOR2
--       port map(A => N_Q_3, B => N_Q_2, Y => XOR2_0_Y);
--     
--     AND3_3 : AND3
--       port map(A => Enable, B => N_Q_0, C => N_Q_1, Y => AND3_3_Y);
--     
--     DFN1E1_N_Q_5 : DFN1E1
--       port map(D => MX2_0_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_5);
--     
--     AND2_10 : AND2
--       port map(A => N_Q_5, B => AND3_9_Y, Y => AND2_10_Y);
--     
--     U_INV_Q0 : INV
--       port map(A => N_Q_0, Y => N_INV_Q0_Y);
--     
--     AND3_1 : AND3
--       port map(A => AND3_0_Y, B => AND3_12_Y, C => AND3_8_Y, Y
--          => AND3_1_Y);
--     
--     XOR2_5 : XOR2
--       port map(A => N_Q_7, B => AND2_6_Y, Y => XOR2_5_Y);
--     
--     DFN1_N_Q_0 : DFN1
--       port map(D => MX2_6_Y, CLK => Clock, Q => N_Q_0);
--     
--     OR2_1 : OR2
--       port map(A => N_Sload_0, B => AND3_4_Y, Y => OR2_1_Y);
--     
--     XOR2_2 : XOR2
--       port map(A => N_Q_4, B => AND2_8_Y, Y => XOR2_2_Y);
--     
--     DFN1_N_Q_1 : DFN1
--       port map(D => MX2_12_Y, CLK => Clock, Q => N_Q_1);
--     
--     XOR2_6 : XOR2
--       port map(A => N_Q_5, B => AND2_2_Y, Y => XOR2_6_Y);
--     
--     MX2_6 : MX2
--       port map(A => XOR2_8_Y, B => Data(0), S => N_Sload_0, Y => 
--         MX2_6_Y);
--     
--     XOR2_4 : XOR2
--       port map(A => N_Q_8, B => AND2_1_Y, Y => XOR2_4_Y);
--     
--     XOR2_8 : XOR2
--       port map(A => N_Q_0, B => Enable, Y => XOR2_8_Y);
--     
--     DFN1E1_N_Q_8 : DFN1E1
--       port map(D => MX2_1_Y, CLK => Clock, E => OR2_0_Y, Q => 
--         N_Q_8);
--     
--     MX2_13 : MX2
--       port map(A => INV_1_Y, B => Data(10), S => N_Sload_0, Y => 
--         MX2_13_Y);
--     
--     XOR2_11 : XOR2
--       port map(A => N_Q_1, B => AND2_4_Y, Y => XOR2_11_Y);
--     
--     INV_0 : INV
--       port map(A => N_Q_2, Y => INV_0_Y);
--     
--     DFN1E1_N_Q_13 : DFN1E1
--       port map(D => MX2_14_Y, CLK => Clock, E => OR2_1_Y, Q => 
--         N_Q_13);
--     
--     DFN1E1_N_Q_10 : DFN1E1
--       port map(D => MX2_13_Y, CLK => Clock, E => OR2_1_Y, Q => 
--         N_Q_10);
--     
--     DFN1E1_N_Q_14 : DFN1E1
--       port map(D => MX2_4_Y, CLK => Clock, E => OR2_1_Y, Q => 
--         N_Q_14);
--     
--     AND3_4 : AND3
--       port map(A => Enable, B => N_LA_0_LA, C => N_Q_9, Y => 
--         AND3_4_Y);
--     
--     MX2_3 : MX2
--       port map(A => AND3_1_Y, B => AND3_5_Y, S => N_Sload_0, Y
--          => MX2_3_Y);
--     
--     MX2_8 : MX2
--       port map(A => XOR2_2_Y, B => Data(4), S => N_Sload_0, Y => 
--         MX2_8_Y);
--     
--     OR2_2 : OR2
--       port map(A => N_Sload_0, B => Enable, Y => OR2_2_Y);
--     
--     MX2_11 : MX2
--       port map(A => XOR2_0_Y, B => Data(3), S => N_Sload_0, Y => 
--         MX2_11_Y);
--     
-- 
-- end DEF_ARCH; 
-- 
-- --================================================================================================--
-- -- Report for cell channel_selector.arch01
-- --   Core Cell usage:
-- --               cell count     area count*area
--               AND2     1      1.0        1.0
--                AO1     3      1.0        3.0
--               AOI1     3      1.0        3.0
--              AOI1B     1      1.0        1.0
--                AX1     1      1.0        1.0
--               AX1A     1      1.0        1.0
--               AX1C     2      1.0        2.0
--               AX1D     1      1.0        1.0
--               AX1E     2      1.0        2.0
--                GND     1      0.0        0.0
--                MX2    48      1.0       48.0
--               MX2B     1      1.0        1.0
--               MX2C    17      1.0       17.0
--               NOR2     7      1.0        7.0
--              NOR2A     9      1.0        9.0
--              NOR2B     7      1.0        7.0
--               NOR3     2      1.0        2.0
--              NOR3A     4      1.0        4.0
--              NOR3B     1      1.0        1.0
--              NOR3C     5      1.0        5.0
--               OA1A     1      1.0        1.0
--               OA1C     2      1.0        2.0
--               OAI1     1      1.0        1.0
--                OR2     6      1.0        6.0
--               OR2A     4      1.0        4.0
--               OR2B     8      1.0        8.0
--                OR3     1      1.0        1.0
--               OR3B     3      1.0        3.0
--               OR3C     5      1.0        5.0
--                VCC     1      0.0        0.0
--               XOR2     4      1.0        4.0
-- 
-- 
--               DFN1     4      1.0        4.0
--                    -----          ----------
--              TOTAL   157               155.0
-- 
-- 
--   IO Cell usage:
--               cell count
--             CLKBUF     1
--              INBUF    18
--             OUTBUF     4
--                    -----
--              TOTAL    23
-- 
-- 
-- Core Cells         : 155 of 38400 (0%)
-- IO Cells           : 23
 
--================================================================================================--
-- 
--                            Requested     Estimated     Requested     Estimated                Clock        Clock              
-- Starting Clock             Frequency     Frequency     Period        Period        Slack      Type         Group              
-- ------------------------------------------------------------------------------------------------------------------------------
-- channel_selector|clk_I     100.0 MHz     68.9 MHz      10.000        14.521        -4.521     inferred     Inferred_clkgroup_0
--
-- 
--================================================================================================--

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[/] [modular_oscilloscope/] [trunk/] [hdl/] [ctrl/] [generic_counter.vhd] - Blame information for rev 33

Line No.	Rev	Author	Line
1	32	budinero	`-------------------------------------------------------------------------------------------------100`
2			`--\| Modular Oscilloscope`
3			`--\| UNSL - Argentine`
4			`--\|`
5			`--\| File: generic_counter.vhd`
6			`--\| Version: 0.1`
7			`--\| Tested in: Actel A3PE1500`
8			`--\| Board: RVI Prototype Board + LP Data Conversion Daughter Board`
9			`--\|-------------------------------------------------------------------------------------------------`
10			`--\| Description:`
11			`--\| CONTROL - Counter`
12			`--\| This is a simple counter`
13			`--\|`
14			`--\|-------------------------------------------------------------------------------------------------`
15			`--\| File history:`
16			`--\| 0.1 \| jul-2009 \| First release`
17			`----------------------------------------------------------------------------------------------------`
18	33	budinero	`--\| Copyright � 2009, Facundo Aguilera.`
19	32	budinero	`--\|`
20			`--\| This VHDL design file is an open design; you can redistribute it and/or`
21			`--\| modify it and/or implement it after contacting the author.`
22			`----------------------------------------------------------------------------------------------------`
23
24
25
26
27
28			`--==================================================================================================`
29			`-- TODO`
30			`-- � ...`
31			`--==================================================================================================`
32
33
34			`library IEEE;`
35			`use ieee.std_logic_1164.all;`
36			`use ieee.std_logic_unsigned.all;`
37			`use IEEE.NUMERIC_STD.ALL;`
38			`--use ieee.math_real.all`
39
40
41
42
43
44			`entity generic_counter is`
45			`generic(`
46			`OUTPUT_WIDTH: integer := 32 -- Output width for counter.`
47			`);`
48			`port(`
49			`clk_I: in std_logic;`
50			`count_O: out std_logic_vector( OUTPUT_WIDTH-1 downto 0);`
51			`reset_I: in std_logic;`
52			`enable_I: in std_logic`
53			`);`
54			`end entity generic_counter;`
55
56
57
58
59			`architecture arch01 of generic_counter is`
60			`signal count: std_logic_vector( OUTPUT_WIDTH-1 downto 0);`
61			`begin`
62
63			`count_O <= count;`
64
65			`P_count: process(clk_I, reset_I, count, enable_I)`
66			`begin`
67			`if clk_I'event and clk_I = '1' and clk_I'LAST_VALUE = '0' then`
68			`if reset_I = '1' then`
69			`count <= (others => '0');`
70			`elsif enable_I = '1' then`
71			`count <= count + 1;`
72			`end if;`
73			`end if;`
74			`end process;`
75
76			`end architecture;`
77
78
79
80
81
82
83			`-- Report for cell generic_counter.arch01`
84			`-- Core Cell usage:`
85			`-- cell count area count*area`
86			`-- AOI1 2 1.0 2.0`
87			`-- BUFF 1 1.0 1.0`
88			`-- GND 1 0.0 0.0`
89			`-- NOR2 1 1.0 1.0`
90			`-- NOR2A 1 1.0 1.0`
91			`-- NOR2B 11 1.0 11.0`
92			`-- NOR3 2 1.0 2.0`
93			`-- NOR3B 2 1.0 2.0`
94			`-- NOR3C 15 1.0 15.0`
95			`-- OR2A 19 1.0 19.0`
96			`-- OR2B 3 1.0 3.0`
97			`-- OR3B 1 1.0 1.0`
98			`-- OR3C 2 1.0 2.0`
99			`-- VCC 1 0.0 0.0`
100			`-- XA1B 6 1.0 6.0`
101			`-- XA1C 24 1.0 24.0`
102			`--`
103			`--`
104			`-- DFN1 33 1.0 33.0`
105			`-- ----- ----------`
106			`-- TOTAL 125 123.0`
107			`--`
108			`--`
109			`-- IO Cell usage:`
110			`-- cell count`
111			`-- CLKBUF 1`
112			`-- INBUF 1`
113			`-- OUTBUF 33`
114			`-- -----`
115			`-- TOTAL 35`
116			`--`
117			`--`
118			`-- Core Cells : 123 of 38400 (0%)`
119			`-- IO Cells : 35`
120
121			`-- Requested Estimated Requested Estimated Clock Clock`
122			`-- Starting Clock Frequency Frequency Period Period Slack Type Group`
123			`-- ----------------------------------------------------------------------------------------------------------------------------`
124			`-- generic_counter\|clk_I 100.0 MHz 110.8 MHz 10.000 9.026 0.974 inferred Inferred_clkgroup_0`
125			`-- ============================================================================================================================`
126
127
128
129
130
131
132
133			`-- -- Version: 8.5 SP1 8.5.1.13`
134			`--`
135			`-- library ieee;`
136			`-- use ieee.std_logic_1164.all;`
137			`-- library proasic3e;`
138			`-- use proasic3e.all;`
139			`--`
140			`-- entity counter is`
141			`--`
142			`-- port( Sload : in std_logic;`
143			`-- Clock : in std_logic;`
144			`-- Data : in std_logic_vector(14 downto 0);`
145			`-- Enable : in std_logic;`
146			`-- Q : out std_logic_vector(14 downto 0)`
147			`-- );`
148			`--`
149			`-- end counter;`
150			`--`
151			`-- architecture DEF_ARCH of counter is`
152			`--`
153			`-- component AND2`
154			`-- port( A : in std_logic := 'U';`
155			`-- B : in std_logic := 'U';`
156			`-- Y : out std_logic`
157			`-- );`
158			`-- end component;`
159			`--`
160			`-- component MX2`
161			`-- port( A : in std_logic := 'U';`
162			`-- B : in std_logic := 'U';`
163			`-- S : in std_logic := 'U';`
164			`-- Y : out std_logic`
165			`-- );`
166			`-- end component;`
167			`--`
168			`-- component XOR2`
169			`-- port( A : in std_logic := 'U';`
170			`-- B : in std_logic := 'U';`
171			`-- Y : out std_logic`
172			`-- );`
173			`-- end component;`
174			`--`
175			`-- component AND3`
176			`-- port( A : in std_logic := 'U';`
177			`-- B : in std_logic := 'U';`
178			`-- C : in std_logic := 'U';`
179			`-- Y : out std_logic`
180			`-- );`
181			`-- end component;`
182			`--`
183			`-- component DFN1E1`
184			`-- port( D : in std_logic := 'U';`
185			`-- CLK : in std_logic := 'U';`
186			`-- E : in std_logic := 'U';`
187			`-- Q : out std_logic`
188			`-- );`
189			`-- end component;`
190			`--`
191			`-- component INV`
192			`-- port( A : in std_logic := 'U';`
193			`-- Y : out std_logic`
194			`-- );`
195			`-- end component;`
196			`--`
197			`-- component BUFF`
198			`-- port( A : in std_logic := 'U';`
199			`-- Y : out std_logic`
200			`-- );`
201			`-- end component;`
202			`--`
203			`-- component OR2`
204			`-- port( A : in std_logic := 'U';`
205			`-- B : in std_logic := 'U';`
206			`-- Y : out std_logic`
207			`-- );`
208			`-- end component;`
209			`--`
210			`-- component DFN1`
211			`-- port( D : in std_logic := 'U';`
212			`-- CLK : in std_logic := 'U';`
213			`-- Q : out std_logic`
214			`-- );`
215			`-- end component;`
216			`--`
217			`-- signal N_Sload_0, N_Sload_1, N_Q_0, N_Q_1, N_Q_2, N_Q_3,`
218			`-- N_Q_4, N_Q_5, N_Q_6, N_Q_7, N_Q_8, N_INV_Q0_Y, N_LA_0_LA,`
219			`-- N_Q_9, N_Q_10, N_Q_11, N_Q_12, N_Q_13, N_Q_14, AND3_3_Y,`
220			`-- OR2_0_Y, AND3_9_Y, AND2_4_Y, AND2_8_Y, AND2_9_Y,`
221			`-- AND3_11_Y, MX2_6_Y, XOR2_8_Y, MX2_12_Y, XOR2_11_Y,`
222			`-- MX2_10_Y, INV_0_Y, MX2_11_Y, XOR2_0_Y, MX2_8_Y, XOR2_2_Y,`
223			`-- MX2_0_Y, XOR2_6_Y, AND2_2_Y, MX2_9_Y, XOR2_12_Y,`
224			`-- AND2_10_Y, MX2_7_Y, XOR2_5_Y, AND2_6_Y, MX2_1_Y, XOR2_4_Y,`
225			`-- AND2_1_Y, AND3_4_Y, OR2_1_Y, AND3_10_Y, AND2_5_Y,`
226			`-- AND2_0_Y, MX2_2_Y, XOR2_7_Y, MX2_13_Y, INV_1_Y, MX2_15_Y,`
227			`-- XOR2_10_Y, MX2_5_Y, XOR2_1_Y, MX2_14_Y, XOR2_3_Y,`
228			`-- AND2_3_Y, MX2_4_Y, XOR2_9_Y, AND2_7_Y, OR2_2_Y, AND3_5_Y,`
229			`-- MX2_3_Y, AND3_1_Y, AND3_6_Y, AND3_7_Y, AND3_2_Y, AND3_0_Y,`
230			`-- AND3_12_Y, AND3_8_Y : std_logic;`
231			`--`
232			`-- begin`
233			`--`
234			`-- Q(14) <= N_Q_14;`
235			`-- Q(13) <= N_Q_13;`
236			`-- Q(12) <= N_Q_12;`
237			`-- Q(11) <= N_Q_11;`
238			`-- Q(10) <= N_Q_10;`
239			`-- Q(9) <= N_Q_9;`
240			`-- Q(8) <= N_Q_8;`
241			`-- Q(7) <= N_Q_7;`
242			`-- Q(6) <= N_Q_6;`
243			`-- Q(5) <= N_Q_5;`
244			`-- Q(4) <= N_Q_4;`
245			`-- Q(3) <= N_Q_3;`
246			`-- Q(2) <= N_Q_2;`
247			`-- Q(1) <= N_Q_1;`
248			`-- Q(0) <= N_Q_0;`
249			`--`
250			`-- AND2_9 : AND2`
251			`-- port map(A => N_Q_5, B => N_Q_6, Y => AND2_9_Y);`
252			`--`
253			`-- MX2_12 : MX2`
254			`-- port map(A => XOR2_11_Y, B => Data(1), S => N_Sload_0, Y`
255			`-- => MX2_12_Y);`
256			`--`
257			`-- XOR2_9 : XOR2`
258			`-- port map(A => N_Q_14, B => AND2_7_Y, Y => XOR2_9_Y);`
259			`--`
260			`-- AND3_5 : AND3`
261			`-- port map(A => AND3_6_Y, B => AND3_7_Y, C => AND3_2_Y, Y =>`
262			`-- AND3_5_Y);`
263			`--`
264			`-- AND3_10 : AND3`
265			`-- port map(A => N_Q_10, B => N_Q_11, C => N_Q_12, Y =>`
266			`-- AND3_10_Y);`
267			`--`
268			`-- MX2_10 : MX2`
269			`-- port map(A => INV_0_Y, B => Data(2), S => N_Sload_0, Y =>`
270			`-- MX2_10_Y);`
271			`--`
272			`-- DFN1E1_N_Q_2 : DFN1E1`
273			`-- port map(D => MX2_10_Y, CLK => Clock, E => OR2_0_Y, Q =>`
274			`-- N_Q_2);`
275			`--`
276			`-- MX2_7 : MX2`
277			`-- port map(A => XOR2_5_Y, B => Data(7), S => N_Sload_0, Y =>`
278			`-- MX2_7_Y);`
279			`--`
280			`-- MX2_15 : MX2`
281			`-- port map(A => XOR2_10_Y, B => Data(11), S => N_Sload_1, Y`
282			`-- => MX2_15_Y);`
283			`--`
284			`-- DFN1E1_N_Q_6 : DFN1E1`
285			`-- port map(D => MX2_9_Y, CLK => Clock, E => OR2_0_Y, Q =>`
286			`-- N_Q_6);`
287			`--`
288			`-- XOR2_1 : XOR2`
289			`-- port map(A => N_Q_12, B => AND2_0_Y, Y => XOR2_1_Y);`
290			`--`
291			`-- XOR2_10 : XOR2`
292			`-- port map(A => N_Q_11, B => N_Q_10, Y => XOR2_10_Y);`
293			`--`
294			`-- DFN1E1_N_LA_0_LA : DFN1E1`
295			`-- port map(D => MX2_3_Y, CLK => Clock, E => OR2_2_Y, Q =>`
296			`-- N_LA_0_LA);`
297			`--`
298			`-- AND3_2 : AND3`
299			`-- port map(A => Data(6), B => Data(7), C => Data(8), Y =>`
300			`-- AND3_2_Y);`
301			`--`
302			`-- AND2_0 : AND2`
303			`-- port map(A => N_Q_10, B => N_Q_11, Y => AND2_0_Y);`
304			`--`
305			`-- XOR2_7 : XOR2`
306			`-- port map(A => N_Q_9, B => AND2_5_Y, Y => XOR2_7_Y);`
307			`--`
308			`-- MX2_2 : MX2`
309			`-- port map(A => XOR2_7_Y, B => Data(9), S => N_Sload_0, Y =>`
310			`-- MX2_2_Y);`
311			`--`
312			`-- AND3_9 : AND3`
313			`-- port map(A => N_Q_2, B => N_Q_3, C => N_Q_4, Y => AND3_9_Y);`
314			`--`
315			`-- DFN1E1_N_Q_3 : DFN1E1`
316			`-- port map(D => MX2_11_Y, CLK => Clock, E => OR2_0_Y, Q =>`
317			`-- N_Q_3);`
318			`--`
319			`-- INV_1 : INV`
320			`-- port map(A => N_Q_10, Y => INV_1_Y);`
321			`--`
322			`-- U_BUFF_ld_1 : BUFF`
323			`-- port map(A => Sload, Y => N_Sload_1);`
324			`--`
325			`-- AND2_2 : AND2`
326			`-- port map(A => N_Q_4, B => AND2_8_Y, Y => AND2_2_Y);`
327			`--`
328			`-- MX2_1 : MX2`
329			`-- port map(A => XOR2_4_Y, B => Data(8), S => N_Sload_0, Y =>`
330			`-- MX2_1_Y);`
331			`--`
332			`-- AND2_8 : AND2`
333			`-- port map(A => N_Q_2, B => N_Q_3, Y => AND2_8_Y);`
334			`--`
335			`-- AND2_5 : AND2`
336			`-- port map(A => Enable, B => N_LA_0_LA, Y => AND2_5_Y);`
337			`--`
338			`-- AND3_7 : AND3`
339			`-- port map(A => Data(3), B => Data(4), C => Data(5), Y =>`
340			`-- AND3_7_Y);`
341			`--`
342			`-- AND3_6 : AND3`
343			`-- port map(A => Data(0), B => Data(1), C => Data(2), Y =>`
344			`-- AND3_6_Y);`
345			`--`
346			`-- AND2_4 : AND2`
347			`-- port map(A => Enable, B => N_Q_0, Y => AND2_4_Y);`
348			`--`
349			`-- AND2_1 : AND2`
350			`-- port map(A => AND3_11_Y, B => AND3_9_Y, Y => AND2_1_Y);`
351			`--`
352			`-- AND3_11 : AND3`
353			`-- port map(A => N_Q_5, B => N_Q_6, C => N_Q_7, Y => AND3_11_Y);`
354			`--`
355			`-- AND2_3 : AND2`
356			`-- port map(A => N_Q_12, B => AND2_0_Y, Y => AND2_3_Y);`
357			`--`
358			`-- MX2_0 : MX2`
359			`-- port map(A => XOR2_6_Y, B => Data(5), S => N_Sload_0, Y =>`
360			`-- MX2_0_Y);`
361			`--`
362			`-- AND2_7 : AND2`
363			`-- port map(A => N_Q_13, B => AND3_10_Y, Y => AND2_7_Y);`
364			`--`
365			`-- AND3_0 : AND3`
366			`-- port map(A => N_INV_Q0_Y, B => N_Q_1, C => N_Q_2, Y =>`
367			`-- AND3_0_Y);`
368			`--`
369			`-- AND3_12 : AND3`
370			`-- port map(A => N_Q_3, B => N_Q_4, C => N_Q_5, Y => AND3_12_Y);`
371			`--`
372			`-- AND3_8 : AND3`
373			`-- port map(A => N_Q_6, B => N_Q_7, C => N_Q_8, Y => AND3_8_Y);`
374			`--`
375			`-- OR2_0 : OR2`
376			`-- port map(A => N_Sload_0, B => AND3_3_Y, Y => OR2_0_Y);`
377			`--`
378			`-- XOR2_12 : XOR2`
379			`-- port map(A => N_Q_6, B => AND2_10_Y, Y => XOR2_12_Y);`
380			`--`
381			`-- DFN1E1_N_Q_7 : DFN1E1`
382			`-- port map(D => MX2_7_Y, CLK => Clock, E => OR2_0_Y, Q =>`
383			`-- N_Q_7);`
384			`--`
385			`-- U_BUFF_ld_0 : BUFF`
386			`-- port map(A => Sload, Y => N_Sload_0);`
387			`--`
388			`-- XOR2_3 : XOR2`
389			`-- port map(A => N_Q_13, B => AND2_3_Y, Y => XOR2_3_Y);`
390			`--`
391			`-- MX2_5 : MX2`
392			`-- port map(A => XOR2_1_Y, B => Data(12), S => N_Sload_1, Y`
393			`-- => MX2_5_Y);`
394			`--`
395			`-- MX2_14 : MX2`
396			`-- port map(A => XOR2_3_Y, B => Data(13), S => N_Sload_1, Y`
397			`-- => MX2_14_Y);`
398			`--`
399			`-- AND2_6 : AND2`
400			`-- port map(A => AND2_9_Y, B => AND3_9_Y, Y => AND2_6_Y);`
401			`--`
402			`-- MX2_9 : MX2`
403			`-- port map(A => XOR2_12_Y, B => Data(6), S => N_Sload_0, Y`
404			`-- => MX2_9_Y);`
405			`--`
406			`-- DFN1E1_N_Q_12 : DFN1E1`
407			`-- port map(D => MX2_5_Y, CLK => Clock, E => OR2_1_Y, Q =>`
408			`-- N_Q_12);`
409			`--`
410			`-- DFN1_N_Q_9 : DFN1`
411			`-- port map(D => MX2_2_Y, CLK => Clock, Q => N_Q_9);`
412			`--`
413			`-- MX2_4 : MX2`
414			`-- port map(A => XOR2_9_Y, B => Data(14), S => N_Sload_1, Y`
415			`-- => MX2_4_Y);`
416			`--`
417			`-- DFN1E1_N_Q_4 : DFN1E1`
418			`-- port map(D => MX2_8_Y, CLK => Clock, E => OR2_0_Y, Q =>`
419			`-- N_Q_4);`
420			`--`
421			`-- DFN1E1_N_Q_11 : DFN1E1`
422			`-- port map(D => MX2_15_Y, CLK => Clock, E => OR2_1_Y, Q =>`
423			`-- N_Q_11);`
424			`--`
425			`-- XOR2_0 : XOR2`
426			`-- port map(A => N_Q_3, B => N_Q_2, Y => XOR2_0_Y);`
427			`--`
428			`-- AND3_3 : AND3`
429			`-- port map(A => Enable, B => N_Q_0, C => N_Q_1, Y => AND3_3_Y);`
430			`--`
431			`-- DFN1E1_N_Q_5 : DFN1E1`
432			`-- port map(D => MX2_0_Y, CLK => Clock, E => OR2_0_Y, Q =>`
433			`-- N_Q_5);`
434			`--`
435			`-- AND2_10 : AND2`
436			`-- port map(A => N_Q_5, B => AND3_9_Y, Y => AND2_10_Y);`
437			`--`
438			`-- U_INV_Q0 : INV`
439			`-- port map(A => N_Q_0, Y => N_INV_Q0_Y);`
440			`--`
441			`-- AND3_1 : AND3`
442			`-- port map(A => AND3_0_Y, B => AND3_12_Y, C => AND3_8_Y, Y`
443			`-- => AND3_1_Y);`
444			`--`
445			`-- XOR2_5 : XOR2`
446			`-- port map(A => N_Q_7, B => AND2_6_Y, Y => XOR2_5_Y);`
447			`--`
448			`-- DFN1_N_Q_0 : DFN1`
449			`-- port map(D => MX2_6_Y, CLK => Clock, Q => N_Q_0);`
450			`--`
451			`-- OR2_1 : OR2`
452			`-- port map(A => N_Sload_0, B => AND3_4_Y, Y => OR2_1_Y);`
453			`--`
454			`-- XOR2_2 : XOR2`
455			`-- port map(A => N_Q_4, B => AND2_8_Y, Y => XOR2_2_Y);`
456			`--`
457			`-- DFN1_N_Q_1 : DFN1`
458			`-- port map(D => MX2_12_Y, CLK => Clock, Q => N_Q_1);`
459			`--`
460			`-- XOR2_6 : XOR2`
461			`-- port map(A => N_Q_5, B => AND2_2_Y, Y => XOR2_6_Y);`
462			`--`
463			`-- MX2_6 : MX2`
464			`-- port map(A => XOR2_8_Y, B => Data(0), S => N_Sload_0, Y =>`
465			`-- MX2_6_Y);`
466			`--`
467			`-- XOR2_4 : XOR2`
468			`-- port map(A => N_Q_8, B => AND2_1_Y, Y => XOR2_4_Y);`
469			`--`
470			`-- XOR2_8 : XOR2`
471			`-- port map(A => N_Q_0, B => Enable, Y => XOR2_8_Y);`
472			`--`
473			`-- DFN1E1_N_Q_8 : DFN1E1`
474			`-- port map(D => MX2_1_Y, CLK => Clock, E => OR2_0_Y, Q =>`
475			`-- N_Q_8);`
476			`--`
477			`-- MX2_13 : MX2`
478			`-- port map(A => INV_1_Y, B => Data(10), S => N_Sload_0, Y =>`
479			`-- MX2_13_Y);`
480			`--`
481			`-- XOR2_11 : XOR2`
482			`-- port map(A => N_Q_1, B => AND2_4_Y, Y => XOR2_11_Y);`
483			`--`
484			`-- INV_0 : INV`
485			`-- port map(A => N_Q_2, Y => INV_0_Y);`
486			`--`
487			`-- DFN1E1_N_Q_13 : DFN1E1`
488			`-- port map(D => MX2_14_Y, CLK => Clock, E => OR2_1_Y, Q =>`
489			`-- N_Q_13);`
490			`--`
491			`-- DFN1E1_N_Q_10 : DFN1E1`
492			`-- port map(D => MX2_13_Y, CLK => Clock, E => OR2_1_Y, Q =>`
493			`-- N_Q_10);`
494			`--`
495			`-- DFN1E1_N_Q_14 : DFN1E1`
496			`-- port map(D => MX2_4_Y, CLK => Clock, E => OR2_1_Y, Q =>`
497			`-- N_Q_14);`
498			`--`
499			`-- AND3_4 : AND3`
500			`-- port map(A => Enable, B => N_LA_0_LA, C => N_Q_9, Y =>`
501			`-- AND3_4_Y);`
502			`--`
503			`-- MX2_3 : MX2`
504			`-- port map(A => AND3_1_Y, B => AND3_5_Y, S => N_Sload_0, Y`
505			`-- => MX2_3_Y);`
506			`--`
507			`-- MX2_8 : MX2`
508			`-- port map(A => XOR2_2_Y, B => Data(4), S => N_Sload_0, Y =>`
509			`-- MX2_8_Y);`
510			`--`
511			`-- OR2_2 : OR2`
512			`-- port map(A => N_Sload_0, B => Enable, Y => OR2_2_Y);`
513			`--`
514			`-- MX2_11 : MX2`
515			`-- port map(A => XOR2_0_Y, B => Data(3), S => N_Sload_0, Y =>`
516			`-- MX2_11_Y);`
517			`--`
518			`--`
519			`-- end DEF_ARCH;`
520			`--`
521			`-- --================================================================================================--`
522			`-- -- Report for cell channel_selector.arch01`
523			`-- -- Core Cell usage:`
524			`-- -- cell count area count*area`
525			`-- AND2 1 1.0 1.0`
526			`-- AO1 3 1.0 3.0`
527			`-- AOI1 3 1.0 3.0`
528			`-- AOI1B 1 1.0 1.0`
529			`-- AX1 1 1.0 1.0`
530			`-- AX1A 1 1.0 1.0`
531			`-- AX1C 2 1.0 2.0`
532			`-- AX1D 1 1.0 1.0`
533			`-- AX1E 2 1.0 2.0`
534			`-- GND 1 0.0 0.0`
535			`-- MX2 48 1.0 48.0`
536			`-- MX2B 1 1.0 1.0`
537			`-- MX2C 17 1.0 17.0`
538			`-- NOR2 7 1.0 7.0`
539			`-- NOR2A 9 1.0 9.0`
540			`-- NOR2B 7 1.0 7.0`
541			`-- NOR3 2 1.0 2.0`
542			`-- NOR3A 4 1.0 4.0`
543			`-- NOR3B 1 1.0 1.0`
544			`-- NOR3C 5 1.0 5.0`
545			`-- OA1A 1 1.0 1.0`
546			`-- OA1C 2 1.0 2.0`
547			`-- OAI1 1 1.0 1.0`
548			`-- OR2 6 1.0 6.0`
549			`-- OR2A 4 1.0 4.0`
550			`-- OR2B 8 1.0 8.0`
551			`-- OR3 1 1.0 1.0`
552			`-- OR3B 3 1.0 3.0`
553			`-- OR3C 5 1.0 5.0`
554			`-- VCC 1 0.0 0.0`
555			`-- XOR2 4 1.0 4.0`
556			`--`
557			`--`
558			`-- DFN1 4 1.0 4.0`
559			`-- ----- ----------`
560			`-- TOTAL 157 155.0`
561			`--`
562			`--`
563			`-- IO Cell usage:`
564			`-- cell count`
565			`-- CLKBUF 1`
566			`-- INBUF 18`
567			`-- OUTBUF 4`
568			`-- -----`
569			`-- TOTAL 23`
570			`--`
571			`--`
572			`-- Core Cells : 155 of 38400 (0%)`
573			`-- IO Cells : 23`
574
575			`--================================================================================================--`
576			`--`
577			`-- Requested Estimated Requested Estimated Clock Clock`
578			`-- Starting Clock Frequency Frequency Period Period Slack Type Group`
579			`-- ------------------------------------------------------------------------------------------------------------------------------`
580			`-- channel_selector\|clk_I 100.0 MHz 68.9 MHz 10.000 14.521 -4.521 inferred Inferred_clkgroup_0`
581			`--`
582			`--`
583			`--================================================================================================--`