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--| Modular Oscilloscope

--| UNSL - Argentine

--|

--| File: memory_writer.vhd

--| Version: 0.1

--| Tested in: Actel A3PE1500

--|-------------------------------------------------------------------------------------------------

--| Description:

--|   CONTROL - Memory writer

--|   Read data and write it in a memory (it's a simple wishbone bridge)

--|   

--|-------------------------------------------------------------------------------------------------

--| File history:

--|   0.1   | jul-2009 | First release

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--| Copyright ® 2009, Facundo Aguilera.

--|

--| This VHDL design file is an open design; you can redistribute it and/or

--| modify it and/or implement it after contacting the author.

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--==================================================================================================

-- TODO

-- · ...

--==================================================================================================

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

----------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------

entity memory_writer is

  generic(

    MEM_ADD_WIDTH: integer :=  14

  );

  port(

    ------------------------------------------------------------------------------------------------

    -- to memory

    DAT_O_mem: out std_logic_vector (15 downto 0);

    ADR_O_mem: out std_logic_vector (MEM_ADD_WIDTH - 1  downto 0);

    CYC_O_mem: out std_logic;

    STB_O_mem: out std_logic;

    ACK_I_mem: in std_logic ;

    WE_O_mem:  out std_logic;

    ------------------------------------------------------------------------------------------------

    -- to acquistion module

    DAT_I_adc: in std_logic_vector (15 downto 0);

    -- Using an address generator, commented

    -- ADR_O_adc: out std_logic_vector (ADC_ADD_WIDTH - 1  downto 0); 

    CYC_O_adc: out std_logic;

    STB_O_adc: out std_logic;

    ACK_I_adc: in std_logic ;

    WE_O_adc:  out std_logic;

    ------------------------------------------------------------------------------------------------

    -- Common signals 

    RST_I: in std_logic;

    CLK_I: in std_logic;

    ------------------------------------------------------------------------------------------------

    -- Internal

    -- reset counter(memory address) to 0

    reset_I:            in std_logic;

    -- read in clk edge from the actual address ('0' means pause, '1' means continue)

    enable_I:           in std_logic;

    -- buffer starts and ends here 

    -- when the buffer arrives here, address is changed to 0  (buffer size)

    final_address_I:    in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);

    -- address wich is being writed by control

    -- stop_address:     in std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);

    -- it is set when communication ends and remains until next restart or actual address change

    finished_O:         out std_logic;

    -- When counter finishes, restart

    continuous_I:       in  std_logic;

  );

end entity memory_writer;

----------------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------------

architecture ARCH11 of output_manager is

  type DataStatusType is (

          INIT,

          WORKING

          );

  signal data_status: DataStatusType; -- comunicates status between both ports

  signal count: std_logic_vector(MEM_ADD_WIDTH-1  downto 0);

  signal enable_count:std_logic;

  signal reset_count: std_logic;

  signal data: std_logic_vector(15 downto 0);

  signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1  downto 0);

  signal s_finished, s_STB_adc, s_STB_mem: std_logic; -- previous to outputs

begin

  --------------------------------------------------------------------------------------------------

  -- Instantiations

  U_COUNTER0: generic_counter

  generic map(

    OUTPUT_WIDTH => MEM_ADD_WIDTH -- Output width for counter.

  )

  port map(

    clk_I => CLK_I,

    count_O => count,

    reset_I => reset_count,

    enable_I => enable_count

  );

  --------------------------------------------------------------------------------------------------

  -- Combinational

  -- counter

  s_finished <= '1' when count >= final_address_I;

  enable_count <= '1' when enable_I = '1' and

                           data_status = WORKING  and

                           s_STB_mem = '1' and

                           ACK_I_mem = '1' and

                           s_finished = '0'

                      else

                  '0';

  reset_count <= '1' when reset_I = '1' or (s_finished = '1' and continuous_I = '1') else

                 '0';

  -- outputs

  finished_O <= s_finished;

  STB_O_adc <= s_STB_adc;

  STB_O_mem <= s_STB_mem;

  DAT_O_mem <= data;

  ADR_O_mem <= count;

  --------------------------------------------------------------------------------------------------

  -- Clocked

  -- Lock interface when working

  P_cyc_signals: process (clk_I, enable_count, ACK_I_adc, ACK_I_mem)

  begin

    if CLK_I'event and CLK_I = '1' then

      if enable_I /= '1' or reset_I = '1' then

        CYC_O_adc <= '0';   CYC_O_mem <= '0';

      else

        CYC_O_adc <= '1';  CYC_O_mem <= '1';

      end if;

    end if;

  end process;

  P_stb_signals: process (CLK_I, reset_I, data_status, s_STB_adc, s_STB_mem, ACK_I_adc, ACK_I_mem)

  begin

    if CLK_I'event and CLK_I = '1' then

      if reset_I = '1' then

        data_status <= INIT;

        s_STB_adc <= '0';

        s_STB_mem <= '0';

        data <= (others => '0');

      elsif enable_I = '1' then

        if data_status = INIT and s_STB_adc = '0' or s_STB_mem = '0' then

          -- this state is only necessary when there are adc convertions in every clock

          -- (for the first convertion)

          s_STB_adc <= '1';

          s_STB_mem <= '1';

        else

          data_status <= WORKING;

          if s_STB_adc = '1' and ACK_I_adc = '1' then

            s_STB_mem <= '1'; -- strobe when adc ack

            data <= DAT_I_adc; -- save data

          elsif s_STB_mem = '1' and ACK_I_mem = '1' then

            s_STB_mem <= '0';

          end if;

          if s_STB_mem = '1' and ACK_I_mem = '1' then

            s_STB_adc <= '1'; -- strobe when mem ack

          elsif s_STB_adc = '1' and ACK_I_adc = '1' then

            s_STB_adc <= '0';

          end if;

        end if;

      else

        s_STB_adc <= '0';

        s_STB_mem <= '0';

      end if;

    end if;

  end process;

end architecture;