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budinero |
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--|
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--| File: data_skipper_tbench_text.vhd
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--| Version: 0.01
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| Adquisition control module.
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--| This file is only for test purposes. Testing daq. Test bench.
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--| It may not work for other than Actel Libero software.
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| 0.01 | apr-2009 | First release
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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-- NOTE: It may not work for other than Actel Libero software.
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-- You can download Libero for free from Actel website (it is not a free software).
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library ieee, std;
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use ieee.std_logic_1164.all;
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library syncad_vhdl_lib;
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use syncad_vhdl_lib.TBDefinitions.all;
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use IEEE.NUMERIC_STD.ALL;
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-- Additional libraries used by Model Under Test.
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use work.ctrl_pkg.all;
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use ieee.math_real.all;
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----------------------------------------------------------------------------------------------------
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entity stimulus is
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generic(
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SELECTOR_WIDTH: integer := 5 -- max looses = 2**(2**SELECTOR_WIDTH)
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);
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port(
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-- sinal from wishbone interface
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ack_I, stb_I: inout std_logic;
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-- selector from register
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selector_I: inout std_logic_vector(SELECTOR_WIDTH-1 downto 0);
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-- enable from register
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enable_skipper_I: inout std_logic;
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-- common signals
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reset_I, clk_I: inout std_logic
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);
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end stimulus;
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architecture STIMULATOR of stimulus is
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-- Period
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constant T: real := 10.0;
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-- Control Signal Declarations
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signal tb_status : TStatus;
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signal tb_ParameterInitFlag : boolean := false;
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-- Parm Declarations
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signal clk_MinHL : time := 0 ns;
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signal clk_MaxHL : time := 0 ns;
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signal clk_MinLH : time := 0 ns;
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signal clk_MaxLH : time := 0 ns;
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signal clk_JFall : time := 0 ns;
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signal clk_JRise : time := 0 ns;
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signal clk_Duty : real := 0.0;
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signal clk_Period : time := 0 ns;
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signal clk_Offset : time := 0 ns;
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begin
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--------------------------------------------------------------------------------------------------
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-- Status Control block.
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process
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-- variable good : boolean;
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begin
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wait until tb_ParameterInitFlag;
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tb_status <= TB_ONCE;
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wait for 50000 ns;
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tb_status <= TB_DONE; -- End of simulation
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wait;
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end process;
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--------------------------------------------------------------------------------------------------
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-- Parm Assignment Block
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AssignParms : process
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variable clk_MinHL_real : real;
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variable clk_MaxHL_real : real;
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variable clk_MinLH_real : real;
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variable clk_MaxLH_real : real;
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variable clk_JFall_real : real;
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variable clk_JRise_real : real;
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variable clk_Duty_real : real;
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variable clk_Period_real : real;
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variable clk_Offset_real : real;
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begin
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-- Basic parameters
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clk_Period_real := T; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
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clk_Period <= clk_Period_real * 1 ns;
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clk_Duty_real := 50.0;
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clk_Duty <= clk_Duty_real;
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-- Aditionale parameters
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clk_MinHL_real := 0.0;
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clk_MinHL <= clk_MinHL_real * 1 ns;
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clk_MaxHL_real := 0.0;
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clk_MaxHL <= clk_MaxHL_real * 1 ns;
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clk_MinLH_real := 0.0;
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clk_MinLH <= clk_MinLH_real * 1 ns;
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clk_MaxLH_real := 0.0;
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clk_MaxLH <= clk_MaxLH_real * 1 ns;
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clk_JFall_real := 0.0;
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clk_JFall <= clk_JFall_real * 1 ns;
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clk_JRise_real := 0.0;
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clk_JRise <= clk_JRise_real * 1 ns;
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clk_Offset_real := 0.0;
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clk_Offset <= clk_Offset_real * 1 ns;
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tb_ParameterInitFlag <= true;
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wait;
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end process;
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--------------------------------------------------------------------------------------------------
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-- Clocks
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-- Clock Instantiation
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tb_clk : entity syncad_vhdl_lib.tb_clock_minmax
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generic map (name => "tb_clk",
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initialize => true,
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state1 => '1',
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state2 => '0')
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port map (tb_status,
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clk_I, --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
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clk_MinLH,
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clk_MaxLH,
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clk_MinHL,
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clk_MaxHL,
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clk_Offset,
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clk_Period,
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clk_Duty,
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clk_JRise,
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clk_JFall);
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--<=============================================================================================
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-- Clocked Sequences
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-- ...
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--===============================================================================================>
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--<===============================================================================================
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-- Sequence: Unclocked
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Unclocked : process
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variable i: natural range 0 to 500;
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begin
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-- Initial
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reset_I <= '1' ;
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enable_skipper_I <= '0';
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ack_I <= '0'; stb_I <= '0';
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selector_I <= (others => '0');
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wait for 15 ns; --<delay>
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-- w/o en_skip
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reset_I <= '0';
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wait for T * 1 ns; --<delay>
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ack_I <= '1';
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wait for T * 1 ns; --<delay>
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ack_I <= '0'; stb_I <= '1';
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wait for T * 1 ns; --<delay>
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ack_I <= '1'; stb_I <= '1';
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wait for (3.0*T) * 1 ns; --<delay>
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-- w/ en_skip
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enable_skipper_I <= '1';
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wait for 10.0*T * 1 ns; --<delay>
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ack_I <= '1'; stb_I <= '0';
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wait for 4.0 * T * 1 ns; --<delay>
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ack_I <= '0'; stb_I <= '1';
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wait for 4.0*T * 1 ns; --<delay>
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-- selector_I /= 0
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ack_I <= '1'; stb_I <= '1'; selector_I <= std_logic_vector(unsigned(selector_I) + 1);
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wait for 20.0*T * 1 ns; --<delay>
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selector_I <= std_logic_vector(to_unsigned( integer(2**real(selector_I'length )/10.0), selector_I'length ));
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wait for 1000.0*T * 1 ns; --<delay>
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selector_I <= std_logic_vector(to_unsigned( integer(2**real(selector_I'length )/4.0), selector_I'length ));
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wait for 2000.0*T * 1 ns; --<delay>
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selector_I <= std_logic_vector(to_unsigned( integer(2**real(selector_I'length )-1.0), selector_I'length ));
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wait for 100000.0*T * 1 ns; --<delay>
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wait;
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end process;
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--===============================================================================================>
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end STIMULATOR;
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----------------------------------------------------------------------------------------------------
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-- Test Bench wrapper for stimulus and Model Under Test
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library ieee, std;
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use ieee.std_logic_1164.all;
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library syncad_vhdl_lib;
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use syncad_vhdl_lib.TBDefinitions.all;
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-- Additional libraries used by Model Under Test.
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-- ...
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----------------------------------------------------------------------------------------------------
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entity testbench is
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end testbench;
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architecture tbGeneratedCode of testbench is
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constant SELECTOR_WIDTH: integer := 5;
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-- enable output signal
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signal ack_O: std_logic;
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-- sinal from wishbone interface
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signal ack_I, stb_I: std_logic;
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-- selector from register
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signal selector_I: std_logic_vector(SELECTOR_WIDTH-1 downto 0);
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-- enable from register
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signal enable_skipper_I: std_logic;
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-- common signals
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signal reset_I, clk_I: std_logic;
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begin
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--------------------------------------------------------------------------------------------------
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-- Instantiation of Stimulus.
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U_stimulus_0 : entity work.stimulus --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
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generic map(
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SELECTOR_WIDTH => SELECTOR_WIDTH
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)
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port map (
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ack_I => ack_I,
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stb_I => stb_I,
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selector_I => selector_I,
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enable_skipper_I => enable_skipper_I,
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reset_I => reset_I,
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clk_I => clk_I
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);
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--------------------------------------------------------------------------------------------------
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-- Instantiation of Model Under Test.
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U_skip_0 : entity work.data_skipper --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
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generic map(
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SELECTOR_WIDTH => 5
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)
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port map (
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ack_O => ack_O,
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ack_I => ack_I,
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stb_I => stb_I,
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selector_I => selector_I,
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enable_skipper_I => enable_skipper_I,
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reset_I => reset_I,
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clk_I => clk_I
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);
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end tbGeneratedCode;
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----------------------------------------------------------------------------------------------------
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