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[/] [modular_oscilloscope/] [trunk/] [hdl/] [ctrl/] [trigger_manager.vhd] - Blame information for rev 48

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Line No. Rev Author Line
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-------------------------------------------------------------------------------------------------100
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--|
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--| File: ctrl_trigger_manager.vhd
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--| Version: 0.1
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--|   CONTROL - Trigger manager
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--|   
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--|   
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--|   0.1   | jul-2009 | First release
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----------------------------------------------------------------------------------------------------
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--| Copyright © 2009, Facundo Aguilera.
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--|
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--| This VHDL design file is an open design; you can redistribute it and/or
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--| modify it and/or implement it after contacting the author.
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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-- TODO
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-- · (OK) Test offset sum
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-- · Speed up
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-- · Compare performance with address_O = actual trigger address - 1
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--==================================================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity ctrl_trigger_manager is
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  generic (
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    MEM_ADD_WIDTH:  integer := 14;
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    DATA_WIDTH:     integer := 10;
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    CHANNELS_WIDTH: integer := 4
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  );
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  port (
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    data_I:           in  std_logic_vector (DATA_WIDTH - 1 downto 0);
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    channel_I:        in  std_logic_vector (CHANNELS_WIDTH -1 downto 0);
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    trig_channel_I:   in  std_logic_vector (CHANNELS_WIDTH -1 downto 0);
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    address_I:        in  std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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    final_address_I:  in  std_logic_vector (MEM_ADD_WIDTH - 1 downto 0);
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    -- offset from trigger address (signed). MUST BE: -final_address_I < offset_I < final_address_I
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    offset_I:         in std_logic_vector (MEM_ADD_WIDTH  downto 0);
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    -- trigger level (from max to min, not signed)
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    level_I:          in  std_logic_vector (DATA_WIDTH - 1 downto 0);
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    -- use falling edge when falling_I = '1', else rising edge
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    falling_I:        in  std_logic;
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    clk_I:            in  std_logic;
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    reset_I:          in  std_logic;
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    enable_I:         in  std_logic;
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    -- it is set when trigger condition occurs
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    trigger_O:        out std_logic;
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    -- address when trigger plus offset
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    address_O:        out std_logic_vector (MEM_ADD_WIDTH - 1 downto 0)
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  );
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end entity ctrl_trigger_manager;
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architecture arch01_trigger of ctrl_trigger_manager is
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  -- trigger process signals
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  signal higher, higher_reg: std_logic;
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  signal pre_trigger: std_logic;
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  -- signals for output address selection
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  --signal final_address_sign: std_logic_vector (MEM_ADD_WIDTH downto 0);
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  signal add_plus_off: unsigned (MEM_ADD_WIDTH downto 0);
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  signal add_plus_off_plus_fa: unsigned (MEM_ADD_WIDTH downto 0);
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  signal add_plus_off_sign: std_logic;
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  signal add_plus_off_plus_fa_sign: std_logic;
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  signal offset_sign: std_logic;
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  signal truncate: std_logic;
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  signal selected_address: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
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  signal selected_address_reg: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
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begin
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  --------------------------------------------------------------------------------------------------
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  -- Output address selection
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  -- Output addess must be between 0 and final_address_I (buffer size), wich may be less than 
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  -- (others -> '1'). For this reaeson, it must be truncated. 
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  add_plus_off <= unsigned(address_I) + unsigned(offset_I);
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  add_plus_off_sign <= add_plus_off(MEM_ADD_WIDTH);
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  offset_sign <= offset_I(MEM_ADD_WIDTH);
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  add_plus_off_plus_fa <= add_plus_off - unsigned(final_address_I) when offset_sign = '0' else
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                           add_plus_off + unsigned(final_address_I);
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  add_plus_off_plus_fa_sign <= add_plus_off_plus_fa (MEM_ADD_WIDTH);
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  truncate <= (offset_sign and  add_plus_off_sign) or
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              (not(offset_sign) and not(add_plus_off_plus_fa_sign));
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  with truncate select
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    selected_address <= std_logic_vector(add_plus_off_plus_fa(MEM_ADD_WIDTH - 1 downto 0))
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                          when '1',
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                        std_logic_vector(add_plus_off(MEM_ADD_WIDTH - 1 downto 0))
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                          when others;
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  address_O <=  selected_address_reg;
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  --------------------------------------------------------------------------------------------------
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  -- Trigger 
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  higher <= '1' when data_I >= level_I else '0';
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  P_trigger: process (clk_I, reset_I, enable_I, channel_I, trig_channel_I, higher_reg,
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  falling_I, higher, address_I, offset_sign, selected_address)
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  begin
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    if clk_I'event and clk_I = '1' then
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      if reset_I = '1' then
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        pre_trigger <= '0';
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        higher_reg <= '0';
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        trigger_O <= '0';
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        selected_address_reg <= (others => '0');
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      elsif enable_I = '1' then
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        if channel_I = trig_channel_I then
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          if  (higher_reg = '0' xor falling_I = '1') and
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              (higher = '1' xor falling_I = '1') and pre_trigger = '0'
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              then -- trigger!
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            pre_trigger <= '1';
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            selected_address_reg <= selected_address;
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            if offset_sign = '1' or unsigned(offset_I) = 0 then
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              trigger_O <= '1';
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            end if;
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          end if;
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          higher_reg <= higher;
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        end if;
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        if pre_trigger = '1' and selected_address_reg = address_I then
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          -- if offset > 0 then trigger will wait until address_I equals trigger address plus offset
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            trigger_O <= '1';
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        end if;
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      end if;
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    end if;
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  end process;
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  -- t pt f /f xor1 xor2 and
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  -- 000 1 0 1 
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  -- 001 0 1 0 
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  -- 010 1 0 0     
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  -- 011 0 1 1 1 
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  -- 100 1 1 1 1 
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  -- 101 0 0 0  
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  -- 110 1 1 0  
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  -- 111 0 0 1  
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end architecture;

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