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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 5 budinero
-- Bloque completo
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architecture eppwbn is
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-- generic (
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      -- data_size : <type> {:= <default_value>};
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      -- <generic2_name> : <type> {:= <default_value>};
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      -- <other generics>...    
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-- );
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port(
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        -- Externo
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        nStrobe: in std_logic;                                          -- Nomenclatura IEEE Std. 1284 ECP/EPP (Compatibiliy)
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                                                                                                -- HostClk/nWrite 
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        Data: inout std_logic_vector (7 downto 0);       --AD8..1 (Data1..Data8)
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        nAck: out std_logic;                                            --  PtrClk/PeriphClk/Intr
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        busy: out std_logic;                                            --  PtrBusy/PeriphAck/nWait
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        PError: out std_logic;                                          --  AckData/nAckReverse
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        Sel: out std_logic;                                             --  XFlag (Select)
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        nAutoFd: in std_logic;                                          --  HostBusy/HostAck/nDStrb
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        PeriphLogicH: out std_logic;                            --  (Periph Logic High)
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        nInit: in std_logic;                                            --  nReverseRequest
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        nFault: out std_logic;                                          --  nDataAvail/nPeriphRequest
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        nSelectIn: in std_logic;                                        --  1284 Active/nAStrb
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        HostLogicH: in std_logic;                                       --  (Host Logic High)
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        --  Interno
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        RST_I: in std_logic;
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        CLK_I: in std_logic;
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        DAT_I: in std_logic_vector (15 downto 0);
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        ADR_I: in std_logic_vector (15 downto 0);
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        DAT_O: out std_logic_vector (15 downto 0);
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        ADR_O: out std_logic_vector (15 downto 0);
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        CYC_I: in std_logic;
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        ACK_O: out std_logic;
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        WE_I: in std_logic;
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        );
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end eppwbn;
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