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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 19

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----------------------------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Tested in: Actel APA300
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   EPP - Wishbone bridge. 
--|       Package for instantiate all EPP-WBN modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.01  | dic-2008 | First release
--|   0.10  | jan-2009 | Added testing memory
--|   0.20  | mar-2009 | Added extension module
--|   0.30  | apr-2009 | Added pll
----------------------------------------------------------------------------------------------------
--| Copyright � 2008, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
-- El m�dulo PLL solo funcionar� con FPGAs de Actel 
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package eppwbn_pgk is
        --------------------------------------------------------------------------------------------------
        -- Componentes  
 
  -- Bridge control
  component eppwbn_ctrl is
    port(
      nStrobe:      in  std_logic;
 
      Data:         in  std_logic_vector (7 downto 0);
      nAck:         out std_logic;
      PError:       out std_logic;
      Sel:          out std_logic;
      nAutoFd:      in  std_logic;
      PeriphLogicH: out std_logic;
      nInit:        in  std_logic;
      nFault:       out std_logic;
      nSelectIn:    in  std_logic;
 
      RST_I:        in  std_logic;
      CLK_I:        in  std_logic;
 
      rst_pp:       out std_logic;
      epp_mode:     out std_logic_vector (1 downto 0)
          );
        end component eppwbn_ctrl;
 
  -- Comunication with EPP interface
  component eppwbn_epp_side is
                port(
                        epp_mode: in std_logic_vector (1 downto 0);
 
                        ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault:   in std_logic;
 
                        ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe:    out std_logic;
 
                        wb_Busy:       in   std_logic;
                        wb_nAutoFd:    out  std_logic;
                        wb_nSelectIn:  out  std_logic;
                        wb_nStrobe:    out  std_logic;
 
                        nAck, PError, Sel, nFault:   out std_logic;
 
                        Busy:         out   std_logic;
                        nAutoFd:      in    std_logic;
                        nSelectIn:    in    std_logic;
                        nStrobe:      in    std_logic
                );
        end component eppwbn_epp_side;
 
        -- Comunication with WB interface
  component eppwbn_wbn_side is
                port(
                        inStrobe:     in    std_logic;
                        iData:        inout std_logic_vector (7 downto 0);
                        iBusy:        out   std_logic;
                        inAutoFd:     in    std_logic;
                        inSelectIn:   in    std_logic;
 
                        RST_I, CLK_I: in    std_logic;
                        DAT_I:        in    std_logic_vector (7 downto 0);
                        DAT_O:        out   std_logic_vector (7 downto 0);
                        ADR_O:        out   std_logic_vector (7 downto 0);
                        CYC_O, STB_O: out   std_logic;
                        ACK_I:        in    std_logic ;
                        WE_O:         out   std_logic;
 
                        rst_pp:       in std_logic
                );
        end component eppwbn_wbn_side;
 
        -- Testing memory
  component test_memory is
    generic ( --USE_RESET   : boolean   := false;  -- use system reset
 
              --USE_CS      : boolean   := false;  -- use chip select signal
 
              DEFAULT_OUT : std_logic;  -- Default output
              --OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
                                          -- for Altera's FPGAs
                                          -- 0: non registered read address
              ADD_WIDTH   : integer;
              WIDTH       : integer);
 
    port (
      cs:        in  std_logic;           -- chip select
      clk:       in  std_logic;           -- write clock
      reset:     in  std_logic;           -- System Reset
      add:       in  std_logic_vector(add_width -1 downto 0);   --  Address
      Data_In:   in  std_logic_vector(WIDTH -1 downto 0);       -- input data
      Data_Out:  out std_logic_vector(WIDTH -1 downto 0);       -- Output Data
      WR:        in  std_logic);          -- Read Write Enable
  end component test_memory;
 
  -- Epp-wishbone bridge
  component eppwbn is
    port(
      -- Externo
      nStrobe:      in    std_logic;                                                            -- HostClk/nWrite       
      Data:         inout std_logic_vector (7 downto 0);         -- AD8..1 (Data1..Data8)
      nAck:         out   std_logic;                                                                                    -- PtrClk/PeriphClk/Intr
      busy:         out   std_logic;                                                                                    -- PtrBusy/PeriphAck/nWait
      PError:       out   std_logic;                                                                                    -- AckData/nAckReverse
      Sel:          out   std_logic;                                                                                    -- XFlag (Select)
      nAutoFd:      in    std_logic;                                                                                    -- HostBusy/HostAck/nDStrb
      PeriphLogicH: out   std_logic;                                                                  -- (Periph Logic High)
      nInit:        in    std_logic;                                                                                    -- nReverseRequest
      nFault:       out   std_logic;                                                                                    -- nDataAvail/nPeriphRequest
      nSelectIn:    in    std_logic;                                                                              -- 1284 Active/nAStrb
 
      --  Interno
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_O:  out std_logic_vector (7 downto 0);
      CYC_O:  out std_logic;
      STB_O:  out std_logic;
      ACK_I:  in  std_logic ;
      WE_O:   out std_logic
      );
  end component eppwbn;
 
  -- Testing component
  component eppwbn_test_wb_side is
    port(
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_I:  in  std_logic_vector (7 downto 0);
      CYC_I:  in  std_logic;
      STB_I:  in  std_logic;
      ACK_O:  out std_logic ;
      WE_I:   in  std_logic
    );
  end component eppwbn_test_wb_side;
 
 
  -- Width extension
  component eppwbn_width_extension is
  generic (
    TIME_OUT_VALUE: integer;
    TIME_OUT_WIDTH: integer
  );
  port(
    -- Slave signals
    DAT_I_sl: in  std_logic_vector (7 downto 0);
    DAT_O_sl: out std_logic_vector (7 downto 0);
    ADR_I_sl: in  std_logic_vector (7 downto 0);
    CYC_I_sl: in  std_logic;
    STB_I_sl: in  std_logic;
    ACK_O_sl: out std_logic ;
    WE_I_sl:  in  std_logic;
 
 
    --  Master signals
    DAT_I_ma: in  std_logic_vector (15 downto 0);
    DAT_O_ma: out std_logic_vector (15 downto 0);
    ADR_O_ma: out std_logic_vector (7 downto 0);
    CYC_O_ma: out std_logic;
    STB_O_ma: out std_logic;
    ACK_I_ma: in  std_logic ;
    WE_O_ma:  out std_logic;
 
    -- Common signals
    RST_I: in std_logic;
    CLK_I: in std_logic
  );
  end component eppwbn_width_extension;
 
  component eppwbn_16bit is
  port(
        -- Externo
    nStrobe:      in std_logic;                       --  HostClk/nWrite 
        Data:         inout std_logic_vector (7 downto 0);--   AD8..1 (Data1..Data8)
        nAck:         out std_logic;                      --  PtrClk/PeriphClk/Intr
        busy:         out std_logic;                      --  PtrBusy/PeriphAck/nWait
        PError:       out std_logic;                      --  AckData/nAckReverse
        Sel:          out std_logic;                      --  XFlag (Select)
        nAutoFd:      in std_logic;                       --  HostBusy/HostAck/nDStrb
        PeriphLogicH: out std_logic;                      --  (Periph Logic High)
    nInit:        in std_logic;                       --  nReverseRequest
        nFault:       out std_logic;                      --  nDataAvail/nPeriphRequest
        nSelectIn:    in std_logic;                       --  1284 Active/nAStrb
 
 
        --  Interno
        RST_I: in std_logic;
        CLK_I: in std_logic;
        DAT_I: in std_logic_vector (15 downto 0);
        DAT_O: out std_logic_vector (15 downto 0);
        ADR_O: out std_logic_vector (7 downto 0);
        CYC_O: out std_logic;
        STB_O: out std_logic;
        ACK_I: in std_logic ;
        WE_O: out std_logic
        );
  end component eppwbn_16bit;
 
  component eppwbn_16bit_test is
  port(
    -- al puerto EPP
    nStrobe:    in std_logic;                                                                                   -- Nomenclatura IEEE Std. 1284 
                                                -- HostClk/nWrite 
    Data:       inout std_logic_vector (7 downto 0);     -- AD8..1 (Data1..Data8)
    nAck:       out std_logic;                                                                                          --  PtrClk/PeriphClk/Intr
    busy:       out std_logic;                                                                                          --  PtrBusy/PeriphAck/nWait
    PError:     out std_logic;                                                                          --  AckData/nAckReverse
    Sel:        out std_logic;                                                                          --  XFlag (Select)
    nAutoFd:    in std_logic;                                                                           --  HostBusy/HostAck/nDStrb
    PeriphLogicH: out std_logic;                                                                --  (Periph Logic High)
    nInit:      in std_logic;                                                                           --  nReverseRequest
    nFault:     out std_logic;                                                                          --  nDataAvail/nPeriphRequest
    nSelectIn:  in std_logic;                                                                           --  1284 Active/nAStrb
 
    -- a los switches
    rst:        in std_logic;
 
    -- al clock
    clk:        in std_logic
 
        );
  end component eppwbn_16bit_test;
 
  component eppwbn_16bit_test_wb_side is
  generic (
    ADD_WIDTH   : integer ;
    WIDTH       : integer
    );
  port(
    RST_I:  in std_logic;
    CLK_I:  in std_logic;
    DAT_I:  in std_logic_vector (WIDTH-1 downto 0);
    DAT_O:  out std_logic_vector (WIDTH-1 downto 0);
    ADR_I:  in std_logic_vector (7 downto 0);
    CYC_I:  in std_logic;
    STB_I:  in std_logic;
    ACK_O:  out std_logic ;
    WE_I:   in std_logic
        );
  end component eppwbn_16bit_test_wb_side;
 
  -- Clock (Actel specific)
  component pll is
    port(GLB, LOCK : out std_logic;  CLK : in std_logic) ;
  end component pll;
 
 
end package eppwbn_pgk;
 

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Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 19

Line No.	Rev	Author	Line
1	19	budinero	`----------------------------------------------------------------------------------------------------`
2			`--\| UNSL - Modular Oscilloscope`
3			`--\|`
4			`--\| File: eppwbn_wbn_side.vhd`
5			`--\| Version: 0.2`
6			`--\| Tested in: Actel APA300`
7			`--\|-------------------------------------------------------------------------------------------------`
8			`--\| Description:`
9			`--\| EPP - Wishbone bridge.`
10			`--\| Package for instantiate all EPP-WBN modules.`
11			`--\|-------------------------------------------------------------------------------------------------`
12			`--\| File history:`
13			`--\| 0.01 \| dic-2008 \| First release`
14			`--\| 0.10 \| jan-2009 \| Added testing memory`
15			`--\| 0.20 \| mar-2009 \| Added extension module`
16			`--\| 0.30 \| apr-2009 \| Added pll`
17			`----------------------------------------------------------------------------------------------------`
18			`--\| Copyright � 2008, Facundo Aguilera.`
19			`--\|`
20			`--\| This VHDL design file is an open design; you can redistribute it and/or`
21			`--\| modify it and/or implement it after contacting the author.`
22			`----------------------------------------------------------------------------------------------------`
23
24			`-- El m�dulo PLL solo funcionar� con FPGAs de Actel`
25
26
27			`-- Bloque completo`
28			`library IEEE;`
29			`use IEEE.STD_LOGIC_1164.ALL;`
30
31			`package eppwbn_pgk is`
32			`--------------------------------------------------------------------------------------------------`
33			`-- Componentes`
34
35			`-- Bridge control`
36			`component eppwbn_ctrl is`
37			`port(`
38			`nStrobe: in std_logic;`
39
40			`Data: in std_logic_vector (7 downto 0);`
41			`nAck: out std_logic;`
42			`PError: out std_logic;`
43			`Sel: out std_logic;`
44			`nAutoFd: in std_logic;`
45			`PeriphLogicH: out std_logic;`
46			`nInit: in std_logic;`
47			`nFault: out std_logic;`
48			`nSelectIn: in std_logic;`
49
50			`RST_I: in std_logic;`
51			`CLK_I: in std_logic;`
52
53			`rst_pp: out std_logic;`
54			`epp_mode: out std_logic_vector (1 downto 0)`
55			`);`
56			`end component eppwbn_ctrl;`
57
58			`-- Comunication with EPP interface`
59			`component eppwbn_epp_side is`
60			`port(`
61			`epp_mode: in std_logic_vector (1 downto 0);`
62
63			`ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;`
64
65			`ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;`
66
67			`wb_Busy: in std_logic;`
68			`wb_nAutoFd: out std_logic;`
69			`wb_nSelectIn: out std_logic;`
70			`wb_nStrobe: out std_logic;`
71
72			`nAck, PError, Sel, nFault: out std_logic;`
73
74			`Busy: out std_logic;`
75			`nAutoFd: in std_logic;`
76			`nSelectIn: in std_logic;`
77			`nStrobe: in std_logic`
78			`);`
79			`end component eppwbn_epp_side;`
80
81			`-- Comunication with WB interface`
82			`component eppwbn_wbn_side is`
83			`port(`
84			`inStrobe: in std_logic;`
85			`iData: inout std_logic_vector (7 downto 0);`
86			`iBusy: out std_logic;`
87			`inAutoFd: in std_logic;`
88			`inSelectIn: in std_logic;`
89
90			`RST_I, CLK_I: in std_logic;`
91			`DAT_I: in std_logic_vector (7 downto 0);`
92			`DAT_O: out std_logic_vector (7 downto 0);`
93			`ADR_O: out std_logic_vector (7 downto 0);`
94			`CYC_O, STB_O: out std_logic;`
95			`ACK_I: in std_logic ;`
96			`WE_O: out std_logic;`
97
98			`rst_pp: in std_logic`
99			`);`
100			`end component eppwbn_wbn_side;`
101
102			`-- Testing memory`
103			`component test_memory is`
104			`generic ( --USE_RESET : boolean := false; -- use system reset`
105
106			`--USE_CS : boolean := false; -- use chip select signal`
107
108			`DEFAULT_OUT : std_logic; -- Default output`
109			`--OPTION : integer := 1; -- 1: Registered read Address(suitable`
110			`-- for Altera's FPGAs`
111			`-- 0: non registered read address`
112			`ADD_WIDTH : integer;`
113			`WIDTH : integer);`
114
115			`port (`
116			`cs: in std_logic; -- chip select`
117			`clk: in std_logic; -- write clock`
118			`reset: in std_logic; -- System Reset`
119			`add: in std_logic_vector(add_width -1 downto 0); -- Address`
120			`Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data`
121			`Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data`
122			`WR: in std_logic); -- Read Write Enable`
123			`end component test_memory;`
124
125			`-- Epp-wishbone bridge`
126			`component eppwbn is`
127			`port(`
128			`-- Externo`
129			`nStrobe: in std_logic; -- HostClk/nWrite`
130			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
131			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
132			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
133			`PError: out std_logic; -- AckData/nAckReverse`
134			`Sel: out std_logic; -- XFlag (Select)`
135			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
136			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
137			`nInit: in std_logic; -- nReverseRequest`
138			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
139			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
140
141			`-- Interno`
142			`RST_I: in std_logic;`
143			`CLK_I: in std_logic;`
144			`DAT_I: in std_logic_vector (7 downto 0);`
145			`DAT_O: out std_logic_vector (7 downto 0);`
146			`ADR_O: out std_logic_vector (7 downto 0);`
147			`CYC_O: out std_logic;`
148			`STB_O: out std_logic;`
149			`ACK_I: in std_logic ;`
150			`WE_O: out std_logic`
151			`);`
152			`end component eppwbn;`
153
154			`-- Testing component`
155			`component eppwbn_test_wb_side is`
156			`port(`
157			`RST_I: in std_logic;`
158			`CLK_I: in std_logic;`
159			`DAT_I: in std_logic_vector (7 downto 0);`
160			`DAT_O: out std_logic_vector (7 downto 0);`
161			`ADR_I: in std_logic_vector (7 downto 0);`
162			`CYC_I: in std_logic;`
163			`STB_I: in std_logic;`
164			`ACK_O: out std_logic ;`
165			`WE_I: in std_logic`
166			`);`
167			`end component eppwbn_test_wb_side;`
168
169
170			`-- Width extension`
171			`component eppwbn_width_extension is`
172			`generic (`
173			`TIME_OUT_VALUE: integer;`
174			`TIME_OUT_WIDTH: integer`
175			`);`
176			`port(`
177			`-- Slave signals`
178			`DAT_I_sl: in std_logic_vector (7 downto 0);`
179			`DAT_O_sl: out std_logic_vector (7 downto 0);`
180			`ADR_I_sl: in std_logic_vector (7 downto 0);`
181			`CYC_I_sl: in std_logic;`
182			`STB_I_sl: in std_logic;`
183			`ACK_O_sl: out std_logic ;`
184			`WE_I_sl: in std_logic;`
185
186
187			`-- Master signals`
188			`DAT_I_ma: in std_logic_vector (15 downto 0);`
189			`DAT_O_ma: out std_logic_vector (15 downto 0);`
190			`ADR_O_ma: out std_logic_vector (7 downto 0);`
191			`CYC_O_ma: out std_logic;`
192			`STB_O_ma: out std_logic;`
193			`ACK_I_ma: in std_logic ;`
194			`WE_O_ma: out std_logic;`
195
196			`-- Common signals`
197			`RST_I: in std_logic;`
198			`CLK_I: in std_logic`
199			`);`
200			`end component eppwbn_width_extension;`
201
202			`component eppwbn_16bit is`
203			`port(`
204			`-- Externo`
205			`nStrobe: in std_logic; -- HostClk/nWrite`
206			`Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)`
207			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
208			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
209			`PError: out std_logic; -- AckData/nAckReverse`
210			`Sel: out std_logic; -- XFlag (Select)`
211			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
212			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
213			`nInit: in std_logic; -- nReverseRequest`
214			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
215			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
216
217
218			`-- Interno`
219			`RST_I: in std_logic;`
220			`CLK_I: in std_logic;`
221			`DAT_I: in std_logic_vector (15 downto 0);`
222			`DAT_O: out std_logic_vector (15 downto 0);`
223			`ADR_O: out std_logic_vector (7 downto 0);`
224			`CYC_O: out std_logic;`
225			`STB_O: out std_logic;`
226			`ACK_I: in std_logic ;`
227			`WE_O: out std_logic`
228			`);`
229			`end component eppwbn_16bit;`
230
231			`component eppwbn_16bit_test is`
232			`port(`
233			`-- al puerto EPP`
234			`nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284`
235			`-- HostClk/nWrite`
236			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
237			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
238			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
239			`PError: out std_logic; -- AckData/nAckReverse`
240			`Sel: out std_logic; -- XFlag (Select)`
241			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
242			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
243			`nInit: in std_logic; -- nReverseRequest`
244			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
245			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
246
247			`-- a los switches`
248			`rst: in std_logic;`
249
250			`-- al clock`
251			`clk: in std_logic`
252
253			`);`
254			`end component eppwbn_16bit_test;`
255
256			`component eppwbn_16bit_test_wb_side is`
257			`generic (`
258			`ADD_WIDTH : integer ;`
259			`WIDTH : integer`
260			`);`
261			`port(`
262			`RST_I: in std_logic;`
263			`CLK_I: in std_logic;`
264			`DAT_I: in std_logic_vector (WIDTH-1 downto 0);`
265			`DAT_O: out std_logic_vector (WIDTH-1 downto 0);`
266			`ADR_I: in std_logic_vector (7 downto 0);`
267			`CYC_I: in std_logic;`
268			`STB_I: in std_logic;`
269			`ACK_O: out std_logic ;`
270			`WE_I: in std_logic`
271			`);`
272			`end component eppwbn_16bit_test_wb_side;`
273
274			`-- Clock (Actel specific)`
275			`component pll is`
276			`port(GLB, LOCK : out std_logic; CLK : in std_logic) ;`
277			`end component pll;`
278
279
280			`end package eppwbn_pgk;`
281