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----------------------------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Tested in: Actel APA300
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   EPP - Wishbone bridge. 
--|       Package for instantiate all EPP-WBN modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.01  | dic-2008 | First release
--|   0.10  | jan-2009 | Added testing memory
--|   0.20  | mar-2009 | Added extension module
----------------------------------------------------------------------------------------------------
--| Copyright � 2008, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
package eppwbn_pkg is
        --------------------------------------------------------------------------------------------------
        -- Componentes  
 
  -- Bridge control
  component eppwbn_ctrl is
    port(
      nStrobe:      in  std_logic;
 
      Data:         in  std_logic_vector (7 downto 0);
      nAck:         out std_logic;
      PError:       out std_logic;
      Sel:          out std_logic;
      nAutoFd:      in  std_logic;
      PeriphLogicH: out std_logic;
      nInit:        in  std_logic;
      nFault:       out std_logic;
      nSelectIn:    in  std_logic;
 
      RST_I:        in  std_logic;
      CLK_I:        in  std_logic;
 
      rst_pp:       out std_logic;
      epp_mode:     out std_logic_vector (1 downto 0)
          );
        end component eppwbn_ctrl;
 
  -- Comunication with EPP interface
  component eppwbn_epp_side is
                port(
                        epp_mode: in std_logic_vector (1 downto 0);
 
                        ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault:   in std_logic;
 
                        ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe:    out std_logic;
 
                        wb_Busy:       in   std_logic;
                        wb_nAutoFd:    out  std_logic;
                        wb_nSelectIn:  out  std_logic;
                        wb_nStrobe:    out  std_logic;
 
                        nAck, PError, Sel, nFault:   out std_logic;
 
                        Busy:         out   std_logic;
                        nAutoFd:      in    std_logic;
                        nSelectIn:    in    std_logic;
                        nStrobe:      in    std_logic
                );
        end component eppwbn_epp_side;
 
        -- Comunication with WB interface
  component eppwbn_wbn_side is
                port(
                        inStrobe:     in    std_logic;
                        iData:        inout std_logic_vector (7 downto 0);
                        iBusy:        out   std_logic;
                        inAutoFd:     in    std_logic;
                        inSelectIn:   in    std_logic;
 
                        RST_I, CLK_I: in    std_logic;
                        DAT_I:        in    std_logic_vector (7 downto 0);
                        DAT_O:        out   std_logic_vector (7 downto 0);
                        ADR_O:        out   std_logic_vector (7 downto 0);
                        CYC_O, STB_O: out   std_logic;
                        ACK_I:        in    std_logic ;
                        WE_O:         out   std_logic;
 
                        rst_pp:       in std_logic
                );
        end component eppwbn_wbn_side;
 
        -- Testing memory
  component test_memory is
    generic ( --USE_RESET   : boolean   := false;  -- use system reset
 
              --USE_CS      : boolean   := false;  -- use chip select signal
 
              DEFAULT_OUT : std_logic;  -- Default output
              --OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
                                          -- for Altera's FPGAs
                                          -- 0: non registered read address
              ADD_WIDTH   : integer;
              WIDTH       : integer);
 
    port (
      cs:        in  std_logic;           -- chip select
      clk:       in  std_logic;           -- write clock
      reset:     in  std_logic;           -- System Reset
      add:       in  std_logic_vector(add_width -1 downto 0);   --  Address
      Data_In:   in  std_logic_vector(WIDTH -1 downto 0);       -- input data
      Data_Out:  out std_logic_vector(WIDTH -1 downto 0);       -- Output Data
      WR:        in  std_logic);          -- Read Write Enable
  end component test_memory;
 
  -- Epp-wishbone bridge
  component eppwbn is
    port(
      -- TEMPORAL
      epp_mode_monitor: out std_logic_vector (1 downto 0);
 
      -- Externo
      nStrobe:      in    std_logic;                                                            -- HostClk/nWrite       
      Data:         inout std_logic_vector (7 downto 0);         -- AD8..1 (Data1..Data8)
      nAck:         out   std_logic;                                                                                    -- PtrClk/PeriphClk/Intr
      busy:         out   std_logic;                                                                                    -- PtrBusy/PeriphAck/nWait
      PError:       out   std_logic;                                                                                    -- AckData/nAckReverse
      Sel:          out   std_logic;                                                                                    -- XFlag (Select)
      nAutoFd:      in    std_logic;                                                                                    -- HostBusy/HostAck/nDStrb
      PeriphLogicH: out   std_logic;                                                                  -- (Periph Logic High)
      nInit:        in    std_logic;                                                                                    -- nReverseRequest
      nFault:       out   std_logic;                                                                                    -- nDataAvail/nPeriphRequest
      nSelectIn:    in    std_logic;                                                                              -- 1284 Active/nAStrb
 
      --  Interno
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_O:  out std_logic_vector (7 downto 0);
      CYC_O:  out std_logic;
      STB_O:  out std_logic;
      ACK_I:  in  std_logic ;
      WE_O:   out std_logic
      );
  end component eppwbn;
 
  -- Testing component
  component eppwbn_test_wb_side is
    port(
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_I:  in  std_logic_vector (7 downto 0);
      CYC_I:  in  std_logic;
      STB_I:  in  std_logic;
      ACK_O:  out std_logic ;
      WE_I:   in  std_logic
    );
  end component eppwbn_test_wb_side;
 
 
  -- Width extension
  component eppwbn_width_extension is
  generic (
    TIME_OUT_VALUE: integer;
    TIME_OUT_WIDTH: integer
  );
  port(
    -- Slave signals
    DAT_I_sl: in  std_logic_vector (7 downto 0);
    DAT_O_sl: out std_logic_vector (7 downto 0);
    ADR_I_sl: in  std_logic_vector (7 downto 0);
    CYC_I_sl: in  std_logic;
    STB_I_sl: in  std_logic;
    ACK_O_sl: out std_logic ;
    WE_I_sl:  in  std_logic;
 
 
    --  Master signals
    DAT_I_ma: in  std_logic_vector (15 downto 0);
    DAT_O_ma: out std_logic_vector (15 downto 0);
    ADR_O_ma: out std_logic_vector (7 downto 0);
    CYC_O_ma: out std_logic;
    STB_O_ma: out std_logic;
    ACK_I_ma: in  std_logic ;
    WE_O_ma:  out std_logic;
 
    -- Common signals
    RST_I: in std_logic;
    CLK_I: in std_logic
  );
  end component eppwbn_width_extension;
 
  component eppwbn_16bit is
  port(
    -- TEMPORAL
    epp_mode_monitor: out std_logic_vector (1 downto 0);
 
        -- Externo
    nStrobe:      in std_logic;                       --  HostClk/nWrite 
        Data:         inout std_logic_vector (7 downto 0);--   AD8..1 (Data1..Data8)
        nAck:         out std_logic;                      --  PtrClk/PeriphClk/Intr
        busy:         out std_logic;                      --  PtrBusy/PeriphAck/nWait
        PError:       out std_logic;                      --  AckData/nAckReverse
        Sel:          out std_logic;                      --  XFlag (Select)
        nAutoFd:      in std_logic;                       --  HostBusy/HostAck/nDStrb
        PeriphLogicH: out std_logic;                      --  (Periph Logic High)
    nInit:        in std_logic;                       --  nReverseRequest
        nFault:       out std_logic;                      --  nDataAvail/nPeriphRequest
        nSelectIn:    in std_logic;                       --  1284 Active/nAStrb
 
 
        --  Interno
        RST_I: in std_logic;
        CLK_I: in std_logic;
        DAT_I: in std_logic_vector (15 downto 0);
        DAT_O: out std_logic_vector (15 downto 0);
        ADR_O: out std_logic_vector (7 downto 0);
        CYC_O: out std_logic;
        STB_O: out std_logic;
        ACK_I: in std_logic ;
        WE_O: out std_logic
        );
  end component eppwbn_16bit;
 
  component eppwbn_16bit_test is
  port(
    -- al puerto EPP
    nStrobe:    in std_logic;                                                                                   -- Nomenclatura IEEE Std. 1284 
                                                -- HostClk/nWrite 
    Data:       inout std_logic_vector (7 downto 0);     -- AD8..1 (Data1..Data8)
    nAck:       out std_logic;                                                                                          --  PtrClk/PeriphClk/Intr
    busy:       out std_logic;                                                                                          --  PtrBusy/PeriphAck/nWait
    PError:     out std_logic;                                                                          --  AckData/nAckReverse
    Sel:        out std_logic;                                                                          --  XFlag (Select)
    nAutoFd:    in std_logic;                                                                           --  HostBusy/HostAck/nDStrb
    PeriphLogicH: out std_logic;                                                                --  (Periph Logic High)
    nInit:      in std_logic;                                                                           --  nReverseRequest
    nFault:     out std_logic;                                                                          --  nDataAvail/nPeriphRequest
    nSelectIn:  in std_logic;                                                                           --  1284 Active/nAStrb
 
    -- a los switches
    rst:        in std_logic;
 
    -- al clock
    clk:        in std_logic;
 
    -- monitores
    data_monitor:     out std_logic_vector (7 downto 0);
    epp_mode_monitor: out std_logic_vector (1 downto 0)
 
        );
  end component eppwbn_16bit_test;
 
  component eppwbn_16bit_test_wb_side is
  generic (
    ADD_WIDTH   : integer ;
    WIDTH       : integer
    );
  port(
    RST_I:  in std_logic;
    CLK_I:  in std_logic;
    DAT_I:  in std_logic_vector (WIDTH-1 downto 0);
    DAT_O:  out std_logic_vector (WIDTH-1 downto 0);
    ADR_I:  in std_logic_vector (7 downto 0);
    CYC_I:  in std_logic;
    STB_I:  in std_logic;
    ACK_O:  out std_logic ;
    WE_I:   in std_logic
        );
  end component eppwbn_16bit_test_wb_side;
 
  -- Clock (Actel specific)
  component A3PE_pll is
      port(POWERDOWN, CLKA : in std_logic;  LOCK, GLA : out
          std_logic) ;
  end component A3PE_pll;
 
  component dual_port_memory_wb is
  port(
    -- Puerto A (Higer prioriry)
    RST_I_a: in std_logic;
    CLK_I_a: in std_logic;
    DAT_I_a: in std_logic_vector (15 downto 0);
    DAT_O_a: out std_logic_vector (15 downto 0);
    ADR_I_a: in std_logic_vector (13 downto 0);
    CYC_I_a: in std_logic;
    STB_I_a: in std_logic;
    ACK_O_a: out std_logic ;
    WE_I_a: in std_logic;
 
 
    -- Puerto B (Lower prioriry)
    RST_I_b: in std_logic;
    CLK_I_b: in std_logic;
    DAT_I_b: in std_logic_vector (15 downto 0);
    DAT_O_b: out std_logic_vector (15 downto 0);
    ADR_I_b: in std_logic_vector (13 downto 0);
    CYC_I_b: in std_logic;
    STB_I_b: in std_logic;
    ACK_O_b: out std_logic ;
    WE_I_b: in std_logic
  );
  end component dual_port_memory_wb;
 
 
end package eppwbn_pkg;
 

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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 22

Line No.	Rev	Author	Line
1	22	budinero	`----------------------------------------------------------------------------------------------------`
2			`--\| UNSL - Modular Oscilloscope`
3			`--\|`
4			`--\| File: eppwbn_wbn_side.vhd`
5			`--\| Version: 0.2`
6			`--\| Tested in: Actel APA300`
7			`--\|-------------------------------------------------------------------------------------------------`
8			`--\| Description:`
9			`--\| EPP - Wishbone bridge.`
10			`--\| Package for instantiate all EPP-WBN modules.`
11			`--\|-------------------------------------------------------------------------------------------------`
12			`--\| File history:`
13			`--\| 0.01 \| dic-2008 \| First release`
14			`--\| 0.10 \| jan-2009 \| Added testing memory`
15			`--\| 0.20 \| mar-2009 \| Added extension module`
16			`----------------------------------------------------------------------------------------------------`
17			`--\| Copyright � 2008, Facundo Aguilera.`
18			`--\|`
19			`--\| This VHDL design file is an open design; you can redistribute it and/or`
20			`--\| modify it and/or implement it after contacting the author.`
21			`----------------------------------------------------------------------------------------------------`
22
23
24			`-- Bloque completo`
25			`library IEEE;`
26			`use IEEE.STD_LOGIC_1164.ALL;`
27
28			`package eppwbn_pkg is`
29			`--------------------------------------------------------------------------------------------------`
30			`-- Componentes`
31
32			`-- Bridge control`
33			`component eppwbn_ctrl is`
34			`port(`
35			`nStrobe: in std_logic;`
36
37			`Data: in std_logic_vector (7 downto 0);`
38			`nAck: out std_logic;`
39			`PError: out std_logic;`
40			`Sel: out std_logic;`
41			`nAutoFd: in std_logic;`
42			`PeriphLogicH: out std_logic;`
43			`nInit: in std_logic;`
44			`nFault: out std_logic;`
45			`nSelectIn: in std_logic;`
46
47			`RST_I: in std_logic;`
48			`CLK_I: in std_logic;`
49
50			`rst_pp: out std_logic;`
51			`epp_mode: out std_logic_vector (1 downto 0)`
52			`);`
53			`end component eppwbn_ctrl;`
54
55			`-- Comunication with EPP interface`
56			`component eppwbn_epp_side is`
57			`port(`
58			`epp_mode: in std_logic_vector (1 downto 0);`
59
60			`ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;`
61
62			`ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;`
63
64			`wb_Busy: in std_logic;`
65			`wb_nAutoFd: out std_logic;`
66			`wb_nSelectIn: out std_logic;`
67			`wb_nStrobe: out std_logic;`
68
69			`nAck, PError, Sel, nFault: out std_logic;`
70
71			`Busy: out std_logic;`
72			`nAutoFd: in std_logic;`
73			`nSelectIn: in std_logic;`
74			`nStrobe: in std_logic`
75			`);`
76			`end component eppwbn_epp_side;`
77
78			`-- Comunication with WB interface`
79			`component eppwbn_wbn_side is`
80			`port(`
81			`inStrobe: in std_logic;`
82			`iData: inout std_logic_vector (7 downto 0);`
83			`iBusy: out std_logic;`
84			`inAutoFd: in std_logic;`
85			`inSelectIn: in std_logic;`
86
87			`RST_I, CLK_I: in std_logic;`
88			`DAT_I: in std_logic_vector (7 downto 0);`
89			`DAT_O: out std_logic_vector (7 downto 0);`
90			`ADR_O: out std_logic_vector (7 downto 0);`
91			`CYC_O, STB_O: out std_logic;`
92			`ACK_I: in std_logic ;`
93			`WE_O: out std_logic;`
94
95			`rst_pp: in std_logic`
96			`);`
97			`end component eppwbn_wbn_side;`
98
99			`-- Testing memory`
100			`component test_memory is`
101			`generic ( --USE_RESET : boolean := false; -- use system reset`
102
103			`--USE_CS : boolean := false; -- use chip select signal`
104
105			`DEFAULT_OUT : std_logic; -- Default output`
106			`--OPTION : integer := 1; -- 1: Registered read Address(suitable`
107			`-- for Altera's FPGAs`
108			`-- 0: non registered read address`
109			`ADD_WIDTH : integer;`
110			`WIDTH : integer);`
111
112			`port (`
113			`cs: in std_logic; -- chip select`
114			`clk: in std_logic; -- write clock`
115			`reset: in std_logic; -- System Reset`
116			`add: in std_logic_vector(add_width -1 downto 0); -- Address`
117			`Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data`
118			`Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data`
119			`WR: in std_logic); -- Read Write Enable`
120			`end component test_memory;`
121
122			`-- Epp-wishbone bridge`
123			`component eppwbn is`
124			`port(`
125			`-- TEMPORAL`
126			`epp_mode_monitor: out std_logic_vector (1 downto 0);`
127
128			`-- Externo`
129			`nStrobe: in std_logic; -- HostClk/nWrite`
130			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
131			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
132			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
133			`PError: out std_logic; -- AckData/nAckReverse`
134			`Sel: out std_logic; -- XFlag (Select)`
135			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
136			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
137			`nInit: in std_logic; -- nReverseRequest`
138			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
139			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
140
141			`-- Interno`
142			`RST_I: in std_logic;`
143			`CLK_I: in std_logic;`
144			`DAT_I: in std_logic_vector (7 downto 0);`
145			`DAT_O: out std_logic_vector (7 downto 0);`
146			`ADR_O: out std_logic_vector (7 downto 0);`
147			`CYC_O: out std_logic;`
148			`STB_O: out std_logic;`
149			`ACK_I: in std_logic ;`
150			`WE_O: out std_logic`
151			`);`
152			`end component eppwbn;`
153
154			`-- Testing component`
155			`component eppwbn_test_wb_side is`
156			`port(`
157			`RST_I: in std_logic;`
158			`CLK_I: in std_logic;`
159			`DAT_I: in std_logic_vector (7 downto 0);`
160			`DAT_O: out std_logic_vector (7 downto 0);`
161			`ADR_I: in std_logic_vector (7 downto 0);`
162			`CYC_I: in std_logic;`
163			`STB_I: in std_logic;`
164			`ACK_O: out std_logic ;`
165			`WE_I: in std_logic`
166			`);`
167			`end component eppwbn_test_wb_side;`
168
169
170			`-- Width extension`
171			`component eppwbn_width_extension is`
172			`generic (`
173			`TIME_OUT_VALUE: integer;`
174			`TIME_OUT_WIDTH: integer`
175			`);`
176			`port(`
177			`-- Slave signals`
178			`DAT_I_sl: in std_logic_vector (7 downto 0);`
179			`DAT_O_sl: out std_logic_vector (7 downto 0);`
180			`ADR_I_sl: in std_logic_vector (7 downto 0);`
181			`CYC_I_sl: in std_logic;`
182			`STB_I_sl: in std_logic;`
183			`ACK_O_sl: out std_logic ;`
184			`WE_I_sl: in std_logic;`
185
186
187			`-- Master signals`
188			`DAT_I_ma: in std_logic_vector (15 downto 0);`
189			`DAT_O_ma: out std_logic_vector (15 downto 0);`
190			`ADR_O_ma: out std_logic_vector (7 downto 0);`
191			`CYC_O_ma: out std_logic;`
192			`STB_O_ma: out std_logic;`
193			`ACK_I_ma: in std_logic ;`
194			`WE_O_ma: out std_logic;`
195
196			`-- Common signals`
197			`RST_I: in std_logic;`
198			`CLK_I: in std_logic`
199			`);`
200			`end component eppwbn_width_extension;`
201
202			`component eppwbn_16bit is`
203			`port(`
204			`-- TEMPORAL`
205			`epp_mode_monitor: out std_logic_vector (1 downto 0);`
206
207			`-- Externo`
208			`nStrobe: in std_logic; -- HostClk/nWrite`
209			`Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)`
210			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
211			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
212			`PError: out std_logic; -- AckData/nAckReverse`
213			`Sel: out std_logic; -- XFlag (Select)`
214			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
215			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
216			`nInit: in std_logic; -- nReverseRequest`
217			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
218			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
219
220
221			`-- Interno`
222			`RST_I: in std_logic;`
223			`CLK_I: in std_logic;`
224			`DAT_I: in std_logic_vector (15 downto 0);`
225			`DAT_O: out std_logic_vector (15 downto 0);`
226			`ADR_O: out std_logic_vector (7 downto 0);`
227			`CYC_O: out std_logic;`
228			`STB_O: out std_logic;`
229			`ACK_I: in std_logic ;`
230			`WE_O: out std_logic`
231			`);`
232			`end component eppwbn_16bit;`
233
234			`component eppwbn_16bit_test is`
235			`port(`
236			`-- al puerto EPP`
237			`nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284`
238			`-- HostClk/nWrite`
239			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
240			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
241			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
242			`PError: out std_logic; -- AckData/nAckReverse`
243			`Sel: out std_logic; -- XFlag (Select)`
244			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
245			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
246			`nInit: in std_logic; -- nReverseRequest`
247			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
248			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
249
250			`-- a los switches`
251			`rst: in std_logic;`
252
253			`-- al clock`
254			`clk: in std_logic;`
255
256			`-- monitores`
257			`data_monitor: out std_logic_vector (7 downto 0);`
258			`epp_mode_monitor: out std_logic_vector (1 downto 0)`
259
260			`);`
261			`end component eppwbn_16bit_test;`
262
263			`component eppwbn_16bit_test_wb_side is`
264			`generic (`
265			`ADD_WIDTH : integer ;`
266			`WIDTH : integer`
267			`);`
268			`port(`
269			`RST_I: in std_logic;`
270			`CLK_I: in std_logic;`
271			`DAT_I: in std_logic_vector (WIDTH-1 downto 0);`
272			`DAT_O: out std_logic_vector (WIDTH-1 downto 0);`
273			`ADR_I: in std_logic_vector (7 downto 0);`
274			`CYC_I: in std_logic;`
275			`STB_I: in std_logic;`
276			`ACK_O: out std_logic ;`
277			`WE_I: in std_logic`
278			`);`
279			`end component eppwbn_16bit_test_wb_side;`
280
281			`-- Clock (Actel specific)`
282			`component A3PE_pll is`
283			`port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out`
284			`std_logic) ;`
285			`end component A3PE_pll;`
286
287			`component dual_port_memory_wb is`
288			`port(`
289			`-- Puerto A (Higer prioriry)`
290			`RST_I_a: in std_logic;`
291			`CLK_I_a: in std_logic;`
292			`DAT_I_a: in std_logic_vector (15 downto 0);`
293			`DAT_O_a: out std_logic_vector (15 downto 0);`
294			`ADR_I_a: in std_logic_vector (13 downto 0);`
295			`CYC_I_a: in std_logic;`
296			`STB_I_a: in std_logic;`
297			`ACK_O_a: out std_logic ;`
298			`WE_I_a: in std_logic;`
299
300
301			`-- Puerto B (Lower prioriry)`
302			`RST_I_b: in std_logic;`
303			`CLK_I_b: in std_logic;`
304			`DAT_I_b: in std_logic_vector (15 downto 0);`
305			`DAT_O_b: out std_logic_vector (15 downto 0);`
306			`ADR_I_b: in std_logic_vector (13 downto 0);`
307			`CYC_I_b: in std_logic;`
308			`STB_I_b: in std_logic;`
309			`ACK_O_b: out std_logic ;`
310			`WE_I_b: in std_logic`
311			`);`
312			`end component dual_port_memory_wb;`
313
314
315			`end package eppwbn_pkg;`
316	19	budinero