URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 37

Go to most recent revision | Details | Compare with Previous | View Log


----------------------------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Tested in: Actel APA300
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   EPP - Wishbone bridge. 
--|       Package for instantiate EPP-WBN modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.01  | dic-2008 | First release
--|   0.10  | jan-2009 | Added testing memory
--|   0.20  | mar-2009 | Added extension module
----------------------------------------------------------------------------------------------------
--| Copyright � 2008, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
package eppwbn_pkg is
        --------------------------------------------------------------------------------------------------
        -- Componentes  
 
  -- Bridge control
  component eppwbn_ctrl is
    port(
      nStrobe:      in  std_logic;
 
      Data:         in  std_logic_vector (7 downto 0);
      nAck:         out std_logic;
      PError:       out std_logic;
      Sel:          out std_logic;
      nAutoFd:      in  std_logic;
      PeriphLogicH: out std_logic;
      nInit:        in  std_logic;
      nFault:       out std_logic;
      nSelectIn:    in  std_logic;
 
      RST_I:        in  std_logic;
      CLK_I:        in  std_logic;
 
      rst_pp:       out std_logic;
      epp_mode:     out std_logic_vector (1 downto 0)
          );
        end component eppwbn_ctrl;
 
  -- Comunication with EPP interface
  component eppwbn_epp_side is
                port(
                        epp_mode: in std_logic_vector (1 downto 0);
 
                        ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault:   in std_logic;
 
                        ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe:    out std_logic;
 
                        wb_Busy:       in   std_logic;
                        wb_nAutoFd:    out  std_logic;
                        wb_nSelectIn:  out  std_logic;
                        wb_nStrobe:    out  std_logic;
 
                        nAck, PError, Sel, nFault:   out std_logic;
 
                        Busy:         out   std_logic;
                        nAutoFd:      in    std_logic;
                        nSelectIn:    in    std_logic;
                        nStrobe:      in    std_logic
                );
        end component eppwbn_epp_side;
 
        -- Comunication with WB interface
  component eppwbn_wbn_side is
                port(
                        inStrobe:     in    std_logic;
                        iData:        inout std_logic_vector (7 downto 0);
                        iBusy:        out   std_logic;
                        inAutoFd:     in    std_logic;
                        inSelectIn:   in    std_logic;
 
                        RST_I, CLK_I: in    std_logic;
                        DAT_I:        in    std_logic_vector (7 downto 0);
                        DAT_O:        out   std_logic_vector (7 downto 0);
                        ADR_O:        out   std_logic_vector (7 downto 0);
                        CYC_O, STB_O: out   std_logic;
                        ACK_I:        in    std_logic ;
                        WE_O:         out   std_logic;
 
                        rst_pp:       in std_logic
                );
        end component eppwbn_wbn_side;
 
        -- Testing memory
  component test_memory is
    generic ( --USE_RESET   : boolean   := false;  -- use system reset
 
              --USE_CS      : boolean   := false;  -- use chip select signal
 
              DEFAULT_OUT : std_logic;  -- Default output
              --OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
                                          -- for Altera's FPGAs
                                          -- 0: non registered read address
              ADD_WIDTH   : integer;
              WIDTH       : integer);
 
    port (
      cs:        in  std_logic;           -- chip select
      clk:       in  std_logic;           -- write clock
      reset:     in  std_logic;           -- System Reset
      add:       in  std_logic_vector(add_width -1 downto 0);   --  Address
      Data_In:   in  std_logic_vector(WIDTH -1 downto 0);       -- input data
      Data_Out:  out std_logic_vector(WIDTH -1 downto 0);       -- Output Data
      WR:        in  std_logic);          -- Read Write Enable
  end component test_memory;
 
  -- Epp-wishbone bridge
  component eppwbn is
    port(
      -- TEMPORAL
      epp_mode_monitor: out std_logic_vector (1 downto 0);
 
      -- Externo
      nStrobe:      in    std_logic;                                                            -- HostClk/nWrite       
      Data:         inout std_logic_vector (7 downto 0);         -- AD8..1 (Data1..Data8)
      nAck:         out   std_logic;                                                                                    -- PtrClk/PeriphClk/Intr
      busy:         out   std_logic;                                                                                    -- PtrBusy/PeriphAck/nWait
      PError:       out   std_logic;                                                                                    -- AckData/nAckReverse
      Sel:          out   std_logic;                                                                                    -- XFlag (Select)
      nAutoFd:      in    std_logic;                                                                                    -- HostBusy/HostAck/nDStrb
      PeriphLogicH: out   std_logic;                                                                  -- (Periph Logic High)
      nInit:        in    std_logic;                                                                                    -- nReverseRequest
      nFault:       out   std_logic;                                                                                    -- nDataAvail/nPeriphRequest
      nSelectIn:    in    std_logic;                                                                              -- 1284 Active/nAStrb
 
      --  Interno
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_O:  out std_logic_vector (7 downto 0);
      CYC_O:  out std_logic;
      STB_O:  out std_logic;
      ACK_I:  in  std_logic ;
      WE_O:   out std_logic
      );
  end component eppwbn;
 
  -- Testing component
  component eppwbn_test_wb_side is
    port(
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_I:  in  std_logic_vector (7 downto 0);
      CYC_I:  in  std_logic;
      STB_I:  in  std_logic;
      ACK_O:  out std_logic ;
      WE_I:   in  std_logic
    );
  end component eppwbn_test_wb_side;
 
 
  -- Width extension
  component eppwbn_width_extension is
  generic (
    TIME_OUT_VALUE: integer;
    TIME_OUT_WIDTH: integer
  );
  port(
    -- Slave signals
    DAT_I_sl: in  std_logic_vector (7 downto 0);
    DAT_O_sl: out std_logic_vector (7 downto 0);
    ADR_I_sl: in  std_logic_vector (7 downto 0);
    CYC_I_sl: in  std_logic;
    STB_I_sl: in  std_logic;
    ACK_O_sl: out std_logic ;
    WE_I_sl:  in  std_logic;
 
 
    --  Master signals
    DAT_I_ma: in  std_logic_vector (15 downto 0);
    DAT_O_ma: out std_logic_vector (15 downto 0);
    ADR_O_ma: out std_logic_vector (7 downto 0);
    CYC_O_ma: out std_logic;
    STB_O_ma: out std_logic;
    ACK_I_ma: in  std_logic ;
    WE_O_ma:  out std_logic;
 
    -- Common signals
    RST_I: in std_logic;
    CLK_I: in std_logic
  );
  end component eppwbn_width_extension;
 
  component eppwbn_16bit is
  port(
    -- TEMPORAL
    epp_mode_monitor: out std_logic_vector (1 downto 0);
 
        -- Externo
    nStrobe:      in std_logic;                       --  HostClk/nWrite 
        Data:         inout std_logic_vector (7 downto 0);--   AD8..1 (Data1..Data8)
        nAck:         out std_logic;                      --  PtrClk/PeriphClk/Intr
        busy:         out std_logic;                      --  PtrBusy/PeriphAck/nWait
        PError:       out std_logic;                      --  AckData/nAckReverse
        Sel:          out std_logic;                      --  XFlag (Select)
        nAutoFd:      in std_logic;                       --  HostBusy/HostAck/nDStrb
        PeriphLogicH: out std_logic;                      --  (Periph Logic High)
    nInit:        in std_logic;                       --  nReverseRequest
        nFault:       out std_logic;                      --  nDataAvail/nPeriphRequest
        nSelectIn:    in std_logic;                       --  1284 Active/nAStrb
 
 
        --  Interno
        RST_I: in std_logic;
        CLK_I: in std_logic;
        DAT_I: in std_logic_vector (15 downto 0);
        DAT_O: out std_logic_vector (15 downto 0);
        ADR_O: out std_logic_vector (7 downto 0);
        CYC_O: out std_logic;
        STB_O: out std_logic;
        ACK_I: in std_logic ;
        WE_O: out std_logic
        );
  end component eppwbn_16bit;
 
  component eppwbn_16bit_test is
  port(
    -- al puerto EPP
    nStrobe:    in std_logic;                                                                                   -- Nomenclatura IEEE Std. 1284 
                                                -- HostClk/nWrite 
    Data:       inout std_logic_vector (7 downto 0);     -- AD8..1 (Data1..Data8)
    nAck:       out std_logic;                                                                                          --  PtrClk/PeriphClk/Intr
    busy:       out std_logic;                                                                                          --  PtrBusy/PeriphAck/nWait
    PError:     out std_logic;                                                                          --  AckData/nAckReverse
    Sel:        out std_logic;                                                                          --  XFlag (Select)
    nAutoFd:    in std_logic;                                                                           --  HostBusy/HostAck/nDStrb
    PeriphLogicH: out std_logic;                                                                --  (Periph Logic High)
    nInit:      in std_logic;                                                                           --  nReverseRequest
    nFault:     out std_logic;                                                                          --  nDataAvail/nPeriphRequest
    nSelectIn:  in std_logic;                                                                           --  1284 Active/nAStrb
 
    -- a los switches
    rst:        in std_logic;
 
    -- al clock
    clk:        in std_logic;
 
    -- monitores
    data_monitor:     out std_logic_vector (7 downto 0);
    epp_mode_monitor: out std_logic_vector (1 downto 0)
 
        );
  end component eppwbn_16bit_test;
 
  component eppwbn_16bit_test_wb_side is
  generic (
    ADD_WIDTH   : integer ;
    WIDTH       : integer
    );
  port(
    RST_I:  in std_logic;
    CLK_I:  in std_logic;
    DAT_I:  in std_logic_vector (WIDTH-1 downto 0);
    DAT_O:  out std_logic_vector (WIDTH-1 downto 0);
    ADR_I:  in std_logic_vector (7 downto 0);
    CYC_I:  in std_logic;
    STB_I:  in std_logic;
    ACK_O:  out std_logic ;
    WE_I:   in std_logic
        );
  end component eppwbn_16bit_test_wb_side;
 
  -- Clock (Actel specific)
  component A3PE_pll is
      port(POWERDOWN, CLKA : in std_logic;  LOCK, GLA : out
          std_logic) ;
  end component A3PE_pll;
 
  component dual_port_memory_wb is
  port(
    -- Puerto A (Higer prioriry)
    RST_I_a: in std_logic;
    CLK_I_a: in std_logic;
    DAT_I_a: in std_logic_vector (15 downto 0);
    DAT_O_a: out std_logic_vector (15 downto 0);
    ADR_I_a: in std_logic_vector (13 downto 0);
    CYC_I_a: in std_logic;
    STB_I_a: in std_logic;
    ACK_O_a: out std_logic ;
    WE_I_a: in std_logic;
 
 
    -- Puerto B (Lower prioriry)
    RST_I_b: in std_logic;
    CLK_I_b: in std_logic;
    DAT_I_b: in std_logic_vector (15 downto 0);
    DAT_O_b: out std_logic_vector (15 downto 0);
    ADR_I_b: in std_logic_vector (13 downto 0);
    CYC_I_b: in std_logic;
    STB_I_b: in std_logic;
    ACK_O_b: out std_logic ;
    WE_I_b: in std_logic
  );
  end component dual_port_memory_wb;
 
 
end package eppwbn_pkg;
 

Browse

Tools

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 37

Line No.	Rev	Author	Line
1	22	budinero	`----------------------------------------------------------------------------------------------------`
2			`--\| UNSL - Modular Oscilloscope`
3			`--\|`
4			`--\| File: eppwbn_wbn_side.vhd`
5			`--\| Version: 0.2`
6			`--\| Tested in: Actel APA300`
7			`--\|-------------------------------------------------------------------------------------------------`
8			`--\| Description:`
9			`--\| EPP - Wishbone bridge.`
10	34	budinero	`--\| Package for instantiate EPP-WBN modules.`
11	22	budinero	`--\|-------------------------------------------------------------------------------------------------`
12			`--\| File history:`
13			`--\| 0.01 \| dic-2008 \| First release`
14			`--\| 0.10 \| jan-2009 \| Added testing memory`
15			`--\| 0.20 \| mar-2009 \| Added extension module`
16			`----------------------------------------------------------------------------------------------------`
17			`--\| Copyright � 2008, Facundo Aguilera.`
18			`--\|`
19			`--\| This VHDL design file is an open design; you can redistribute it and/or`
20			`--\| modify it and/or implement it after contacting the author.`
21			`----------------------------------------------------------------------------------------------------`
22
23
24			`-- Bloque completo`
25			`library IEEE;`
26			`use IEEE.STD_LOGIC_1164.ALL;`
27
28	34	budinero
29	22	budinero	`package eppwbn_pkg is`
30			`--------------------------------------------------------------------------------------------------`
31			`-- Componentes`
32
33			`-- Bridge control`
34			`component eppwbn_ctrl is`
35			`port(`
36			`nStrobe: in std_logic;`
37
38			`Data: in std_logic_vector (7 downto 0);`
39			`nAck: out std_logic;`
40			`PError: out std_logic;`
41			`Sel: out std_logic;`
42			`nAutoFd: in std_logic;`
43			`PeriphLogicH: out std_logic;`
44			`nInit: in std_logic;`
45			`nFault: out std_logic;`
46			`nSelectIn: in std_logic;`
47
48			`RST_I: in std_logic;`
49			`CLK_I: in std_logic;`
50
51			`rst_pp: out std_logic;`
52			`epp_mode: out std_logic_vector (1 downto 0)`
53			`);`
54			`end component eppwbn_ctrl;`
55
56			`-- Comunication with EPP interface`
57			`component eppwbn_epp_side is`
58			`port(`
59			`epp_mode: in std_logic_vector (1 downto 0);`
60
61			`ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;`
62
63			`ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;`
64
65			`wb_Busy: in std_logic;`
66			`wb_nAutoFd: out std_logic;`
67			`wb_nSelectIn: out std_logic;`
68			`wb_nStrobe: out std_logic;`
69
70			`nAck, PError, Sel, nFault: out std_logic;`
71
72			`Busy: out std_logic;`
73			`nAutoFd: in std_logic;`
74			`nSelectIn: in std_logic;`
75			`nStrobe: in std_logic`
76			`);`
77			`end component eppwbn_epp_side;`
78
79			`-- Comunication with WB interface`
80			`component eppwbn_wbn_side is`
81			`port(`
82			`inStrobe: in std_logic;`
83			`iData: inout std_logic_vector (7 downto 0);`
84			`iBusy: out std_logic;`
85			`inAutoFd: in std_logic;`
86			`inSelectIn: in std_logic;`
87
88			`RST_I, CLK_I: in std_logic;`
89			`DAT_I: in std_logic_vector (7 downto 0);`
90			`DAT_O: out std_logic_vector (7 downto 0);`
91			`ADR_O: out std_logic_vector (7 downto 0);`
92			`CYC_O, STB_O: out std_logic;`
93			`ACK_I: in std_logic ;`
94			`WE_O: out std_logic;`
95
96			`rst_pp: in std_logic`
97			`);`
98			`end component eppwbn_wbn_side;`
99
100			`-- Testing memory`
101			`component test_memory is`
102			`generic ( --USE_RESET : boolean := false; -- use system reset`
103
104			`--USE_CS : boolean := false; -- use chip select signal`
105
106			`DEFAULT_OUT : std_logic; -- Default output`
107			`--OPTION : integer := 1; -- 1: Registered read Address(suitable`
108			`-- for Altera's FPGAs`
109			`-- 0: non registered read address`
110			`ADD_WIDTH : integer;`
111			`WIDTH : integer);`
112
113			`port (`
114			`cs: in std_logic; -- chip select`
115			`clk: in std_logic; -- write clock`
116			`reset: in std_logic; -- System Reset`
117			`add: in std_logic_vector(add_width -1 downto 0); -- Address`
118			`Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data`
119			`Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data`
120			`WR: in std_logic); -- Read Write Enable`
121			`end component test_memory;`
122
123			`-- Epp-wishbone bridge`
124			`component eppwbn is`
125			`port(`
126			`-- TEMPORAL`
127			`epp_mode_monitor: out std_logic_vector (1 downto 0);`
128
129			`-- Externo`
130			`nStrobe: in std_logic; -- HostClk/nWrite`
131			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
132			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
133			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
134			`PError: out std_logic; -- AckData/nAckReverse`
135			`Sel: out std_logic; -- XFlag (Select)`
136			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
137			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
138			`nInit: in std_logic; -- nReverseRequest`
139			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
140			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
141
142			`-- Interno`
143			`RST_I: in std_logic;`
144			`CLK_I: in std_logic;`
145			`DAT_I: in std_logic_vector (7 downto 0);`
146			`DAT_O: out std_logic_vector (7 downto 0);`
147			`ADR_O: out std_logic_vector (7 downto 0);`
148			`CYC_O: out std_logic;`
149			`STB_O: out std_logic;`
150			`ACK_I: in std_logic ;`
151			`WE_O: out std_logic`
152			`);`
153			`end component eppwbn;`
154
155			`-- Testing component`
156			`component eppwbn_test_wb_side is`
157			`port(`
158			`RST_I: in std_logic;`
159			`CLK_I: in std_logic;`
160			`DAT_I: in std_logic_vector (7 downto 0);`
161			`DAT_O: out std_logic_vector (7 downto 0);`
162			`ADR_I: in std_logic_vector (7 downto 0);`
163			`CYC_I: in std_logic;`
164			`STB_I: in std_logic;`
165			`ACK_O: out std_logic ;`
166			`WE_I: in std_logic`
167			`);`
168			`end component eppwbn_test_wb_side;`
169
170
171			`-- Width extension`
172			`component eppwbn_width_extension is`
173			`generic (`
174			`TIME_OUT_VALUE: integer;`
175			`TIME_OUT_WIDTH: integer`
176			`);`
177			`port(`
178			`-- Slave signals`
179			`DAT_I_sl: in std_logic_vector (7 downto 0);`
180			`DAT_O_sl: out std_logic_vector (7 downto 0);`
181			`ADR_I_sl: in std_logic_vector (7 downto 0);`
182			`CYC_I_sl: in std_logic;`
183			`STB_I_sl: in std_logic;`
184			`ACK_O_sl: out std_logic ;`
185			`WE_I_sl: in std_logic;`
186
187
188			`-- Master signals`
189			`DAT_I_ma: in std_logic_vector (15 downto 0);`
190			`DAT_O_ma: out std_logic_vector (15 downto 0);`
191			`ADR_O_ma: out std_logic_vector (7 downto 0);`
192			`CYC_O_ma: out std_logic;`
193			`STB_O_ma: out std_logic;`
194			`ACK_I_ma: in std_logic ;`
195			`WE_O_ma: out std_logic;`
196
197			`-- Common signals`
198			`RST_I: in std_logic;`
199			`CLK_I: in std_logic`
200			`);`
201			`end component eppwbn_width_extension;`
202
203			`component eppwbn_16bit is`
204			`port(`
205			`-- TEMPORAL`
206			`epp_mode_monitor: out std_logic_vector (1 downto 0);`
207
208			`-- Externo`
209			`nStrobe: in std_logic; -- HostClk/nWrite`
210			`Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)`
211			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
212			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
213			`PError: out std_logic; -- AckData/nAckReverse`
214			`Sel: out std_logic; -- XFlag (Select)`
215			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
216			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
217			`nInit: in std_logic; -- nReverseRequest`
218			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
219			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
220
221
222			`-- Interno`
223			`RST_I: in std_logic;`
224			`CLK_I: in std_logic;`
225			`DAT_I: in std_logic_vector (15 downto 0);`
226			`DAT_O: out std_logic_vector (15 downto 0);`
227			`ADR_O: out std_logic_vector (7 downto 0);`
228			`CYC_O: out std_logic;`
229			`STB_O: out std_logic;`
230			`ACK_I: in std_logic ;`
231			`WE_O: out std_logic`
232			`);`
233			`end component eppwbn_16bit;`
234
235			`component eppwbn_16bit_test is`
236			`port(`
237			`-- al puerto EPP`
238			`nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284`
239			`-- HostClk/nWrite`
240			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
241			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
242			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
243			`PError: out std_logic; -- AckData/nAckReverse`
244			`Sel: out std_logic; -- XFlag (Select)`
245			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
246			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
247			`nInit: in std_logic; -- nReverseRequest`
248			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
249			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
250
251			`-- a los switches`
252			`rst: in std_logic;`
253
254			`-- al clock`
255			`clk: in std_logic;`
256
257			`-- monitores`
258			`data_monitor: out std_logic_vector (7 downto 0);`
259			`epp_mode_monitor: out std_logic_vector (1 downto 0)`
260
261			`);`
262			`end component eppwbn_16bit_test;`
263
264			`component eppwbn_16bit_test_wb_side is`
265			`generic (`
266			`ADD_WIDTH : integer ;`
267			`WIDTH : integer`
268			`);`
269			`port(`
270			`RST_I: in std_logic;`
271			`CLK_I: in std_logic;`
272			`DAT_I: in std_logic_vector (WIDTH-1 downto 0);`
273			`DAT_O: out std_logic_vector (WIDTH-1 downto 0);`
274			`ADR_I: in std_logic_vector (7 downto 0);`
275			`CYC_I: in std_logic;`
276			`STB_I: in std_logic;`
277			`ACK_O: out std_logic ;`
278			`WE_I: in std_logic`
279			`);`
280			`end component eppwbn_16bit_test_wb_side;`
281
282			`-- Clock (Actel specific)`
283			`component A3PE_pll is`
284			`port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out`
285			`std_logic) ;`
286			`end component A3PE_pll;`
287
288			`component dual_port_memory_wb is`
289			`port(`
290			`-- Puerto A (Higer prioriry)`
291			`RST_I_a: in std_logic;`
292			`CLK_I_a: in std_logic;`
293			`DAT_I_a: in std_logic_vector (15 downto 0);`
294			`DAT_O_a: out std_logic_vector (15 downto 0);`
295			`ADR_I_a: in std_logic_vector (13 downto 0);`
296			`CYC_I_a: in std_logic;`
297			`STB_I_a: in std_logic;`
298			`ACK_O_a: out std_logic ;`
299			`WE_I_a: in std_logic;`
300
301
302			`-- Puerto B (Lower prioriry)`
303			`RST_I_b: in std_logic;`
304			`CLK_I_b: in std_logic;`
305			`DAT_I_b: in std_logic_vector (15 downto 0);`
306			`DAT_O_b: out std_logic_vector (15 downto 0);`
307			`ADR_I_b: in std_logic_vector (13 downto 0);`
308			`CYC_I_b: in std_logic;`
309			`STB_I_b: in std_logic;`
310			`ACK_O_b: out std_logic ;`
311			`WE_I_b: in std_logic`
312			`);`
313			`end component dual_port_memory_wb;`
314
315
316			`end package eppwbn_pkg;`
317	19	budinero