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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 57

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----------------------------------------------------------------------------------------------------
--| UNSL - Modular Oscilloscope
--|
--| File: eppwbn_wbn_side.vhd
--| Version: 0.2
--| Tested in: Actel APA300
--| Tested in: Actel A3PE1500
--|   Board: RVI Prototype Board + LP Data Conversion Daughter Board
--|-------------------------------------------------------------------------------------------------
--| Description:
--|   EPP - Wishbone bridge. 
--|       Package for instantiate EPP-WBN modules.
--|-------------------------------------------------------------------------------------------------
--| File history:
--|   0.01  | dic-2008 | First release
--|   0.10  | jan-2009 | Added testing memory
--|   0.20  | mar-2009 | Added extension module
----------------------------------------------------------------------------------------------------
--| Copyright � 2008, Facundo Aguilera.
--|
--| This VHDL design file is an open design; you can redistribute it and/or
--| modify it and/or implement it after contacting the author.
----------------------------------------------------------------------------------------------------
 
 
-- Bloque completo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
package eppwbn_pkg is
        --------------------------------------------------------------------------------------------------
        -- Componentes  
 
  -- Bridge control
  component eppwbn_ctrl is
    port(
      nStrobe:      in  std_logic;
 
      Data:         in  std_logic_vector (7 downto 0);
      nAck:         out std_logic;
      PError:       out std_logic;
      Sel:          out std_logic;
      nAutoFd:      in  std_logic;
      PeriphLogicH: out std_logic;
      nInit:        in  std_logic;
      nFault:       out std_logic;
      nSelectIn:    in  std_logic;
 
      RST_I:        in  std_logic;
      CLK_I:        in  std_logic;
 
      rst_pp:       out std_logic;
      epp_mode:     out std_logic_vector (1 downto 0)
          );
        end component eppwbn_ctrl;
 
  -- Comunication with EPP interface
  component eppwbn_epp_side is
                port(
                        epp_mode: in std_logic_vector (1 downto 0);
 
                        ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault:   in std_logic;
 
                        ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe:    out std_logic;
 
                        wb_Busy:       in   std_logic;
                        wb_nAutoFd:    out  std_logic;
                        wb_nSelectIn:  out  std_logic;
                        wb_nStrobe:    out  std_logic;
 
                        nAck, PError, Sel, nFault:   out std_logic;
 
                        Busy:         out   std_logic;
                        nAutoFd:      in    std_logic;
                        nSelectIn:    in    std_logic;
                        nStrobe:      in    std_logic
                );
        end component eppwbn_epp_side;
 
        -- Comunication with WB interface
  component eppwbn_wbn_side is
                port(
                        inStrobe:     in    std_logic;
                        iData:        inout std_logic_vector (7 downto 0);
                        iBusy:        out   std_logic;
                        inAutoFd:     in    std_logic;
                        inSelectIn:   in    std_logic;
 
                        RST_I, CLK_I: in    std_logic;
                        DAT_I:        in    std_logic_vector (7 downto 0);
                        DAT_O:        out   std_logic_vector (7 downto 0);
                        ADR_O:        out   std_logic_vector (7 downto 0);
                        CYC_O, STB_O: out   std_logic;
                        ACK_I:        in    std_logic ;
                        WE_O:         out   std_logic;
 
                        rst_pp:       in std_logic
                );
        end component eppwbn_wbn_side;
 
        -- Testing memory
  component test_memory is
    generic ( --USE_RESET   : boolean   := false;  -- use system reset
 
              --USE_CS      : boolean   := false;  -- use chip select signal
 
              DEFAULT_OUT : std_logic;  -- Default output
              --OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
                                          -- for Altera's FPGAs
                                          -- 0: non registered read address
              ADD_WIDTH   : integer;
              WIDTH       : integer);
 
    port (
      cs:        in  std_logic;           -- chip select
      clk:       in  std_logic;           -- write clock
      reset:     in  std_logic;           -- System Reset
      add:       in  std_logic_vector(add_width -1 downto 0);   --  Address
      Data_In:   in  std_logic_vector(WIDTH -1 downto 0);       -- input data
      Data_Out:  out std_logic_vector(WIDTH -1 downto 0);       -- Output Data
      WR:        in  std_logic);          -- Read Write Enable
  end component test_memory;
 
  -- Epp-wishbone bridge
  component eppwbn is
    port(
      -- TEMPORAL
      --epp_mode_monitor: out std_logic_vector (1 downto 0);
 
      -- Externo
      nStrobe:      in    std_logic;                                                            -- HostClk/nWrite       
      Data:         inout std_logic_vector (7 downto 0);         -- AD8..1 (Data1..Data8)
      nAck:         out   std_logic;                                                                                    -- PtrClk/PeriphClk/Intr
      busy:         out   std_logic;                                                                                    -- PtrBusy/PeriphAck/nWait
      PError:       out   std_logic;                                                                                    -- AckData/nAckReverse
      Sel:          out   std_logic;                                                                                    -- XFlag (Select)
      nAutoFd:      in    std_logic;                                                                                    -- HostBusy/HostAck/nDStrb
      PeriphLogicH: out   std_logic;                                                                  -- (Periph Logic High)
      nInit:        in    std_logic;                                                                                    -- nReverseRequest
      nFault:       out   std_logic;                                                                                    -- nDataAvail/nPeriphRequest
      nSelectIn:    in    std_logic;                                                                              -- 1284 Active/nAStrb
 
      --  Interno
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_O:  out std_logic_vector (7 downto 0);
      CYC_O:  out std_logic;
      STB_O:  out std_logic;
      ACK_I:  in  std_logic ;
      WE_O:   out std_logic
      );
  end component eppwbn;
 
  -- Testing component
  component eppwbn_test_wb_side is
    port(
      RST_I:  in  std_logic;
      CLK_I:  in  std_logic;
      DAT_I:  in  std_logic_vector (7 downto 0);
      DAT_O:  out std_logic_vector (7 downto 0);
      ADR_I:  in  std_logic_vector (7 downto 0);
      CYC_I:  in  std_logic;
      STB_I:  in  std_logic;
      ACK_O:  out std_logic ;
      WE_I:   in  std_logic
    );
  end component eppwbn_test_wb_side;
 
 
  -- Width extension
  component eppwbn_width_extension is
  generic (
    TIME_OUT_VALUE: integer;
    TIME_OUT_WIDTH: integer
  );
  port(
    -- Slave signals
    DAT_I_sl: in  std_logic_vector (7 downto 0);
    DAT_O_sl: out std_logic_vector (7 downto 0);
    ADR_I_sl: in  std_logic_vector (7 downto 0);
    CYC_I_sl: in  std_logic;
    STB_I_sl: in  std_logic;
    ACK_O_sl: out std_logic ;
    WE_I_sl:  in  std_logic;
 
 
    --  Master signals
    DAT_I_ma: in  std_logic_vector (15 downto 0);
    DAT_O_ma: out std_logic_vector (15 downto 0);
    ADR_O_ma: out std_logic_vector (7 downto 0);
    CYC_O_ma: out std_logic;
    STB_O_ma: out std_logic;
    ACK_I_ma: in  std_logic ;
    WE_O_ma:  out std_logic;
 
    -- Common signals
    RST_I: in std_logic;
    CLK_I: in std_logic
  );
  end component eppwbn_width_extension;
 
  component eppwbn_16bit is
  port(
    -- TEMPORAL
    --epp_mode_monitor: out std_logic_vector (1 downto 0);
 
        -- Externo
    nStrobe:      in std_logic;                       --  HostClk/nWrite 
        Data:         inout std_logic_vector (7 downto 0);--   AD8..1 (Data1..Data8)
        nAck:         out std_logic;                      --  PtrClk/PeriphClk/Intr
        busy:         out std_logic;                      --  PtrBusy/PeriphAck/nWait
        PError:       out std_logic;                      --  AckData/nAckReverse
        Sel:          out std_logic;                      --  XFlag (Select)
        nAutoFd:      in std_logic;                       --  HostBusy/HostAck/nDStrb
        PeriphLogicH: out std_logic;                      --  (Periph Logic High)
    nInit:        in std_logic;                       --  nReverseRequest
        nFault:       out std_logic;                      --  nDataAvail/nPeriphRequest
        nSelectIn:    in std_logic;                       --  1284 Active/nAStrb
 
 
        --  Interno
        RST_I: in std_logic;
        CLK_I: in std_logic;
        DAT_I: in std_logic_vector (15 downto 0);
        DAT_O: out std_logic_vector (15 downto 0);
        ADR_O: out std_logic_vector (7 downto 0);
        CYC_O: out std_logic;
        STB_O: out std_logic;
        ACK_I: in std_logic ;
        WE_O: out std_logic
        );
  end component eppwbn_16bit;
 
  component eppwbn_16bit_test is
  port(
    -- al puerto EPP
    nStrobe:    in std_logic;                                                                                   -- Nomenclatura IEEE Std. 1284 
                                                -- HostClk/nWrite 
    Data:       inout std_logic_vector (7 downto 0);     -- AD8..1 (Data1..Data8)
    nAck:       out std_logic;                                                                                          --  PtrClk/PeriphClk/Intr
    busy:       out std_logic;                                                                                          --  PtrBusy/PeriphAck/nWait
    PError:     out std_logic;                                                                          --  AckData/nAckReverse
    Sel:        out std_logic;                                                                          --  XFlag (Select)
    nAutoFd:    in std_logic;                                                                           --  HostBusy/HostAck/nDStrb
    PeriphLogicH: out std_logic;                                                                --  (Periph Logic High)
    nInit:      in std_logic;                                                                           --  nReverseRequest
    nFault:     out std_logic;                                                                          --  nDataAvail/nPeriphRequest
    nSelectIn:  in std_logic;                                                                           --  1284 Active/nAStrb
 
    -- a los switches
    rst:        in std_logic;
 
    -- al clock
    clk:        in std_logic;
 
    -- monitores
    data_monitor:     out std_logic_vector (7 downto 0);
    epp_mode_monitor: out std_logic_vector (1 downto 0)
 
        );
  end component eppwbn_16bit_test;
 
  component eppwbn_16bit_test_wb_side is
  generic (
    ADD_WIDTH   : integer ;
    WIDTH       : integer
    );
  port(
    RST_I:  in std_logic;
    CLK_I:  in std_logic;
    DAT_I:  in std_logic_vector (WIDTH-1 downto 0);
    DAT_O:  out std_logic_vector (WIDTH-1 downto 0);
    ADR_I:  in std_logic_vector (7 downto 0);
    CYC_I:  in std_logic;
    STB_I:  in std_logic;
    ACK_O:  out std_logic ;
    WE_I:   in std_logic
        );
  end component eppwbn_16bit_test_wb_side;
 
  -- Clock (Actel specific)
  component A3PE_pll is
      port(POWERDOWN, CLKA : in std_logic;  LOCK, GLA : out
          std_logic) ;
  end component A3PE_pll;
 
end package eppwbn_pkg;
 

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Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [eppwbn_pkg.vhd] - Blame information for rev 57

Line No.	Rev	Author	Line
1	22	budinero	`----------------------------------------------------------------------------------------------------`
2			`--\| UNSL - Modular Oscilloscope`
3			`--\|`
4			`--\| File: eppwbn_wbn_side.vhd`
5			`--\| Version: 0.2`
6			`--\| Tested in: Actel APA300`
7	51	budinero	`--\| Tested in: Actel A3PE1500`
8			`--\| Board: RVI Prototype Board + LP Data Conversion Daughter Board`
9	22	budinero	`--\|-------------------------------------------------------------------------------------------------`
10			`--\| Description:`
11			`--\| EPP - Wishbone bridge.`
12	34	budinero	`--\| Package for instantiate EPP-WBN modules.`
13	22	budinero	`--\|-------------------------------------------------------------------------------------------------`
14			`--\| File history:`
15			`--\| 0.01 \| dic-2008 \| First release`
16			`--\| 0.10 \| jan-2009 \| Added testing memory`
17			`--\| 0.20 \| mar-2009 \| Added extension module`
18			`----------------------------------------------------------------------------------------------------`
19	41	budinero	`--\| Copyright � 2008, Facundo Aguilera.`
20	22	budinero	`--\|`
21			`--\| This VHDL design file is an open design; you can redistribute it and/or`
22			`--\| modify it and/or implement it after contacting the author.`
23			`----------------------------------------------------------------------------------------------------`
24
25
26			`-- Bloque completo`
27			`library IEEE;`
28			`use IEEE.STD_LOGIC_1164.ALL;`
29
30	34	budinero
31	22	budinero	`package eppwbn_pkg is`
32			`--------------------------------------------------------------------------------------------------`
33			`-- Componentes`
34
35			`-- Bridge control`
36			`component eppwbn_ctrl is`
37			`port(`
38			`nStrobe: in std_logic;`
39
40			`Data: in std_logic_vector (7 downto 0);`
41			`nAck: out std_logic;`
42			`PError: out std_logic;`
43			`Sel: out std_logic;`
44			`nAutoFd: in std_logic;`
45			`PeriphLogicH: out std_logic;`
46			`nInit: in std_logic;`
47			`nFault: out std_logic;`
48			`nSelectIn: in std_logic;`
49
50			`RST_I: in std_logic;`
51			`CLK_I: in std_logic;`
52
53			`rst_pp: out std_logic;`
54			`epp_mode: out std_logic_vector (1 downto 0)`
55			`);`
56			`end component eppwbn_ctrl;`
57
58			`-- Comunication with EPP interface`
59			`component eppwbn_epp_side is`
60			`port(`
61			`epp_mode: in std_logic_vector (1 downto 0);`
62
63			`ctr_nAck, ctr_PError, ctr_Sel, ctr_nFault: in std_logic;`
64
65			`ctr_nAutoFd, ctr_nSelectIn, ctr_nStrobe: out std_logic;`
66
67			`wb_Busy: in std_logic;`
68			`wb_nAutoFd: out std_logic;`
69			`wb_nSelectIn: out std_logic;`
70			`wb_nStrobe: out std_logic;`
71
72			`nAck, PError, Sel, nFault: out std_logic;`
73
74			`Busy: out std_logic;`
75			`nAutoFd: in std_logic;`
76			`nSelectIn: in std_logic;`
77			`nStrobe: in std_logic`
78			`);`
79			`end component eppwbn_epp_side;`
80
81			`-- Comunication with WB interface`
82			`component eppwbn_wbn_side is`
83			`port(`
84			`inStrobe: in std_logic;`
85			`iData: inout std_logic_vector (7 downto 0);`
86			`iBusy: out std_logic;`
87			`inAutoFd: in std_logic;`
88			`inSelectIn: in std_logic;`
89
90			`RST_I, CLK_I: in std_logic;`
91			`DAT_I: in std_logic_vector (7 downto 0);`
92			`DAT_O: out std_logic_vector (7 downto 0);`
93			`ADR_O: out std_logic_vector (7 downto 0);`
94			`CYC_O, STB_O: out std_logic;`
95			`ACK_I: in std_logic ;`
96			`WE_O: out std_logic;`
97
98			`rst_pp: in std_logic`
99			`);`
100			`end component eppwbn_wbn_side;`
101
102			`-- Testing memory`
103			`component test_memory is`
104			`generic ( --USE_RESET : boolean := false; -- use system reset`
105
106			`--USE_CS : boolean := false; -- use chip select signal`
107
108			`DEFAULT_OUT : std_logic; -- Default output`
109			`--OPTION : integer := 1; -- 1: Registered read Address(suitable`
110			`-- for Altera's FPGAs`
111			`-- 0: non registered read address`
112			`ADD_WIDTH : integer;`
113			`WIDTH : integer);`
114
115			`port (`
116			`cs: in std_logic; -- chip select`
117			`clk: in std_logic; -- write clock`
118			`reset: in std_logic; -- System Reset`
119			`add: in std_logic_vector(add_width -1 downto 0); -- Address`
120			`Data_In: in std_logic_vector(WIDTH -1 downto 0); -- input data`
121			`Data_Out: out std_logic_vector(WIDTH -1 downto 0); -- Output Data`
122			`WR: in std_logic); -- Read Write Enable`
123			`end component test_memory;`
124
125			`-- Epp-wishbone bridge`
126			`component eppwbn is`
127			`port(`
128			`-- TEMPORAL`
129	51	budinero	`--epp_mode_monitor: out std_logic_vector (1 downto 0);`
130	22	budinero
131			`-- Externo`
132			`nStrobe: in std_logic; -- HostClk/nWrite`
133			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
134			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
135			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
136			`PError: out std_logic; -- AckData/nAckReverse`
137			`Sel: out std_logic; -- XFlag (Select)`
138			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
139			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
140			`nInit: in std_logic; -- nReverseRequest`
141			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
142			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
143
144			`-- Interno`
145			`RST_I: in std_logic;`
146			`CLK_I: in std_logic;`
147			`DAT_I: in std_logic_vector (7 downto 0);`
148			`DAT_O: out std_logic_vector (7 downto 0);`
149			`ADR_O: out std_logic_vector (7 downto 0);`
150			`CYC_O: out std_logic;`
151			`STB_O: out std_logic;`
152			`ACK_I: in std_logic ;`
153			`WE_O: out std_logic`
154			`);`
155			`end component eppwbn;`
156
157			`-- Testing component`
158			`component eppwbn_test_wb_side is`
159			`port(`
160			`RST_I: in std_logic;`
161			`CLK_I: in std_logic;`
162			`DAT_I: in std_logic_vector (7 downto 0);`
163			`DAT_O: out std_logic_vector (7 downto 0);`
164			`ADR_I: in std_logic_vector (7 downto 0);`
165			`CYC_I: in std_logic;`
166			`STB_I: in std_logic;`
167			`ACK_O: out std_logic ;`
168			`WE_I: in std_logic`
169			`);`
170			`end component eppwbn_test_wb_side;`
171
172
173			`-- Width extension`
174			`component eppwbn_width_extension is`
175			`generic (`
176			`TIME_OUT_VALUE: integer;`
177			`TIME_OUT_WIDTH: integer`
178			`);`
179			`port(`
180			`-- Slave signals`
181			`DAT_I_sl: in std_logic_vector (7 downto 0);`
182			`DAT_O_sl: out std_logic_vector (7 downto 0);`
183			`ADR_I_sl: in std_logic_vector (7 downto 0);`
184			`CYC_I_sl: in std_logic;`
185			`STB_I_sl: in std_logic;`
186			`ACK_O_sl: out std_logic ;`
187			`WE_I_sl: in std_logic;`
188
189
190			`-- Master signals`
191			`DAT_I_ma: in std_logic_vector (15 downto 0);`
192			`DAT_O_ma: out std_logic_vector (15 downto 0);`
193			`ADR_O_ma: out std_logic_vector (7 downto 0);`
194			`CYC_O_ma: out std_logic;`
195			`STB_O_ma: out std_logic;`
196			`ACK_I_ma: in std_logic ;`
197			`WE_O_ma: out std_logic;`
198
199			`-- Common signals`
200			`RST_I: in std_logic;`
201			`CLK_I: in std_logic`
202			`);`
203			`end component eppwbn_width_extension;`
204
205			`component eppwbn_16bit is`
206			`port(`
207			`-- TEMPORAL`
208	51	budinero	`--epp_mode_monitor: out std_logic_vector (1 downto 0);`
209	22	budinero
210			`-- Externo`
211			`nStrobe: in std_logic; -- HostClk/nWrite`
212			`Data: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)`
213			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
214			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
215			`PError: out std_logic; -- AckData/nAckReverse`
216			`Sel: out std_logic; -- XFlag (Select)`
217			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
218			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
219			`nInit: in std_logic; -- nReverseRequest`
220			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
221			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
222
223
224			`-- Interno`
225			`RST_I: in std_logic;`
226			`CLK_I: in std_logic;`
227			`DAT_I: in std_logic_vector (15 downto 0);`
228			`DAT_O: out std_logic_vector (15 downto 0);`
229			`ADR_O: out std_logic_vector (7 downto 0);`
230			`CYC_O: out std_logic;`
231			`STB_O: out std_logic;`
232			`ACK_I: in std_logic ;`
233			`WE_O: out std_logic`
234			`);`
235			`end component eppwbn_16bit;`
236
237			`component eppwbn_16bit_test is`
238			`port(`
239			`-- al puerto EPP`
240			`nStrobe: in std_logic; -- Nomenclatura IEEE Std. 1284`
241			`-- HostClk/nWrite`
242			`Data: inout std_logic_vector (7 downto 0); -- AD8..1 (Data1..Data8)`
243			`nAck: out std_logic; -- PtrClk/PeriphClk/Intr`
244			`busy: out std_logic; -- PtrBusy/PeriphAck/nWait`
245			`PError: out std_logic; -- AckData/nAckReverse`
246			`Sel: out std_logic; -- XFlag (Select)`
247			`nAutoFd: in std_logic; -- HostBusy/HostAck/nDStrb`
248			`PeriphLogicH: out std_logic; -- (Periph Logic High)`
249			`nInit: in std_logic; -- nReverseRequest`
250			`nFault: out std_logic; -- nDataAvail/nPeriphRequest`
251			`nSelectIn: in std_logic; -- 1284 Active/nAStrb`
252
253			`-- a los switches`
254			`rst: in std_logic;`
255
256			`-- al clock`
257			`clk: in std_logic;`
258
259			`-- monitores`
260			`data_monitor: out std_logic_vector (7 downto 0);`
261			`epp_mode_monitor: out std_logic_vector (1 downto 0)`
262
263			`);`
264			`end component eppwbn_16bit_test;`
265
266			`component eppwbn_16bit_test_wb_side is`
267			`generic (`
268			`ADD_WIDTH : integer ;`
269			`WIDTH : integer`
270			`);`
271			`port(`
272			`RST_I: in std_logic;`
273			`CLK_I: in std_logic;`
274			`DAT_I: in std_logic_vector (WIDTH-1 downto 0);`
275			`DAT_O: out std_logic_vector (WIDTH-1 downto 0);`
276			`ADR_I: in std_logic_vector (7 downto 0);`
277			`CYC_I: in std_logic;`
278			`STB_I: in std_logic;`
279			`ACK_O: out std_logic ;`
280			`WE_I: in std_logic`
281			`);`
282			`end component eppwbn_16bit_test_wb_side;`
283
284			`-- Clock (Actel specific)`
285			`component A3PE_pll is`
286			`port(POWERDOWN, CLKA : in std_logic; LOCK, GLA : out`
287			`std_logic) ;`
288			`end component A3PE_pll;`
289
290			`end package eppwbn_pkg;`
291	19	budinero