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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [memory_8bit_reset.vhd] - Blame information for rev 19

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1 19 budinero 
-------------------------------------------------------------------------------
2 
-- Title      :  Single port RAM
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-- Project    :  Memory Cores
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-------------------------------------------------------------------------------
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-- File        : spmem.vhd
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-- Author      : Jamil Khatib  (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Created     : 1999/5/14
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-- Last update : 2000/12/19
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-- Platform    :
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-- Simulators  : Modelsim 5.3XE/Windows98
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-- Synthesizers: Leonardo/WindowsNT
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-- Target      :
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-- Dependency  : ieee.std_logic_1164,ieee.std_logic_unsigned
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-------------------------------------------------------------------------------
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-- Description:  Single Port memory
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :   12 May 1999
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Created
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   2
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-- Version         :   0.2
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-- Date            :   19 Dec 2000
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   General review
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--                     Two versions are now available with reset and without
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--                     Default output can can be defined
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   3
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-- Version         :   0.3
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-- Date            :   5 Jan 2001
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Registered Read Address feature is added to make use of
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--                     Altera's FPGAs memory bits
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--                     This feature was added from Richard Herveille's
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--                     contribution and his memory core
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
58 
 
59 
-- (!)
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-- Original file modified to reduce code and make WR and reset signals
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-- positive, make Reset sincronous, make data transfer asinc.
62 
 
63 
 
64 
library ieee;
65 
 
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use ieee.std_logic_1164.all;
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68 
use ieee.std_logic_unsigned.all;
69 
 
70 
-------------------------------------------------------------------------------
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-- Single port Memory core with reset
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-- To make use of on FPGA memory bits do not use the RESET option
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-- For Altera's FPGA you have to use also OPTION := 1
74 
 
75 
entity mem_8bit_reset is
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  generic ( --USE_RESET   : boolean   := false;  -- use system reset
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            --USE_CS      : boolean   := false;  -- use chip select signal
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            DEFAULT_OUT : std_logic := '0';  -- Default output
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            --OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
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                                        -- for Altera's FPGAs
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                                        -- 0: non registered read address
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            ADD_WIDTH   : integer   := 8;
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            WIDTH       : integer   := 8);
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88 
  port (
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    cs       : in  std_logic;           -- chip select
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    clk      : in  std_logic;           -- write clock
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    reset    : in  std_logic;           -- System Reset
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    add      : in  std_logic_vector(add_width -1 downto 0);  --  Address
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    Data_In  : in  std_logic_vector(WIDTH -1 downto 0);  -- input data
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    Data_Out : out std_logic_vector(WIDTH -1 downto 0);  -- Output Data
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    WR       : in  std_logic);          -- Read Write Enable
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end mem_8bit_reset;
97 
 
98 
 
99 
 
100 
architecture spmem_beh of mem_8bit_reset is
101 
 
102 
  type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
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 -- signal s_reset: std_logic;
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                                                      -- Memory Type
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  signal data : data_array(0 to (2** add_width-1) );  -- Local data
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107 
 
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        -- FLEX/APEX devices require address to be registered with inclock for read operations
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  -- This signal is used only when OPTION = 1
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        -- signal regA : std_logic_vector( (add_width -1) downto 0);
111 
 
112 
  procedure init_mem(signal memory_cell : inout data_array ) is
113 
 
114 
  begin
115 
 
116 
    for i in 0 to (2** add_width-1) loop
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      memory_cell(i) <= (others => '0');
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    end loop;
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120 
  end init_mem;
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begin  -- spmem_beh
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-- -------------------------------------------------------------------------------
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-- -- Non Registered Read Address
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-- -------------------------------------------------------------------------------
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   -- NON_REG         : if OPTION = 0 generate
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-- -------------------------------------------------------------------------------
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-- -- Clocked Process with Reset
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-- -------------------------------------------------------------------------------
130 
   -- Reset_ENABLED : if USE_RESET = true generate
131 
 
132 
-- -------------------------------------------------------------------------------
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--      CS_ENABLED  : if USE_CS = true generate
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135 
        process (clk, reset,CS,WR, add)
136 
 
137 
        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
139 
 
140 
          -- activities triggered by rising edge of clock
141 
 
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          data_out <= data(conv_integer(add));
143 
 
144 
 
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          if clk'event and clk = '1' then
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                if reset = '1' then
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              init_mem (data);
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                elsif CS = '1' then
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                  if WR = '1' then
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                      data(conv_integer(add)) <= Data_In;
151 
                  end if;
152 
                end if;
153 
          end if;
154 
 
155 
 
156 
        end process;
157 
--     end generate CS_ENABLED;
158 
-------------------------------------------------------------------------------
159 
-------------------------------------------------------------------------------
160 
      -- CS_DISABLED : if USE_CS = false generate
161 
 
162 
        -- process (clk, reset)
163 
 
164 
 
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        -- begin  -- PROCESS
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          -- -- activities triggered by asynchronous reset (active low)
167 
 
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          -- if reset = '0' then
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            -- data_out <= (others => DEFAULT_OUT);
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            -- init_mem ( data);
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            -- -- activities triggered by rising edge of clock
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          -- elsif clk'event and clk = '1' then
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            -- if WR = '0' then
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              -- data(conv_integer(add)) <= data_in;
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              -- data_out                <= (others => DEFAULT_OUT);
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            -- else
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              -- data_out                <= data(conv_integer(add));
179 
            -- end if;
180 
 
181 
          -- end if;
182 
 
183 
        -- end process;
184 
      -- end generate CS_DISABLED;
185 
 
186 
-- -------------------------------------------------------------------------------
187 
-- -------------------------------------------------------------------------------
188 
    -- end generate Reset_ENABLED;
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-- -------------------------------------------------------------------------------
190 
-- -------------------------------------------------------------------------------
191 
-- -------------------------------------------------------------------------------
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-- -- Clocked Process without Reset
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-- -------------------------------------------------------------------------------
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    -- Reset_DISABLED : if USE_RESET = false generate
195 
 
196 
-- -------------------------------------------------------------------------------
197 
-- -------------------------------------------------------------------------------
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      -- CS_ENABLED   : if USE_CS = true generate
199 
 
200 
        -- process (clk)
201 
        -- begin  -- PROCESS
202 
 
203 
          -- -- activities triggered by rising edge of clock
204 
          -- if clk'event and clk = '1' then
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            -- if cs = '1' then
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              -- if WR = '0' then
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                -- data(conv_integer(add)) <= data_in;
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                -- data_out                <= (others => DEFAULT_OUT);
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              -- else
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                -- data_out                <= data(conv_integer(add));
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              -- end if;
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            -- else
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              -- data_out                  <= (others => DEFAULT_OUT);
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            -- end if;
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216 
 
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          -- end if;
218 
 
219 
        -- end process;
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      -- end generate CS_ENABLED;
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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      -- CS_DISABLED : if USE_CS = false generate
224 
 
225 
        -- process (clk)
226 
        -- begin  -- PROCESS
227 
 
228 
          -- -- activities triggered by rising edge of clock
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          -- if clk'event and clk = '1' then
230 
            -- if WR = '0' then
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              -- data(conv_integer(add)) <= data_in;
232 
              -- data_out                <= (others => DEFAULT_OUT);
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            -- else
234 
              -- data_out                <= data(conv_integer(add));
235 
            -- end if;
236 
 
237 
          -- end if;
238 
 
239 
        -- end process;
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      -- end generate CS_DISABLED;
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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    -- end generate Reset_DISABLED;
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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  -- end generate NON_REG;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- REG: if OPTION = 1 generate
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-- -------------------------------------------------------------------------------
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-- -- Clocked Process with Reset
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-- -------------------------------------------------------------------------------
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    -- Reset_ENABLED : if USE_RESET = true generate
257 
 
258 
-- -------------------------------------------------------------------------------
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      -- CS_ENABLED  : if USE_CS = true generate
260 
 
261 
        -- process (clk, reset)
262 
 
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        -- begin  -- PROCESS
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          -- -- activities triggered by asynchronous reset (active low)
265 
 
266 
          -- if reset = '0' then
267 
            -- data_out <= (others => DEFAULT_OUT);
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            -- init_mem ( data);
269 
 
270 
            -- -- activities triggered by rising edge of clock
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          -- elsif clk'event and clk = '1' then
272 
 
273 
            -- regA <= add;
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275 
            -- if CS = '1' then
276 
              -- if WR = '0' then
277 
                -- data(conv_integer(add)) <= data_in;
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                -- data_out                <= (others => DEFAULT_OUT);
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              -- else
280 
                -- data_out                <= data(conv_integer(regA));
281 
              -- end if;
282 
            -- else
283 
              -- data_out                  <= (others => DEFAULT_OUT);
284 
            -- end if;
285 
 
286 
          -- end if;
287 
 
288 
        -- end process;
289 
      -- end generate CS_ENABLED;
290 
-- -------------------------------------------------------------------------------
291 
-- -------------------------------------------------------------------------------
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      -- CS_DISABLED : if USE_CS = false generate
293 
 
294 
        -- process (clk, reset)
295 
 
296 
 
297 
        -- begin  -- PROCESS
298 
          -- -- activities triggered by asynchronous reset (active low)
299 
 
300 
          -- if reset = '0' then
301 
            -- data_out <= (others => DEFAULT_OUT);
302 
            -- init_mem ( data);
303 
 
304 
            -- -- activities triggered by rising edge of clock
305 
          -- elsif clk'event and clk = '1' then
306 
            -- regA <= add;
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308 
            -- if WR = '0' then
309 
              -- data(conv_integer(add)) <= data_in;
310 
              -- data_out                <= (others => DEFAULT_OUT);
311 
            -- else
312 
              -- data_out                <= data(conv_integer(regA));
313 
            -- end if;
314 
 
315 
          -- end if;
316 
 
317 
        -- end process;
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      -- end generate CS_DISABLED;
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-- -------------------------------------------------------------------------------
321 
-- -------------------------------------------------------------------------------
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    -- end generate Reset_ENABLED;
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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-- -- Clocked Process without Reset
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-- -------------------------------------------------------------------------------
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    -- Reset_DISABLED : if USE_RESET = false generate
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330 
-- -------------------------------------------------------------------------------
331 
-- -------------------------------------------------------------------------------
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      -- CS_ENABLED   : if USE_CS = true generate
333 
 
334 
        -- process (clk)
335 
        -- begin  -- PROCESS
336 
 
337 
          -- -- activities triggered by rising edge of clock
338 
          -- if clk'event and clk = '1' then
339 
 
340 
            -- regA <= add;
341 
 
342 
            -- if cs = '1' then
343 
              -- if WR = '0' then
344 
                -- data(conv_integer(add)) <= data_in;
345 
                -- data_out                <= (others => DEFAULT_OUT);
346 
              -- else
347 
                -- data_out                <= data(conv_integer(regA));
348 
              -- end if;
349 
            -- else
350 
              -- data_out                  <= (others => DEFAULT_OUT);
351 
            -- end if;
352 
 
353 
 
354 
          -- end if;
355 
 
356 
        -- end process;
357 
      -- end generate CS_ENABLED;
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-- -------------------------------------------------------------------------------
359 
-- -------------------------------------------------------------------------------
360 
      -- CS_DISABLED : if USE_CS = false generate
361 
 
362 
        -- process (clk)
363 
        -- begin  -- PROCESS
364 
 
365 
          -- -- activities triggered by rising edge of clock
366 
          -- if clk'event and clk = '1' then
367 
 
368 
            -- regA <= add;
369 
 
370 
            -- if WR = '0' then
371 
              -- data(conv_integer(add)) <= data_in;
372 
              -- data_out                <= (others => DEFAULT_OUT);
373 
            -- else
374 
              -- data_out                <= data(conv_integer(regA));
375 
            -- end if;
376 
 
377 
          -- end if;
378 
 
379 
        -- end process;
380 
      -- end generate CS_DISABLED;
381 
-- -------------------------------------------------------------------------------
382 
-- -------------------------------------------------------------------------------
383 
    -- end generate Reset_DISABLED;
384 
-- -------------------------------------------------------------------------------
385 
-- -------------------------------------------------------------------------------
386 
-- -------------------------------------------------------------------------------
387 
 
388 
-- end generate REG;
389 
 
390 
end spmem_beh;
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-------------------------------------------------------------------------------

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