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[/] [modular_oscilloscope/] [trunk/] [hdl/] [epp/] [memory_original.vhd] - Blame information for rev 19

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1 19 budinero 
-------------------------------------------------------------------------------
2 
-- Title      :  Single port RAM
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-- Project    :  Memory Cores
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-------------------------------------------------------------------------------
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-- File        : spmem.vhd
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-- Author      : Jamil Khatib  (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Created     : 1999/5/14
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-- Last update : 2000/12/19
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-- Platform    :
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-- Simulators  : Modelsim 5.3XE/Windows98
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-- Synthesizers: Leonardo/WindowsNT
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-- Target      :
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-- Dependency  : ieee.std_logic_1164,ieee.std_logic_unsigned
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-------------------------------------------------------------------------------
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-- Description:  Single Port memory
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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25 
-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :   12 May 1999
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Created
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   2
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-- Version         :   0.2
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-- Date            :   19 Dec 2000
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   General review
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--                     Two versions are now available with reset and without
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--                     Default output can can be defined
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   3
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-- Version         :   0.3
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-- Date            :   5 Jan 2001
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Registered Read Address feature is added to make use of
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--                     Altera's FPGAs memory bits
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--                     This feature was added from Richard Herveille's
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--                     contribution and his memory core
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
58 
 
59 
 
60 
 
61 
library ieee;
62 
 
63 
use ieee.std_logic_1164.all;
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65 
use ieee.std_logic_unsigned.all;
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67 
-------------------------------------------------------------------------------
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-- Single port Memory core with reset
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-- To make use of on FPGA memory bits do not use the RESET option
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-- For Altera's FPGA you have to use also OPTION := 1
71 
 
72 
entity Spmem_ent is
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  generic ( USE_RESET   : boolean   := false;  -- use system reset
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            USE_CS      : boolean   := false;  -- use chip select signal
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            DEFAULT_OUT : std_logic := '1';  -- Default output
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            OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
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                                        -- for Altera's FPGAs
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                                        -- 0: non registered read address
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            ADD_WIDTH   : integer   := 3;
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            WIDTH       : integer   := 8);
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  port (
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    cs       :     std_logic;           -- chip select
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    clk      : in  std_logic;           -- write clock
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    reset    : in  std_logic;           -- System Reset
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    add      : in  std_logic_vector(add_width -1 downto 0);  --  Address
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    Data_In  : in  std_logic_vector(WIDTH -1 downto 0);  -- input data
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    Data_Out : out std_logic_vector(WIDTH -1 downto 0);  -- Output Data
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    WR       : in  std_logic);          -- Read Write Enable
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end Spmem_ent;
94 
 
95 
 
96 
 
97 
architecture spmem_beh of Spmem_ent is
98 
 
99 
  type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
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                                                      -- Memory Type
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  signal data : data_array(0 to (2** add_width-1) );  -- Local data
102 
 
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        -- FLEX/APEX devices require address to be registered with inclock for read operations
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  -- This signal is used only when OPTION = 1
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        signal regA : std_logic_vector( (add_width -1) downto 0);
106 
 
107 
  procedure init_mem(signal memory_cell : inout data_array ) is
108 
 
109 
  begin
110 
 
111 
    for i in 0 to (2** add_width-1) loop
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      memory_cell(i) <= (others => '0');
113 
    end loop;
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115 
  end init_mem;
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begin  -- spmem_beh
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-------------------------------------------------------------------------------
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-- Non Registered Read Address
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-------------------------------------------------------------------------------
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  NON_REG         : if OPTION = 0 generate
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-------------------------------------------------------------------------------
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-- Clocked Process with Reset
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-------------------------------------------------------------------------------
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    Reset_ENABLED : if USE_RESET = true generate
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127 
-------------------------------------------------------------------------------
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      CS_ENABLED  : if USE_CS = true generate
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        process (clk, reset)
131 
 
132 
        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
134 
 
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          if reset = '0' then
136 
            data_out <= (others => DEFAULT_OUT);
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            init_mem ( data);
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            -- activities triggered by rising edge of clock
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          elsif clk'event and clk = '1' then
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            if CS = '1' then
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              if WR = '0' then
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                data(conv_integer(add)) <= data_in;
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                data_out                <= (others => DEFAULT_OUT);
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              else
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                data_out                <= data(conv_integer(add));
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              end if;
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            else
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              data_out                  <= (others => DEFAULT_OUT);
150 
            end if;
151 
 
152 
          end if;
153 
 
154 
        end process;
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      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
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160 
        process (clk, reset)
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162 
 
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        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
165 
 
166 
          if reset = '0' then
167 
            data_out <= (others => DEFAULT_OUT);
168 
            init_mem ( data);
169 
 
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            -- activities triggered by rising edge of clock
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          elsif clk'event and clk = '1' then
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            if WR = '0' then
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              data(conv_integer(add)) <= data_in;
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              data_out                <= (others => DEFAULT_OUT);
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            else
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              data_out                <= data(conv_integer(add));
177 
            end if;
178 
 
179 
          end if;
180 
 
181 
        end process;
182 
      end generate CS_DISABLED;
183 
 
184 
-------------------------------------------------------------------------------
185 
-------------------------------------------------------------------------------
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    end generate Reset_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
189 
-------------------------------------------------------------------------------
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-- Clocked Process without Reset
191 
-------------------------------------------------------------------------------
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    Reset_DISABLED : if USE_RESET = false generate
193 
 
194 
-------------------------------------------------------------------------------
195 
-------------------------------------------------------------------------------
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      CS_ENABLED   : if USE_CS = true generate
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198 
        process (clk)
199 
        begin  -- PROCESS
200 
 
201 
          -- activities triggered by rising edge of clock
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          if clk'event and clk = '1' then
203 
            if cs = '1' then
204 
              if WR = '0' then
205 
                data(conv_integer(add)) <= data_in;
206 
                data_out                <= (others => DEFAULT_OUT);
207 
              else
208 
                data_out                <= data(conv_integer(add));
209 
              end if;
210 
            else
211 
              data_out                  <= (others => DEFAULT_OUT);
212 
            end if;
213 
 
214 
 
215 
          end if;
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217 
        end process;
218 
      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
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223 
        process (clk)
224 
        begin  -- PROCESS
225 
 
226 
          -- activities triggered by rising edge of clock
227 
          if clk'event and clk = '1' then
228 
            if WR = '0' then
229 
              data(conv_integer(add)) <= data_in;
230 
              data_out                <= (others => DEFAULT_OUT);
231 
            else
232 
              data_out                <= data(conv_integer(add));
233 
            end if;
234 
 
235 
          end if;
236 
 
237 
        end process;
238 
      end generate CS_DISABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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    end generate Reset_DISABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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  end generate NON_REG;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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REG: if OPTION = 1 generate
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-------------------------------------------------------------------------------
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-- Clocked Process with Reset
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-------------------------------------------------------------------------------
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    Reset_ENABLED : if USE_RESET = true generate
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256 
-------------------------------------------------------------------------------
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      CS_ENABLED  : if USE_CS = true generate
258 
 
259 
        process (clk, reset)
260 
 
261 
        begin  -- PROCESS
262 
          -- activities triggered by asynchronous reset (active low)
263 
 
264 
          if reset = '0' then
265 
            data_out <= (others => DEFAULT_OUT);
266 
            init_mem ( data);
267 
 
268 
            -- activities triggered by rising edge of clock
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          elsif clk'event and clk = '1' then
270 
 
271 
            regA <= add;
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273 
            if CS = '1' then
274 
              if WR = '0' then
275 
                data(conv_integer(add)) <= data_in;
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                data_out                <= (others => DEFAULT_OUT);
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              else
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                data_out                <= data(conv_integer(regA));
279 
              end if;
280 
            else
281 
              data_out                  <= (others => DEFAULT_OUT);
282 
            end if;
283 
 
284 
          end if;
285 
 
286 
        end process;
287 
      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
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292 
        process (clk, reset)
293 
 
294 
 
295 
        begin  -- PROCESS
296 
          -- activities triggered by asynchronous reset (active low)
297 
 
298 
          if reset = '0' then
299 
            data_out <= (others => DEFAULT_OUT);
300 
            init_mem ( data);
301 
 
302 
            -- activities triggered by rising edge of clock
303 
          elsif clk'event and clk = '1' then
304 
            regA <= add;
305 
 
306 
            if WR = '0' then
307 
              data(conv_integer(add)) <= data_in;
308 
              data_out                <= (others => DEFAULT_OUT);
309 
            else
310 
              data_out                <= data(conv_integer(regA));
311 
            end if;
312 
 
313 
          end if;
314 
 
315 
        end process;
316 
      end generate CS_DISABLED;
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318 
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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    end generate Reset_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Clocked Process without Reset
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-------------------------------------------------------------------------------
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    Reset_DISABLED : if USE_RESET = false generate
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328 
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      CS_ENABLED   : if USE_CS = true generate
331 
 
332 
        process (clk)
333 
        begin  -- PROCESS
334 
 
335 
          -- activities triggered by rising edge of clock
336 
          if clk'event and clk = '1' then
337 
 
338 
            regA <= add;
339 
 
340 
            if cs = '1' then
341 
              if WR = '0' then
342 
                data(conv_integer(add)) <= data_in;
343 
                data_out                <= (others => DEFAULT_OUT);
344 
              else
345 
                data_out                <= data(conv_integer(regA));
346 
              end if;
347 
            else
348 
              data_out                  <= (others => DEFAULT_OUT);
349 
            end if;
350 
 
351 
 
352 
          end if;
353 
 
354 
        end process;
355 
      end generate CS_ENABLED;
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-------------------------------------------------------------------------------
357 
-------------------------------------------------------------------------------
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      CS_DISABLED : if USE_CS = false generate
359 
 
360 
        process (clk)
361 
        begin  -- PROCESS
362 
 
363 
          -- activities triggered by rising edge of clock
364 
          if clk'event and clk = '1' then
365 
 
366 
            regA <= add;
367 
 
368 
            if WR = '0' then
369 
              data(conv_integer(add)) <= data_in;
370 
              data_out                <= (others => DEFAULT_OUT);
371 
            else
372 
              data_out                <= data(conv_integer(regA));
373 
            end if;
374 
 
375 
          end if;
376 
 
377 
        end process;
378 
      end generate CS_DISABLED;
379 
-------------------------------------------------------------------------------
380 
-------------------------------------------------------------------------------
381 
    end generate Reset_DISABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
384 
-------------------------------------------------------------------------------
385 
 
386 
end generate REG;
387 
 
388 
end spmem_beh;
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-------------------------------------------------------------------------------
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391 14 budinero 
1

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