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-------------------------------------------------------------------------------
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-- Title      :  Single port RAM
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-- Project    :  Memory Cores
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-------------------------------------------------------------------------------
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-- File        : spmem.vhd
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-- Author      : Jamil Khatib  (khatib@ieee.org)
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-- Organization: OpenIPCore Project
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-- Created     : 1999/5/14
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-- Last update : 2000/12/19
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-- Platform    :
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-- Simulators  : Modelsim 5.3XE/Windows98
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-- Synthesizers: Leonardo/WindowsNT
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-- Target      :
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-- Dependency  : ieee.std_logic_1164,ieee.std_logic_unsigned
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-------------------------------------------------------------------------------
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-- Description:  Single Port memory
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-------------------------------------------------------------------------------
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-- Copyright (c) 2000 Jamil Khatib
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- You can check the draft license at
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-- http://www.opencores.org/OIPC/license.shtml
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1
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-- Version         :   0.1
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-- Date            :   12 May 1999
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Created
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   2
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-- Version         :   0.2
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-- Date            :   19 Dec 2000
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   General review
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--                     Two versions are now available with reset and without
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--                     Default output can can be defined
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   3
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-- Version         :   0.3
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-- Date            :   5 Jan 2001
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-- Modifier        :   Jamil Khatib (khatib@ieee.org)
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-- Desccription    :   Registered Read Address feature is added to make use of
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--                     Altera's FPGAs memory bits
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--                     This feature was added from Richard Herveille's
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--                     contribution and his memory core
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-- Known bugs      :
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-- To Optimze      :
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Revision Number :   1asinc
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-- Version         :   0.1asinc
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-- Date            :   13 Mar 2009
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-- Modifier        :   Aguilera Facundo (afacu@ieee.org)
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-- Desccription    :   Original file modified to reduce code and to make WR and
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--                     reset signals positive, Reset sincronous, data transfer
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--                     asinc.
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-------------------------------------------------------------------------------
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-- (!)
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-- Original file modified to reduce code and to make WR and reset signals
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-- positive, Reset sincronous, data transfer asinc.
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72 
 
73 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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-- Single port Memory core with reset
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-- To make use of on FPGA memory bits do not use the RESET option
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-- For Altera's FPGA you have to use also OPTION := 1
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84 
entity test_memory is
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  generic ( --USE_RESET   : boolean   := false;  -- use system reset
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            --USE_CS      : boolean   := false;  -- use chip select signal
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            DEFAULT_OUT : std_logic := '0';  -- Default output
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            --OPTION      : integer   := 1;  -- 1: Registered read Address(suitable
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                                        -- for Altera's FPGAs
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                                        -- 0: non registered read address
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            ADD_WIDTH   : integer   := 8;
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            WIDTH       : integer   := 8);
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  port (
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    cs       : in  std_logic;           -- chip select
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    clk      : in  std_logic;           -- write clock
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    reset    : in  std_logic;           -- System Reset
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    add      : in  std_logic_vector(add_width -1 downto 0);  --  Address
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    Data_In  : in  std_logic_vector(WIDTH -1 downto 0);  -- input data
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    Data_Out : out std_logic_vector(WIDTH -1 downto 0);  -- Output Data
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    WR       : in  std_logic);          -- Read Write Enable
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end test_memory;
105 
 
106 
 
107 
 
108 
architecture spmem_beh of test_memory is
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  type data_array is array (integer range <>) of std_logic_vector(WIDTH-1 downto 0);
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 -- signal s_reset: std_logic;
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                                                      -- Memory Type
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  signal data : data_array(0 to (2** add_width-1) );  -- Local data
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115 
 
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        -- FLEX/APEX devices require address to be registered with inclock for read operations
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  -- This signal is used only when OPTION = 1
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        -- signal regA : std_logic_vector( (add_width -1) downto 0);
119 
 
120 
  procedure init_mem(signal memory_cell : inout data_array ) is
121 
 
122 
  begin
123 
 
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    for i in 0 to (2** add_width-1) loop
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      memory_cell(i) <= (others => '0');
126 
    end loop;
127 
 
128 
  end init_mem;
129 
 
130 
begin  -- spmem_beh
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-- -------------------------------------------------------------------------------
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-- -- Non Registered Read Address
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-- -------------------------------------------------------------------------------
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   -- NON_REG         : if OPTION = 0 generate
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-- -------------------------------------------------------------------------------
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-- -- Clocked Process with Reset
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-- -------------------------------------------------------------------------------
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   -- Reset_ENABLED : if USE_RESET = true generate
139 
 
140 
-- -------------------------------------------------------------------------------
141 
--      CS_ENABLED  : if USE_CS = true generate
142 
 
143 
        process (clk, reset,CS,WR, add)
144 
 
145 
        begin  -- PROCESS
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          -- activities triggered by asynchronous reset (active low)
147 
 
148 
          -- activities triggered by rising edge of clock
149 
 
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          data_out <= data(conv_integer(add));
151 
 
152 
 
153 
          if clk'event and clk = '1' then
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                if reset = '1' then
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              init_mem (data);
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                elsif CS = '1' then
157 43 budinero 
              if WR = '1' then
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                  data(conv_integer(add)) <= Data_In;
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              end if;
160 
            end if;
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          end if;
162 
 
163 
 
164 
        end process;
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--     end generate CS_ENABLED;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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      -- CS_DISABLED : if USE_CS = false generate
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170 
        -- process (clk, reset)
171 
 
172 
 
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        -- begin  -- PROCESS
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          -- -- activities triggered by asynchronous reset (active low)
175 
 
176 
          -- if reset = '0' then
177 
            -- data_out <= (others => DEFAULT_OUT);
178 
            -- init_mem ( data);
179 
 
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            -- -- activities triggered by rising edge of clock
181 
          -- elsif clk'event and clk = '1' then
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            -- if WR = '0' then
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              -- data(conv_integer(add)) <= data_in;
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              -- data_out                <= (others => DEFAULT_OUT);
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            -- else
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              -- data_out                <= data(conv_integer(add));
187 
            -- end if;
188 
 
189 
          -- end if;
190 
 
191 
        -- end process;
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      -- end generate CS_DISABLED;
193 
 
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-- -------------------------------------------------------------------------------
195 
-- -------------------------------------------------------------------------------
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    -- end generate Reset_ENABLED;
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-- -------------------------------------------------------------------------------
198 
-- -------------------------------------------------------------------------------
199 
-- -------------------------------------------------------------------------------
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-- -- Clocked Process without Reset
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-- -------------------------------------------------------------------------------
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    -- Reset_DISABLED : if USE_RESET = false generate
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204 
-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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      -- CS_ENABLED   : if USE_CS = true generate
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        -- process (clk)
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        -- begin  -- PROCESS
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          -- -- activities triggered by rising edge of clock
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          -- if clk'event and clk = '1' then
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            -- if cs = '1' then
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              -- if WR = '0' then
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                -- data(conv_integer(add)) <= data_in;
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                -- data_out                <= (others => DEFAULT_OUT);
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              -- else
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                -- data_out                <= data(conv_integer(add));
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              -- end if;
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            -- else
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              -- data_out                  <= (others => DEFAULT_OUT);
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            -- end if;
223 
 
224 
 
225 
          -- end if;
226 
 
227 
        -- end process;
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      -- end generate CS_ENABLED;
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-- -------------------------------------------------------------------------------
230 
-- -------------------------------------------------------------------------------
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      -- CS_DISABLED : if USE_CS = false generate
232 
 
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        -- process (clk)
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        -- begin  -- PROCESS
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          -- -- activities triggered by rising edge of clock
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          -- if clk'event and clk = '1' then
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            -- if WR = '0' then
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              -- data(conv_integer(add)) <= data_in;
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              -- data_out                <= (others => DEFAULT_OUT);
241 
            -- else
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              -- data_out                <= data(conv_integer(add));
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            -- end if;
244 
 
245 
          -- end if;
246 
 
247 
        -- end process;
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      -- end generate CS_DISABLED;
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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    -- end generate Reset_DISABLED;
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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  -- end generate NON_REG;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- REG: if OPTION = 1 generate
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-- -------------------------------------------------------------------------------
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-- -- Clocked Process with Reset
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-- -------------------------------------------------------------------------------
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    -- Reset_ENABLED : if USE_RESET = true generate
265 
 
266 
-- -------------------------------------------------------------------------------
267 
      -- CS_ENABLED  : if USE_CS = true generate
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269 
        -- process (clk, reset)
270 
 
271 
        -- begin  -- PROCESS
272 
          -- -- activities triggered by asynchronous reset (active low)
273 
 
274 
          -- if reset = '0' then
275 
            -- data_out <= (others => DEFAULT_OUT);
276 
            -- init_mem ( data);
277 
 
278 
            -- -- activities triggered by rising edge of clock
279 
          -- elsif clk'event and clk = '1' then
280 
 
281 
            -- regA <= add;
282 
 
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            -- if CS = '1' then
284 
              -- if WR = '0' then
285 
                -- data(conv_integer(add)) <= data_in;
286 
                -- data_out                <= (others => DEFAULT_OUT);
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              -- else
288 
                -- data_out                <= data(conv_integer(regA));
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              -- end if;
290 
            -- else
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              -- data_out                  <= (others => DEFAULT_OUT);
292 
            -- end if;
293 
 
294 
          -- end if;
295 
 
296 
        -- end process;
297 
      -- end generate CS_ENABLED;
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-- -------------------------------------------------------------------------------
299 
-- -------------------------------------------------------------------------------
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      -- CS_DISABLED : if USE_CS = false generate
301 
 
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        -- process (clk, reset)
303 
 
304 
 
305 
        -- begin  -- PROCESS
306 
          -- -- activities triggered by asynchronous reset (active low)
307 
 
308 
          -- if reset = '0' then
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            -- data_out <= (others => DEFAULT_OUT);
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            -- init_mem ( data);
311 
 
312 
            -- -- activities triggered by rising edge of clock
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          -- elsif clk'event and clk = '1' then
314 
            -- regA <= add;
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            -- if WR = '0' then
317 
              -- data(conv_integer(add)) <= data_in;
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              -- data_out                <= (others => DEFAULT_OUT);
319 
            -- else
320 
              -- data_out                <= data(conv_integer(regA));
321 
            -- end if;
322 
 
323 
          -- end if;
324 
 
325 
        -- end process;
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      -- end generate CS_DISABLED;
327 
 
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-- -------------------------------------------------------------------------------
329 
-- -------------------------------------------------------------------------------
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    -- end generate Reset_ENABLED;
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-- -------------------------------------------------------------------------------
332 
-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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-- -- Clocked Process without Reset
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-- -------------------------------------------------------------------------------
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    -- Reset_DISABLED : if USE_RESET = false generate
337 
 
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-- -------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------
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      -- CS_ENABLED   : if USE_CS = true generate
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342 
        -- process (clk)
343 
        -- begin  -- PROCESS
344 
 
345 
          -- -- activities triggered by rising edge of clock
346 
          -- if clk'event and clk = '1' then
347 
 
348 
            -- regA <= add;
349 
 
350 
            -- if cs = '1' then
351 
              -- if WR = '0' then
352 
                -- data(conv_integer(add)) <= data_in;
353 
                -- data_out                <= (others => DEFAULT_OUT);
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              -- else
355 
                -- data_out                <= data(conv_integer(regA));
356 
              -- end if;
357 
            -- else
358 
              -- data_out                  <= (others => DEFAULT_OUT);
359 
            -- end if;
360 
 
361 
 
362 
          -- end if;
363 
 
364 
        -- end process;
365 
      -- end generate CS_ENABLED;
366 
-- -------------------------------------------------------------------------------
367 
-- -------------------------------------------------------------------------------
368 
      -- CS_DISABLED : if USE_CS = false generate
369 
 
370 
        -- process (clk)
371 
        -- begin  -- PROCESS
372 
 
373 
          -- -- activities triggered by rising edge of clock
374 
          -- if clk'event and clk = '1' then
375 
 
376 
            -- regA <= add;
377 
 
378 
            -- if WR = '0' then
379 
              -- data(conv_integer(add)) <= data_in;
380 
              -- data_out                <= (others => DEFAULT_OUT);
381 
            -- else
382 
              -- data_out                <= data(conv_integer(regA));
383 
            -- end if;
384 
 
385 
          -- end if;
386 
 
387 
        -- end process;
388 
      -- end generate CS_DISABLED;
389 
-- -------------------------------------------------------------------------------
390 
-- -------------------------------------------------------------------------------
391 
    -- end generate Reset_DISABLED;
392 
-- -------------------------------------------------------------------------------
393 
-- -------------------------------------------------------------------------------
394 
-- -------------------------------------------------------------------------------
395 
 
396 
-- end generate REG;
397 
 
398 
end spmem_beh;
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-------------------------------------------------------------------------------

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