Subversion Repositories modular_oscilloscope

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--| Modular Oscilloscope

--| UNSL - Argentine

--|

--| File: dual_port_memory.vhd

--| Version: 0.1

--| Tested in: Actel A3PE1500

--|-------------------------------------------------------------------------------------------------

--| Description:

--|   MEMORY - Dual Port Memory

--|   Generated with Actel SmartGen tool. It will not work with other Actel FPGA than A3PE1500 

--|             or similar.

--|-------------------------------------------------------------------------------------------------

--| File history:

--|   0.10  | jan-2009 | First release

----------------------------------------------------------------------------------------------------

-- Libero Project Manager Version: 8.5 SP1 8.5.1.13

-- Copyright 1989-2009  Actel Corporation

-- · Parámetros 

---- Generales

-- Reset: Not inverted

-- Double clock

-- High Speed

---- Para ambos puertos

-- Depth: 15360

-- Width: 16

-- BLKx: Not Inverted

-- CLKA: Rising

-- Pipeline: no

-- DOUT type: DINA0

library ieee;

use ieee.std_logic_1164.all;

library proasic3e;

use proasic3e.all;

entity dual_port_memory is

  port(

    DINA:   in    std_logic_vector(15 downto 0);

    DOUTA:  out   std_logic_vector(15 downto 0);

    ADDRA:  in    std_logic_vector(13 downto 0);  -- Only available until 15360

    RWA:    in    std_logic;                      -- '1' Read, '0' Write

    BLKA:   in    std_logic;                      -- '1' Block select

    CLKA:   in    std_logic;                      -- Rising edge

    DINB:   in    std_logic_vector(15 downto 0);

    DOUTB:  out   std_logic_vector(15 downto 0);

    ADDRB:  in    std_logic_vector(13 downto 0);

    RWB:    in    std_logic;

    BLKB:   in    std_logic;

    CLKB:   in    std_logic;

    RESET:  in    std_logic                       -- '1' Reset

  ) ;

end dual_port_memory;

architecture DEF_ARCH of  dual_port_memory is

    component BUFF

        port(A : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component RAM4K9

    generic (MEMORYFILE:string := "");

        port(ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,

        ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11,

        ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4,

        ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6,

        DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7,

        DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0,

        WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB,

        BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic :=

        'U'; DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3,

        DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5,

        DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic) ;

    end component;

    component OR2

        port(A, B : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component MX2

        port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component NAND2

        port(A, B : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component DFN1

        port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;

    end component;

    component INV

        port(A : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component AND2A

        port(A, B : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component NOR2

        port(A, B : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component AND2

        port(A, B : in std_logic := 'U'; Y : out std_logic) ;

    end component;

    component VCC

        port( Y : out std_logic);

    end component;

    component GND

        port( Y : out std_logic);

    end component;

    signal WEAP, WEBP, RESETP, ADDRA_FF2_0_net, ADDRA_FF2_1_net,

        ADDRA_FF2_2_net, ADDRA_FF2_3_net, ADDRB_FF2_0_net,

        ADDRB_FF2_1_net, ADDRB_FF2_2_net, ADDRB_FF2_3_net,

        ENABLE_ADDRA_0_net, ENABLE_ADDRA_1_net,

        ENABLE_ADDRA_2_net, ENABLE_ADDRA_3_net,

        ENABLE_ADDRA_4_net, ENABLE_ADDRA_5_net,

        ENABLE_ADDRA_6_net, ENABLE_ADDRA_7_net,

        ENABLE_ADDRA_8_net, ENABLE_ADDRA_9_net,

        ENABLE_ADDRA_10_net, ENABLE_ADDRA_11_net,

        ENABLE_ADDRA_12_net, ENABLE_ADDRA_13_net,

        ENABLE_ADDRA_14_net, ENABLE_ADDRB_0_net,

        ENABLE_ADDRB_1_net, ENABLE_ADDRB_2_net,

        ENABLE_ADDRB_3_net, ENABLE_ADDRB_4_net,

        ENABLE_ADDRB_5_net, ENABLE_ADDRB_6_net,

        ENABLE_ADDRB_7_net, ENABLE_ADDRB_8_net,

        ENABLE_ADDRB_9_net, ENABLE_ADDRB_10_net,

        ENABLE_ADDRB_11_net, ENABLE_ADDRB_12_net,

        ENABLE_ADDRB_13_net, ENABLE_ADDRB_14_net, BLKA_EN_0_net,

        BLKB_EN_0_net, BLKA_EN_1_net, BLKB_EN_1_net,

        BLKA_EN_2_net, BLKB_EN_2_net, BLKA_EN_3_net,

        BLKB_EN_3_net, BLKA_EN_4_net, BLKB_EN_4_net,

        BLKA_EN_5_net, BLKB_EN_5_net, BLKA_EN_6_net,

        BLKB_EN_6_net, BLKA_EN_7_net, BLKB_EN_7_net,

        BLKA_EN_8_net, BLKB_EN_8_net, BLKA_EN_9_net,

        BLKB_EN_9_net, BLKA_EN_10_net, BLKB_EN_10_net,

        BLKA_EN_11_net, BLKB_EN_11_net, BLKA_EN_12_net,

        BLKB_EN_12_net, BLKA_EN_13_net, BLKB_EN_13_net,

        BLKA_EN_14_net, BLKB_EN_14_net, QBX_TEMPR0_0_net,

        QBX_TEMPR0_1_net, QBX_TEMPR0_2_net, QBX_TEMPR0_3_net,

        QBX_TEMPR1_0_net, QBX_TEMPR1_1_net, QBX_TEMPR1_2_net,

        QBX_TEMPR1_3_net, QBX_TEMPR2_0_net, QBX_TEMPR2_1_net,

        QBX_TEMPR2_2_net, QBX_TEMPR2_3_net, QBX_TEMPR3_0_net,

        QBX_TEMPR3_1_net, QBX_TEMPR3_2_net, QBX_TEMPR3_3_net,

        QBX_TEMPR4_0_net, QBX_TEMPR4_1_net, QBX_TEMPR4_2_net,

        QBX_TEMPR4_3_net, QBX_TEMPR5_0_net, QBX_TEMPR5_1_net,

        QBX_TEMPR5_2_net, QBX_TEMPR5_3_net, QBX_TEMPR6_0_net,

        QBX_TEMPR6_1_net, QBX_TEMPR6_2_net, QBX_TEMPR6_3_net,

        QBX_TEMPR7_0_net, QBX_TEMPR7_1_net, QBX_TEMPR7_2_net,

        QBX_TEMPR7_3_net, QBX_TEMPR8_0_net, QBX_TEMPR8_1_net,

        QBX_TEMPR8_2_net, QBX_TEMPR8_3_net, QBX_TEMPR9_0_net,

        QBX_TEMPR9_1_net, QBX_TEMPR9_2_net, QBX_TEMPR9_3_net,

        QBX_TEMPR10_0_net, QBX_TEMPR10_1_net, QBX_TEMPR10_2_net,

        QBX_TEMPR10_3_net, QBX_TEMPR11_0_net, QBX_TEMPR11_1_net,

        QBX_TEMPR11_2_net, QBX_TEMPR11_3_net, QBX_TEMPR12_0_net,

        QBX_TEMPR12_1_net, QBX_TEMPR12_2_net, QBX_TEMPR12_3_net,

        QBX_TEMPR13_0_net, QBX_TEMPR13_1_net, QBX_TEMPR13_2_net,

        QBX_TEMPR13_3_net, QBX_TEMPR14_0_net, QBX_TEMPR14_1_net,

        QBX_TEMPR14_2_net, QBX_TEMPR14_3_net, QAX_TEMPR0_0_net,

        QAX_TEMPR0_1_net, QAX_TEMPR0_2_net, QAX_TEMPR0_3_net,

        QAX_TEMPR1_0_net, QAX_TEMPR1_1_net, QAX_TEMPR1_2_net,

        QAX_TEMPR1_3_net, QAX_TEMPR2_0_net, QAX_TEMPR2_1_net,

        QAX_TEMPR2_2_net, QAX_TEMPR2_3_net, QAX_TEMPR3_0_net,

        QAX_TEMPR3_1_net, QAX_TEMPR3_2_net, QAX_TEMPR3_3_net,

        QAX_TEMPR4_0_net, QAX_TEMPR4_1_net, QAX_TEMPR4_2_net,

        QAX_TEMPR4_3_net, QAX_TEMPR5_0_net, QAX_TEMPR5_1_net,

        QAX_TEMPR5_2_net, QAX_TEMPR5_3_net, QAX_TEMPR6_0_net,

        QAX_TEMPR6_1_net, QAX_TEMPR6_2_net, QAX_TEMPR6_3_net,

        QAX_TEMPR7_0_net, QAX_TEMPR7_1_net, QAX_TEMPR7_2_net,

        QAX_TEMPR7_3_net, QAX_TEMPR8_0_net, QAX_TEMPR8_1_net,

        QAX_TEMPR8_2_net, QAX_TEMPR8_3_net, QAX_TEMPR9_0_net,

        QAX_TEMPR9_1_net, QAX_TEMPR9_2_net, QAX_TEMPR9_3_net,

        QAX_TEMPR10_0_net, QAX_TEMPR10_1_net, QAX_TEMPR10_2_net,

        QAX_TEMPR10_3_net, QAX_TEMPR11_0_net, QAX_TEMPR11_1_net,

        QAX_TEMPR11_2_net, QAX_TEMPR11_3_net, QAX_TEMPR12_0_net,

        QAX_TEMPR12_1_net, QAX_TEMPR12_2_net, QAX_TEMPR12_3_net,

        QAX_TEMPR13_0_net, QAX_TEMPR13_1_net, QAX_TEMPR13_2_net,

        QAX_TEMPR13_3_net, QAX_TEMPR14_0_net, QAX_TEMPR14_1_net,

        QAX_TEMPR14_2_net, QAX_TEMPR14_3_net, QBX_TEMPR0_4_net,

        QBX_TEMPR0_5_net, QBX_TEMPR0_6_net, QBX_TEMPR0_7_net,

        QBX_TEMPR1_4_net, QBX_TEMPR1_5_net, QBX_TEMPR1_6_net,

        QBX_TEMPR1_7_net, QBX_TEMPR2_4_net, QBX_TEMPR2_5_net,

        QBX_TEMPR2_6_net, QBX_TEMPR2_7_net, QBX_TEMPR3_4_net,

        QBX_TEMPR3_5_net, QBX_TEMPR3_6_net, QBX_TEMPR3_7_net,

        QBX_TEMPR4_4_net, QBX_TEMPR4_5_net, QBX_TEMPR4_6_net,

        QBX_TEMPR4_7_net, QBX_TEMPR5_4_net, QBX_TEMPR5_5_net,

        QBX_TEMPR5_6_net, QBX_TEMPR5_7_net, QBX_TEMPR6_4_net,

        QBX_TEMPR6_5_net, QBX_TEMPR6_6_net, QBX_TEMPR6_7_net,

        QBX_TEMPR7_4_net, QBX_TEMPR7_5_net, QBX_TEMPR7_6_net,

        QBX_TEMPR7_7_net, QBX_TEMPR8_4_net, QBX_TEMPR8_5_net,

        QBX_TEMPR8_6_net, QBX_TEMPR8_7_net, QBX_TEMPR9_4_net,

        QBX_TEMPR9_5_net, QBX_TEMPR9_6_net, QBX_TEMPR9_7_net,

        QBX_TEMPR10_4_net, QBX_TEMPR10_5_net, QBX_TEMPR10_6_net,

        QBX_TEMPR10_7_net, QBX_TEMPR11_4_net, QBX_TEMPR11_5_net,

        QBX_TEMPR11_6_net, QBX_TEMPR11_7_net, QBX_TEMPR12_4_net,

        QBX_TEMPR12_5_net, QBX_TEMPR12_6_net, QBX_TEMPR12_7_net,

        QBX_TEMPR13_4_net, QBX_TEMPR13_5_net, QBX_TEMPR13_6_net,

        QBX_TEMPR13_7_net, QBX_TEMPR14_4_net, QBX_TEMPR14_5_net,

        QBX_TEMPR14_6_net, QBX_TEMPR14_7_net, QAX_TEMPR0_4_net,

        QAX_TEMPR0_5_net, QAX_TEMPR0_6_net, QAX_TEMPR0_7_net,

        QAX_TEMPR1_4_net, QAX_TEMPR1_5_net, QAX_TEMPR1_6_net,

        QAX_TEMPR1_7_net, QAX_TEMPR2_4_net, QAX_TEMPR2_5_net,

        QAX_TEMPR2_6_net, QAX_TEMPR2_7_net, QAX_TEMPR3_4_net,

        QAX_TEMPR3_5_net, QAX_TEMPR3_6_net, QAX_TEMPR3_7_net,

        QAX_TEMPR4_4_net, QAX_TEMPR4_5_net, QAX_TEMPR4_6_net,

        QAX_TEMPR4_7_net, QAX_TEMPR5_4_net, QAX_TEMPR5_5_net,

        QAX_TEMPR5_6_net, QAX_TEMPR5_7_net, QAX_TEMPR6_4_net,

        QAX_TEMPR6_5_net, QAX_TEMPR6_6_net, QAX_TEMPR6_7_net,

        QAX_TEMPR7_4_net, QAX_TEMPR7_5_net, QAX_TEMPR7_6_net,

        QAX_TEMPR7_7_net, QAX_TEMPR8_4_net, QAX_TEMPR8_5_net,

        QAX_TEMPR8_6_net, QAX_TEMPR8_7_net, QAX_TEMPR9_4_net,

        QAX_TEMPR9_5_net, QAX_TEMPR9_6_net, QAX_TEMPR9_7_net,

        QAX_TEMPR10_4_net, QAX_TEMPR10_5_net, QAX_TEMPR10_6_net,

        QAX_TEMPR10_7_net, QAX_TEMPR11_4_net, QAX_TEMPR11_5_net,

        QAX_TEMPR11_6_net, QAX_TEMPR11_7_net, QAX_TEMPR12_4_net,

        QAX_TEMPR12_5_net, QAX_TEMPR12_6_net, QAX_TEMPR12_7_net,

        QAX_TEMPR13_4_net, QAX_TEMPR13_5_net, QAX_TEMPR13_6_net,

        QAX_TEMPR13_7_net, QAX_TEMPR14_4_net, QAX_TEMPR14_5_net,

        QAX_TEMPR14_6_net, QAX_TEMPR14_7_net, QBX_TEMPR0_8_net,

        QBX_TEMPR0_9_net, QBX_TEMPR0_10_net, QBX_TEMPR0_11_net,

        QBX_TEMPR1_8_net, QBX_TEMPR1_9_net, QBX_TEMPR1_10_net,

        QBX_TEMPR1_11_net, QBX_TEMPR2_8_net, QBX_TEMPR2_9_net,

        QBX_TEMPR2_10_net, QBX_TEMPR2_11_net, QBX_TEMPR3_8_net,

        QBX_TEMPR3_9_net, QBX_TEMPR3_10_net, QBX_TEMPR3_11_net,

        QBX_TEMPR4_8_net, QBX_TEMPR4_9_net, QBX_TEMPR4_10_net,

        QBX_TEMPR4_11_net, QBX_TEMPR5_8_net, QBX_TEMPR5_9_net,

        QBX_TEMPR5_10_net, QBX_TEMPR5_11_net, QBX_TEMPR6_8_net,

        QBX_TEMPR6_9_net, QBX_TEMPR6_10_net, QBX_TEMPR6_11_net,

        QBX_TEMPR7_8_net, QBX_TEMPR7_9_net, QBX_TEMPR7_10_net,

        QBX_TEMPR7_11_net, QBX_TEMPR8_8_net, QBX_TEMPR8_9_net,

        QBX_TEMPR8_10_net, QBX_TEMPR8_11_net, QBX_TEMPR9_8_net,

        QBX_TEMPR9_9_net, QBX_TEMPR9_10_net, QBX_TEMPR9_11_net,

        QBX_TEMPR10_8_net, QBX_TEMPR10_9_net, QBX_TEMPR10_10_net,

        QBX_TEMPR10_11_net, QBX_TEMPR11_8_net, QBX_TEMPR11_9_net,

        QBX_TEMPR11_10_net, QBX_TEMPR11_11_net, QBX_TEMPR12_8_net,

        QBX_TEMPR12_9_net, QBX_TEMPR12_10_net, QBX_TEMPR12_11_net,

        QBX_TEMPR13_8_net, QBX_TEMPR13_9_net, QBX_TEMPR13_10_net,

        QBX_TEMPR13_11_net, QBX_TEMPR14_8_net, QBX_TEMPR14_9_net,

        QBX_TEMPR14_10_net, QBX_TEMPR14_11_net, QAX_TEMPR0_8_net,

        QAX_TEMPR0_9_net, QAX_TEMPR0_10_net, QAX_TEMPR0_11_net,

        QAX_TEMPR1_8_net, QAX_TEMPR1_9_net, QAX_TEMPR1_10_net,

        QAX_TEMPR1_11_net, QAX_TEMPR2_8_net, QAX_TEMPR2_9_net,

        QAX_TEMPR2_10_net, QAX_TEMPR2_11_net, QAX_TEMPR3_8_net,

        QAX_TEMPR3_9_net, QAX_TEMPR3_10_net, QAX_TEMPR3_11_net,

        QAX_TEMPR4_8_net, QAX_TEMPR4_9_net, QAX_TEMPR4_10_net,

        QAX_TEMPR4_11_net, QAX_TEMPR5_8_net, QAX_TEMPR5_9_net,

        QAX_TEMPR5_10_net, QAX_TEMPR5_11_net, QAX_TEMPR6_8_net,

        QAX_TEMPR6_9_net, QAX_TEMPR6_10_net, QAX_TEMPR6_11_net,

        QAX_TEMPR7_8_net, QAX_TEMPR7_9_net, QAX_TEMPR7_10_net,

        QAX_TEMPR7_11_net, QAX_TEMPR8_8_net, QAX_TEMPR8_9_net,

        QAX_TEMPR8_10_net, QAX_TEMPR8_11_net, QAX_TEMPR9_8_net,

        QAX_TEMPR9_9_net, QAX_TEMPR9_10_net, QAX_TEMPR9_11_net,

        QAX_TEMPR10_8_net, QAX_TEMPR10_9_net, QAX_TEMPR10_10_net,

        QAX_TEMPR10_11_net, QAX_TEMPR11_8_net, QAX_TEMPR11_9_net,

        QAX_TEMPR11_10_net, QAX_TEMPR11_11_net, QAX_TEMPR12_8_net,

        QAX_TEMPR12_9_net, QAX_TEMPR12_10_net, QAX_TEMPR12_11_net,

        QAX_TEMPR13_8_net, QAX_TEMPR13_9_net, QAX_TEMPR13_10_net,

        QAX_TEMPR13_11_net, QAX_TEMPR14_8_net, QAX_TEMPR14_9_net,

        QAX_TEMPR14_10_net, QAX_TEMPR14_11_net, QBX_TEMPR0_12_net,

        QBX_TEMPR0_13_net, QBX_TEMPR0_14_net, QBX_TEMPR0_15_net,

        QBX_TEMPR1_12_net, QBX_TEMPR1_13_net, QBX_TEMPR1_14_net,

        QBX_TEMPR1_15_net, QBX_TEMPR2_12_net, QBX_TEMPR2_13_net,

        QBX_TEMPR2_14_net, QBX_TEMPR2_15_net, QBX_TEMPR3_12_net,

        QBX_TEMPR3_13_net, QBX_TEMPR3_14_net, QBX_TEMPR3_15_net,

        QBX_TEMPR4_12_net, QBX_TEMPR4_13_net, QBX_TEMPR4_14_net,

        QBX_TEMPR4_15_net, QBX_TEMPR5_12_net, QBX_TEMPR5_13_net,

        QBX_TEMPR5_14_net, QBX_TEMPR5_15_net, QBX_TEMPR6_12_net,

        QBX_TEMPR6_13_net, QBX_TEMPR6_14_net, QBX_TEMPR6_15_net,

        QBX_TEMPR7_12_net, QBX_TEMPR7_13_net, QBX_TEMPR7_14_net,

        QBX_TEMPR7_15_net, QBX_TEMPR8_12_net, QBX_TEMPR8_13_net,

        QBX_TEMPR8_14_net, QBX_TEMPR8_15_net, QBX_TEMPR9_12_net,

        QBX_TEMPR9_13_net, QBX_TEMPR9_14_net, QBX_TEMPR9_15_net,

        QBX_TEMPR10_12_net, QBX_TEMPR10_13_net,

        QBX_TEMPR10_14_net, QBX_TEMPR10_15_net,

        QBX_TEMPR11_12_net, QBX_TEMPR11_13_net,

        QBX_TEMPR11_14_net, QBX_TEMPR11_15_net,

        QBX_TEMPR12_12_net, QBX_TEMPR12_13_net,

        QBX_TEMPR12_14_net, QBX_TEMPR12_15_net,

        QBX_TEMPR13_12_net, QBX_TEMPR13_13_net,

        QBX_TEMPR13_14_net, QBX_TEMPR13_15_net,

        QBX_TEMPR14_12_net, QBX_TEMPR14_13_net,

        QBX_TEMPR14_14_net, QBX_TEMPR14_15_net, QAX_TEMPR0_12_net,

        QAX_TEMPR0_13_net, QAX_TEMPR0_14_net, QAX_TEMPR0_15_net,

        QAX_TEMPR1_12_net, QAX_TEMPR1_13_net, QAX_TEMPR1_14_net,

        QAX_TEMPR1_15_net, QAX_TEMPR2_12_net, QAX_TEMPR2_13_net,

        QAX_TEMPR2_14_net, QAX_TEMPR2_15_net, QAX_TEMPR3_12_net,

        QAX_TEMPR3_13_net, QAX_TEMPR3_14_net, QAX_TEMPR3_15_net,

        QAX_TEMPR4_12_net, QAX_TEMPR4_13_net, QAX_TEMPR4_14_net,

        QAX_TEMPR4_15_net, QAX_TEMPR5_12_net, QAX_TEMPR5_13_net,

        QAX_TEMPR5_14_net, QAX_TEMPR5_15_net, QAX_TEMPR6_12_net,

        QAX_TEMPR6_13_net, QAX_TEMPR6_14_net, QAX_TEMPR6_15_net,

        QAX_TEMPR7_12_net, QAX_TEMPR7_13_net, QAX_TEMPR7_14_net,

        QAX_TEMPR7_15_net, QAX_TEMPR8_12_net, QAX_TEMPR8_13_net,

        QAX_TEMPR8_14_net, QAX_TEMPR8_15_net, QAX_TEMPR9_12_net,

        QAX_TEMPR9_13_net, QAX_TEMPR9_14_net, QAX_TEMPR9_15_net,

        QAX_TEMPR10_12_net, QAX_TEMPR10_13_net,

        QAX_TEMPR10_14_net, QAX_TEMPR10_15_net,

        QAX_TEMPR11_12_net, QAX_TEMPR11_13_net,

        QAX_TEMPR11_14_net, QAX_TEMPR11_15_net,

        QAX_TEMPR12_12_net, QAX_TEMPR12_13_net,

        QAX_TEMPR12_14_net, QAX_TEMPR12_15_net,

        QAX_TEMPR13_12_net, QAX_TEMPR13_13_net,

        QAX_TEMPR13_14_net, QAX_TEMPR13_15_net,

        QAX_TEMPR14_12_net, QAX_TEMPR14_13_net,

        QAX_TEMPR14_14_net, QAX_TEMPR14_15_net, BUFF_22_Y,

        BUFF_26_Y, BUFF_10_Y, BUFF_35_Y, BUFF_27_Y, MX2_117_Y,

        MX2_291_Y, MX2_82_Y, MX2_362_Y, MX2_351_Y, MX2_276_Y,

        MX2_90_Y, MX2_327_Y, MX2_36_Y, MX2_218_Y, MX2_118_Y,

        MX2_363_Y, MX2_22_Y, MX2_146_Y, MX2_301_Y, MX2_384_Y,

        MX2_371_Y, MX2_170_Y, MX2_101_Y, MX2_168_Y, MX2_216_Y,

        MX2_37_Y, MX2_86_Y, MX2_163_Y, MX2_243_Y, MX2_309_Y,

        MX2_317_Y, MX2_322_Y, MX2_110_Y, MX2_181_Y, MX2_271_Y,

        MX2_124_Y, MX2_231_Y, MX2_346_Y, MX2_178_Y, MX2_235_Y,

        MX2_98_Y, MX2_383_Y, MX2_40_Y, MX2_388_Y, MX2_305_Y,

        MX2_413_Y, MX2_365_Y, MX2_128_Y, MX2_17_Y, MX2_31_Y,

        MX2_237_Y, MX2_228_Y, MX2_132_Y, MX2_28_Y, MX2_268_Y,

        MX2_334_Y, BUFF_12_Y, BUFF_6_Y, BUFF_3_Y, BUFF_29_Y,

        BUFF_25_Y, MX2_134_Y, MX2_386_Y, MX2_249_Y, MX2_342_Y,

        MX2_254_Y, MX2_10_Y, MX2_66_Y, MX2_340_Y, MX2_355_Y,

        MX2_171_Y, MX2_201_Y, MX2_52_Y, MX2_325_Y, MX2_114_Y,

        MX2_250_Y, MX2_133_Y, MX2_12_Y, MX2_385_Y, MX2_255_Y,

        MX2_344_Y, MX2_222_Y, MX2_293_Y, MX2_32_Y, MX2_353_Y,

        MX2_329_Y, MX2_211_Y, MX2_230_Y, MX2_119_Y, MX2_273_Y,

        MX2_298_Y, MX2_205_Y, MX2_366_Y, MX2_277_Y, MX2_368_Y,

        MX2_292_Y, MX2_196_Y, MX2_64_Y, MX2_65_Y, MX2_349_Y,

        MX2_27_Y, MX2_4_Y, MX2_219_Y, MX2_415_Y, MX2_373_Y,

        MX2_315_Y, MX2_109_Y, MX2_313_Y, MX2_112_Y, MX2_137_Y,

        MX2_144_Y, MX2_20_Y, MX2_300_Y, NOR2_2_Y, AND2A_4_Y,

        AND2A_2_Y, AND2_2_Y, NOR2_3_Y, AND2A_5_Y, AND2A_3_Y,

        AND2_3_Y, BUFF_34_Y, BUFF_28_Y, BUFF_39_Y, BUFF_1_Y,

        BUFF_19_Y, MX2_100_Y, MX2_360_Y, MX2_227_Y, MX2_321_Y,

        MX2_233_Y, MX2_406_Y, MX2_57_Y, MX2_210_Y, MX2_331_Y,

        MX2_405_Y, MX2_176_Y, MX2_159_Y, MX2_198_Y, MX2_80_Y,

        MX2_229_Y, MX2_95_Y, MX2_407_Y, MX2_357_Y, MX2_234_Y,

        MX2_323_Y, MX2_69_Y, MX2_275_Y, MX2_279_Y, MX2_330_Y,

        MX2_19_Y, MX2_56_Y, MX2_215_Y, MX2_84_Y, MX2_252_Y,

        MX2_278_Y, MX2_194_Y, MX2_341_Y, MX2_257_Y, MX2_225_Y,

        MX2_272_Y, MX2_14_Y, MX2_49_Y, MX2_184_Y, MX2_212_Y,

        MX2_3_Y, MX2_401_Y, MX2_204_Y, MX2_393_Y, MX2_347_Y,

        MX2_299_Y, MX2_76_Y, MX2_188_Y, MX2_77_Y, MX2_372_Y,

        MX2_111_Y, MX2_116_Y, MX2_164_Y, BUFF_23_Y, BUFF_33_Y,

        BUFF_5_Y, BUFF_36_Y, BUFF_7_Y, MX2_283_Y, MX2_145_Y,

        MX2_411_Y, MX2_85_Y, MX2_0_Y, MX2_190_Y, MX2_236_Y,

        MX2_232_Y, MX2_103_Y, MX2_224_Y, MX2_336_Y, MX2_200_Y,

        MX2_157_Y, MX2_270_Y, MX2_414_Y, MX2_281_Y, MX2_191_Y,

        MX2_141_Y, MX2_1_Y, MX2_87_Y, MX2_104_Y, MX2_43_Y,

        MX2_89_Y, MX2_102_Y, MX2_58_Y, MX2_18_Y, MX2_395_Y,

        MX2_274_Y, MX2_21_Y, MX2_47_Y, MX2_352_Y, MX2_121_Y,

        MX2_23_Y, MX2_258_Y, MX2_41_Y, MX2_247_Y, MX2_226_Y,

        MX2_213_Y, MX2_182_Y, MX2_202_Y, MX2_180_Y, MX2_376_Y,

        MX2_173_Y, MX2_131_Y, MX2_61_Y, MX2_265_Y, MX2_208_Y,

        MX2_267_Y, MX2_203_Y, MX2_289_Y, MX2_165_Y, MX2_115_Y,

        BUFF_11_Y, BUFF_20_Y, BUFF_14_Y, BUFF_31_Y, BUFF_32_Y,

        MX2_140_Y, MX2_304_Y, MX2_107_Y, MX2_379_Y, MX2_370_Y,

        MX2_290_Y, MX2_122_Y, MX2_78_Y, MX2_53_Y, MX2_394_Y,

        MX2_142_Y, MX2_35_Y, MX2_263_Y, MX2_162_Y, MX2_314_Y,

        MX2_400_Y, MX2_392_Y, MX2_186_Y, MX2_129_Y, MX2_185_Y,

        MX2_380_Y, MX2_54_Y, MX2_266_Y, MX2_177_Y, MX2_320_Y,

        MX2_158_Y, MX2_333_Y, MX2_337_Y, MX2_138_Y, MX2_199_Y,

        MX2_288_Y, MX2_148_Y, MX2_248_Y, MX2_106_Y, MX2_197_Y,

        MX2_410_Y, MX2_127_Y, MX2_55_Y, MX2_282_Y, MX2_402_Y,

        MX2_319_Y, MX2_9_Y, MX2_387_Y, MX2_150_Y, MX2_33_Y,

        MX2_48_Y, MX2_409_Y, MX2_246_Y, MX2_295_Y, MX2_46_Y,

        MX2_350_Y, MX2_187_Y, BUFF_24_Y, BUFF_2_Y, BUFF_16_Y,

        BUFF_4_Y, BUFF_13_Y, MX2_256_Y, MX2_94_Y, MX2_381_Y,

        MX2_62_Y, MX2_390_Y, MX2_160_Y, MX2_214_Y, MX2_286_Y,

        MX2_68_Y, MX2_6_Y, MX2_311_Y, MX2_60_Y, MX2_302_Y,

        MX2_242_Y, MX2_382_Y, MX2_253_Y, MX2_161_Y, MX2_93_Y,

        MX2_391_Y, MX2_63_Y, MX2_175_Y, MX2_8_Y, MX2_297_Y,

        MX2_67_Y, MX2_339_Y, MX2_192_Y, MX2_359_Y, MX2_245_Y,

        MX2_404_Y, MX2_13_Y, MX2_324_Y, MX2_74_Y, MX2_408_Y,

        MX2_307_Y, MX2_7_Y, MX2_34_Y, MX2_206_Y, MX2_72_Y,

        MX2_318_Y, MX2_172_Y, MX2_152_Y, MX2_343_Y, MX2_143_Y,

        MX2_83_Y, MX2_38_Y, MX2_238_Y, MX2_259_Y, MX2_241_Y,

        MX2_396_Y, MX2_261_Y, MX2_30_Y, MX2_269_Y, NOR2_1_Y,

        AND2A_1_Y, AND2A_7_Y, AND2_1_Y, NOR2_0_Y, AND2A_0_Y,

        AND2A_6_Y, AND2_0_Y, BUFF_37_Y, BUFF_15_Y, BUFF_9_Y,

        BUFF_8_Y, BUFF_30_Y, MX2_91_Y, MX2_280_Y, MX2_70_Y,

        MX2_345_Y, MX2_335_Y, MX2_262_Y, MX2_75_Y, MX2_126_Y,

        MX2_24_Y, MX2_358_Y, MX2_92_Y, MX2_209_Y, MX2_294_Y,

        MX2_125_Y, MX2_287_Y, MX2_367_Y, MX2_356_Y, MX2_156_Y,

        MX2_81_Y, MX2_154_Y, MX2_412_Y, MX2_25_Y, MX2_239_Y,

        MX2_149_Y, MX2_71_Y, MX2_189_Y, MX2_306_Y, MX2_312_Y,

        MX2_88_Y, MX2_167_Y, MX2_260_Y, MX2_97_Y, MX2_220_Y,

        MX2_151_Y, MX2_166_Y, MX2_378_Y, MX2_79_Y, MX2_221_Y,

        MX2_308_Y, MX2_369_Y, MX2_296_Y, MX2_399_Y, MX2_348_Y,

        MX2_105_Y, MX2_2_Y, MX2_16_Y, MX2_26_Y, MX2_217_Y,

        MX2_264_Y, MX2_11_Y, MX2_108_Y, MX2_207_Y, BUFF_18_Y,

        BUFF_21_Y, BUFF_0_Y, BUFF_38_Y, BUFF_17_Y, MX2_135_Y,

        MX2_303_Y, MX2_99_Y, MX2_374_Y, MX2_364_Y, MX2_285_Y,

        MX2_113_Y, MX2_44_Y, MX2_50_Y, MX2_338_Y, MX2_136_Y,

        MX2_153_Y, MX2_73_Y, MX2_155_Y, MX2_310_Y, MX2_397_Y,

        MX2_389_Y, MX2_183_Y, MX2_123_Y, MX2_179_Y, MX2_326_Y,

        MX2_51_Y, MX2_223_Y, MX2_174_Y, MX2_15_Y, MX2_375_Y,

        MX2_328_Y, MX2_332_Y, MX2_130_Y, MX2_195_Y, MX2_284_Y,

        MX2_139_Y, MX2_244_Y, MX2_59_Y, MX2_193_Y, MX2_361_Y,

        MX2_120_Y, MX2_169_Y, MX2_96_Y, MX2_398_Y, MX2_316_Y,

        MX2_5_Y, MX2_377_Y, MX2_147_Y, MX2_29_Y, MX2_42_Y,

        MX2_354_Y, MX2_240_Y, MX2_251_Y, MX2_39_Y, MX2_45_Y,

        MX2_403_Y, VCC_1_net, GND_1_net : std_logic ;

    begin

    VCC_2_net : VCC port map(Y => VCC_1_net);

    GND_2_net : GND port map(Y => GND_1_net);

    BUFF_8 : BUFF

      port map(A => ADDRA_FF2_1_net, Y => BUFF_8_Y);

    dual_port_memory_R0C3 : RAM4K9

      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,

        ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>

        ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),

        ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>

        ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),

        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>

        ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),

        ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>

        ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),

        ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>

        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,

        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),

        DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),

        DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>

        GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,

        DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),

        DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>

        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,

        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>

        VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_0_net,

        BLKB => BLKB_EN_0_net, WENA => RWA, WENB => RWB, CLKA =>

        CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,

        DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,

        DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR0_15_net, DOUTA2 =>

        QAX_TEMPR0_14_net, DOUTA1 => QAX_TEMPR0_13_net, DOUTA0 =>

        QAX_TEMPR0_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,

        DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,

        DOUTB3 => QBX_TEMPR0_15_net, DOUTB2 => QBX_TEMPR0_14_net,

        DOUTB1 => QBX_TEMPR0_13_net, DOUTB0 => QBX_TEMPR0_12_net);

    ORB_GATE_11_inst : OR2

      port map(A => ENABLE_ADDRB_11_net, B => WEBP, Y =>

        BLKB_EN_11_net);

    MX2_113 : MX2

      port map(A => QAX_TEMPR6_3_net, B => QAX_TEMPR7_3_net, S =>

        BUFF_0_Y, Y => MX2_113_Y);

    MX2_279 : MX2

      port map(A => QBX_TEMPR10_10_net, B => QBX_TEMPR11_10_net,

        S => BUFF_39_Y, Y => MX2_279_Y);

    ORB_GATE_4_inst : OR2

      port map(A => ENABLE_ADDRB_4_net, B => WEBP, Y =>

        BLKB_EN_4_net);

    dual_port_memory_R9C0 : RAM4K9

      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,

        ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>

        ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),

        ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>

        ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),

        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>

        ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),

        ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>

        ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),

        ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>

        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,

        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),

        DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),

        DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>

        GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,

        DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),

        DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>

        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,

        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>

        VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_9_net,

        BLKB => BLKB_EN_9_net, WENA => RWA, WENB => RWB, CLKA =>

        CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,

        DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,

        DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR9_3_net, DOUTA2 =>

        QAX_TEMPR9_2_net, DOUTA1 => QAX_TEMPR9_1_net, DOUTA0 =>

        QAX_TEMPR9_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,

        DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,

        DOUTB3 => QBX_TEMPR9_3_net, DOUTB2 => QBX_TEMPR9_2_net,

        DOUTB1 => QBX_TEMPR9_1_net, DOUTB0 => QBX_TEMPR9_0_net);

    MX2_319 : MX2

      port map(A => QAX_TEMPR2_9_net, B => QAX_TEMPR3_9_net, S =>

        BUFF_11_Y, Y => MX2_319_Y);

    MX2_226 : MX2

      port map(A => MX2_41_Y, B => MX2_247_Y, S => BUFF_36_Y,

        Y => MX2_226_Y);

    MX2_304 : MX2

      port map(A => QAX_TEMPR2_11_net, B => QAX_TEMPR3_11_net,

        S => BUFF_14_Y, Y => MX2_304_Y);

    MX2_382 : MX2

      port map(A => QBX_TEMPR2_14_net, B => QBX_TEMPR3_14_net,

        S => BUFF_2_Y, Y => MX2_382_Y);

    MX2_183 : MX2

      port map(A => MX2_397_Y, B => MX2_389_Y, S =>

        ADDRA_FF2_2_net, Y => MX2_183_Y);

    dual_port_memory_R13C3 : RAM4K9

      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,

        ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>

        ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),

        ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>

        ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),

        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>

        ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),

        ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>

        ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),

        ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>

        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,

        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),

        DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),

        DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>

        GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,

        DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),

        DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>

        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,

        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>

        VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_13_net,

        BLKB => BLKB_EN_13_net, WENA => RWA, WENB => RWB, CLKA =>

        CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,

        DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,

        DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR13_15_net, DOUTA2 =>

        QAX_TEMPR13_14_net, DOUTA1 => QAX_TEMPR13_13_net,

        DOUTA0 => QAX_TEMPR13_12_net, DOUTB8 => OPEN , DOUTB7 =>

        OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,

        DOUTB3 => QBX_TEMPR13_15_net, DOUTB2 =>

        QBX_TEMPR13_14_net, DOUTB1 => QBX_TEMPR13_13_net,

        DOUTB0 => QBX_TEMPR13_12_net);

    dual_port_memory_R6C3 : RAM4K9

      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,

        ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>

        ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),

        ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>

        ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),

        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>

        ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),

        ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>

        ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),

        ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>

        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,

        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),

        DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),

        DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>

        GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,

        DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),

        DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>

        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,

        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>

        VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_6_net,

        BLKB => BLKB_EN_6_net, WENA => RWA, WENB => RWB, CLKA =>

        CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,

        DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,

        DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR6_15_net, DOUTA2 =>

        QAX_TEMPR6_14_net, DOUTA1 => QAX_TEMPR6_13_net, DOUTA0 =>

        QAX_TEMPR6_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,

        DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,

        DOUTB3 => QBX_TEMPR6_15_net, DOUTB2 => QBX_TEMPR6_14_net,

        DOUTB1 => QBX_TEMPR6_13_net, DOUTB0 => QBX_TEMPR6_12_net);

    MX2_389 : MX2

      port map(A => MX2_123_Y, B => MX2_179_Y, S => BUFF_17_Y,

        Y => MX2_389_Y);

    MX2_405 : MX2

      port map(A => QBX_TEMPR10_11_net, B => QBX_TEMPR11_11_net,

        S => BUFF_39_Y, Y => MX2_405_Y);

    MX2_377 : MX2

      port map(A => MX2_29_Y, B => MX2_42_Y, S => BUFF_38_Y, Y =>

        MX2_377_Y);

    BUFF_7 : BUFF

      port map(A => ADDRB_FF2_1_net, Y => BUFF_7_Y);

    MX2_273 : MX2

      port map(A => MX2_230_Y, B => MX2_119_Y, S => BUFF_29_Y,

        Y => MX2_273_Y);

    NAND2_ENABLE_ADDRA_7_inst : NAND2

      port map(A => AND2_2_Y, B => AND2A_5_Y, Y =>

        ENABLE_ADDRA_7_net);

    MX2_408 : MX2

      port map(A => QBX_TEMPR6_12_net, B => QBX_TEMPR7_12_net,

        S => BUFF_24_Y, Y => MX2_408_Y);

    MX2_124 : MX2

      port map(A => QAX_TEMPR4_4_net, B => QAX_TEMPR5_4_net, S =>

        BUFF_22_Y, Y => MX2_124_Y);

    MX2_89 : MX2

      port map(A => QBX_TEMPR10_2_net, B => QBX_TEMPR11_2_net,

        S => BUFF_5_Y, Y => MX2_89_Y);

    MX2_37 : MX2

      port map(A => QAX_TEMPR8_6_net, B => QAX_TEMPR9_6_net, S =>

        BUFF_26_Y, Y => MX2_37_Y);

    MX2_54 : MX2

      port map(A => QAX_TEMPR8_10_net, B => QAX_TEMPR9_10_net,

        S => BUFF_20_Y, Y => MX2_54_Y);

    MX2_328 : MX2

      port map(A => QAX_TEMPR0_0_net, B => QAX_TEMPR1_0_net, S =>

        BUFF_18_Y, Y => MX2_328_Y);

    MX2_75 : MX2

      port map(A => QAX_TEMPR6_15_net, B => QAX_TEMPR7_15_net,

        S => BUFF_9_Y, Y => MX2_75_Y);

    dual_port_memory_R3C1 : RAM4K9

      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,

        ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>

        ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),

        ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>

        ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),

        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>

        ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),

        ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>

        ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),

        ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>

        GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,

        DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),

        DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),

        DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>

        GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,

        DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),

        DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>

        VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,

        PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>

        VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_3_net,

        BLKB => BLKB_EN_3_net, WENA => RWA, WENB => RWB, CLKA =>

        CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,

        DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,

        DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR3_7_net, DOUTA2 =>

        QAX_TEMPR3_6_net, DOUTA1 => QAX_TEMPR3_5_net, DOUTA0 =>

        QAX_TEMPR3_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,

        DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,

        DOUTB3 => QBX_TEMPR3_7_net, DOUTB2 => QBX_TEMPR3_6_net,

        DOUTB1 => QBX_TEMPR3_5_net, DOUTB0 => QBX_TEMPR3_4_net);

    MX2_23 : MX2

      port map(A => QBX_TEMPR6_0_net, B => QBX_TEMPR7_0_net, S =>

        BUFF_23_Y, Y => MX2_23_Y);

    MX2_112 : MX2

      port map(A => QBX_TEMPR8_5_net, B => QBX_TEMPR9_5_net, S =>

        BUFF_6_Y, Y => MX2_112_Y);

    MX2_323 : MX2

      port map(A => QBX_TEMPR6_10_net, B => QBX_TEMPR7_10_net,

        S => BUFF_28_Y, Y => MX2_323_Y);

    MX2_296 : MX2

      port map(A => QAX_TEMPR2_13_net, B => QAX_TEMPR3_13_net,

        S => BUFF_37_Y, Y => MX2_296_Y);

    MX2_94 : MX2

      port map(A => QBX_TEMPR2_15_net, B => QBX_TEMPR3_15_net,

        S => BUFF_16_Y, Y => MX2_94_Y);

    MX2_65 : MX2

      port map(A => MX2_349_Y, B => QBX_TEMPR14_4_net, S =>

        BUFF_29_Y, Y => MX2_65_Y);

    AFF1_0_inst : DFN1

      port map(D => ADDRA(10), CLK => CLKA, Q => ADDRA_FF2_0_net);

    MX2_1 : MX2

      port map(A => QBX_TEMPR4_2_net, B => QBX_TEMPR5_2_net, S =>

        BUFF_33_Y, Y => MX2_1_Y);

    MX2_364 : MX2

      port map(A => MX2_99_Y, B => MX2_374_Y, S =>

        ADDRA_FF2_2_net, Y => MX2_364_Y);

    MX2_182 : MX2

      port map(A => QBX_TEMPR12_0_net, B => QBX_TEMPR13_0_net,

        S => BUFF_23_Y, Y => MX2_182_Y);

    MX2_414 : MX2

      port map(A => QBX_TEMPR2_2_net, B => QBX_TEMPR3_2_net, S =>

        BUFF_33_Y, Y => MX2_414_Y);

    MX2_278 : MX2

      port map(A => MX2_341_Y, B => MX2_257_Y, S => BUFF_1_Y,

        Y => MX2_278_Y);

    MX2_251 : MX2

      port map(A => QAX_TEMPR10_1_net, B => QAX_TEMPR11_1_net,

        S => BUFF_21_Y, Y => MX2_251_Y);

    MX2_257 : MX2

      port map(A => QBX_TEMPR6_8_net, B => QBX_TEMPR7_8_net, S =>

        BUFF_34_Y, Y => MX2_257_Y);

    BUFF_12 : BUFF

      port map(A => ADDRB_FF2_0_net, Y => BUFF_12_Y);

    MX2_176 : MX2

      port map(A => MX2_331_Y, B => MX2_405_Y, S => BUFF_19_Y,

        Y => MX2_176_Y);

    dual_port_memory_R7C2 : RAM4K9

      port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,

        ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>

        ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),

        ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>

        ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),

        ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>

        ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),

        ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>

        ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),