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----------------------------------------------------------------------------------------------------
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--| Modular Oscilloscope
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--| UNSL - Argentine
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--|
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--| File: dual_port_memory.vhd
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--| Version: 0.1
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--| Tested in: Actel A3PE1500
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--|-------------------------------------------------------------------------------------------------
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--| Description:
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--| MEMORY - Dual Port Memory
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--| Generated with Actel SmartGen tool. It will not work with other Actel FPGA than A3PE1500
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--| or similar.
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--|-------------------------------------------------------------------------------------------------
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--| File history:
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--| 0.10 | jan-2009 | First release
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----------------------------------------------------------------------------------------------------
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-- Libero Project Manager Version: 8.5 SP1 8.5.1.13
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-- Copyright 1989-2009 Actel Corporation
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-- · Parámetros
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---- Generales
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-- Reset: Not inverted
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-- Double clock
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-- High Speed
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---- Both ports
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-- Depth: 15360
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-- Width: 16
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-- BLKx: Not Inverted
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-- CLKA: Rising
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-- Pipeline: no
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-- DOUT type: DINA0
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-- Version: 8.5 8.5.0.34
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library ieee;
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use ieee.std_logic_1164.all;
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library proasic3e;
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use proasic3e.all;
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entity dual_port_memory is
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port(
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DINA: in std_logic_vector(15 downto 0);
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DOUTA: out std_logic_vector(15 downto 0);
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ADDRA: in std_logic_vector(13 downto 0); -- Only available until 15360
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RWA: in std_logic; -- '1' Read, '0' Write
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BLKA: in std_logic; -- '1' Block select
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CLKA: in std_logic; -- Rising edge
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DINB: in std_logic_vector(15 downto 0);
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DOUTB: out std_logic_vector(15 downto 0);
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ADDRB: in std_logic_vector(13 downto 0);
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RWB: in std_logic;
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BLKB: in std_logic;
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CLKB: in std_logic;
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RESET: in std_logic -- '1' Reset
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) ;
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end dual_port_memory;
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architecture DEF_ARCH of dual_port_memory is
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component BUFF
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port(A : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component RAM4K9
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generic (MEMORYFILE:string := "");
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port(ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
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ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11,
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ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4,
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ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6,
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DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7,
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DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0,
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WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB,
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BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic :=
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'U'; DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3,
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DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5,
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DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic) ;
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end component;
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component OR2
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port(A, B : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component MX2
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port(A, B, S : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component NAND2
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port(A, B : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component DFN1
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port(D, CLK : in std_logic := 'U'; Q : out std_logic) ;
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end component;
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component INV
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port(A : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component AND2A
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port(A, B : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component NOR2
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port(A, B : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component AND2
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port(A, B : in std_logic := 'U'; Y : out std_logic) ;
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end component;
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component VCC
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port( Y : out std_logic);
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end component;
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component GND
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port( Y : out std_logic);
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end component;
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signal WEAP, WEBP, RESETP, ADDRA_FF2_0_net, ADDRA_FF2_1_net,
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ADDRA_FF2_2_net, ADDRA_FF2_3_net, ADDRB_FF2_0_net,
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ADDRB_FF2_1_net, ADDRB_FF2_2_net, ADDRB_FF2_3_net,
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ENABLE_ADDRA_0_net, ENABLE_ADDRA_1_net,
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ENABLE_ADDRA_2_net, ENABLE_ADDRA_3_net,
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ENABLE_ADDRA_4_net, ENABLE_ADDRA_5_net,
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ENABLE_ADDRA_6_net, ENABLE_ADDRA_7_net,
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ENABLE_ADDRA_8_net, ENABLE_ADDRA_9_net,
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ENABLE_ADDRA_10_net, ENABLE_ADDRA_11_net,
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ENABLE_ADDRA_12_net, ENABLE_ADDRA_13_net,
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ENABLE_ADDRA_14_net, ENABLE_ADDRB_0_net,
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ENABLE_ADDRB_1_net, ENABLE_ADDRB_2_net,
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ENABLE_ADDRB_3_net, ENABLE_ADDRB_4_net,
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ENABLE_ADDRB_5_net, ENABLE_ADDRB_6_net,
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ENABLE_ADDRB_7_net, ENABLE_ADDRB_8_net,
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ENABLE_ADDRB_9_net, ENABLE_ADDRB_10_net,
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ENABLE_ADDRB_11_net, ENABLE_ADDRB_12_net,
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ENABLE_ADDRB_13_net, ENABLE_ADDRB_14_net, BLKA_EN_0_net,
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BLKB_EN_0_net, BLKA_EN_1_net, BLKB_EN_1_net,
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BLKA_EN_2_net, BLKB_EN_2_net, BLKA_EN_3_net,
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BLKB_EN_3_net, BLKA_EN_4_net, BLKB_EN_4_net,
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BLKA_EN_5_net, BLKB_EN_5_net, BLKA_EN_6_net,
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BLKB_EN_6_net, BLKA_EN_7_net, BLKB_EN_7_net,
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BLKA_EN_8_net, BLKB_EN_8_net, BLKA_EN_9_net,
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BLKB_EN_9_net, BLKA_EN_10_net, BLKB_EN_10_net,
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BLKA_EN_11_net, BLKB_EN_11_net, BLKA_EN_12_net,
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BLKB_EN_12_net, BLKA_EN_13_net, BLKB_EN_13_net,
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BLKA_EN_14_net, BLKB_EN_14_net, QBX_TEMPR0_0_net,
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QBX_TEMPR0_1_net, QBX_TEMPR0_2_net, QBX_TEMPR0_3_net,
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| 157 |
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QBX_TEMPR1_0_net, QBX_TEMPR1_1_net, QBX_TEMPR1_2_net,
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QBX_TEMPR1_3_net, QBX_TEMPR2_0_net, QBX_TEMPR2_1_net,
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| 159 |
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QBX_TEMPR2_2_net, QBX_TEMPR2_3_net, QBX_TEMPR3_0_net,
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QBX_TEMPR3_1_net, QBX_TEMPR3_2_net, QBX_TEMPR3_3_net,
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QBX_TEMPR4_0_net, QBX_TEMPR4_1_net, QBX_TEMPR4_2_net,
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| 162 |
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QBX_TEMPR4_3_net, QBX_TEMPR5_0_net, QBX_TEMPR5_1_net,
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QBX_TEMPR5_2_net, QBX_TEMPR5_3_net, QBX_TEMPR6_0_net,
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| 164 |
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QBX_TEMPR6_1_net, QBX_TEMPR6_2_net, QBX_TEMPR6_3_net,
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| 165 |
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QBX_TEMPR7_0_net, QBX_TEMPR7_1_net, QBX_TEMPR7_2_net,
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| 166 |
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QBX_TEMPR7_3_net, QBX_TEMPR8_0_net, QBX_TEMPR8_1_net,
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QBX_TEMPR8_2_net, QBX_TEMPR8_3_net, QBX_TEMPR9_0_net,
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| 168 |
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QBX_TEMPR9_1_net, QBX_TEMPR9_2_net, QBX_TEMPR9_3_net,
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| 169 |
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QBX_TEMPR10_0_net, QBX_TEMPR10_1_net, QBX_TEMPR10_2_net,
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| 170 |
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QBX_TEMPR10_3_net, QBX_TEMPR11_0_net, QBX_TEMPR11_1_net,
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| 171 |
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QBX_TEMPR11_2_net, QBX_TEMPR11_3_net, QBX_TEMPR12_0_net,
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| 172 |
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QBX_TEMPR12_1_net, QBX_TEMPR12_2_net, QBX_TEMPR12_3_net,
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| 173 |
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QBX_TEMPR13_0_net, QBX_TEMPR13_1_net, QBX_TEMPR13_2_net,
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| 174 |
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QBX_TEMPR13_3_net, QBX_TEMPR14_0_net, QBX_TEMPR14_1_net,
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QBX_TEMPR14_2_net, QBX_TEMPR14_3_net, QAX_TEMPR0_0_net,
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QAX_TEMPR0_1_net, QAX_TEMPR0_2_net, QAX_TEMPR0_3_net,
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QAX_TEMPR1_0_net, QAX_TEMPR1_1_net, QAX_TEMPR1_2_net,
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QAX_TEMPR1_3_net, QAX_TEMPR2_0_net, QAX_TEMPR2_1_net,
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| 179 |
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QAX_TEMPR2_2_net, QAX_TEMPR2_3_net, QAX_TEMPR3_0_net,
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| 180 |
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QAX_TEMPR3_1_net, QAX_TEMPR3_2_net, QAX_TEMPR3_3_net,
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| 181 |
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QAX_TEMPR4_0_net, QAX_TEMPR4_1_net, QAX_TEMPR4_2_net,
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| 182 |
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QAX_TEMPR4_3_net, QAX_TEMPR5_0_net, QAX_TEMPR5_1_net,
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QAX_TEMPR5_2_net, QAX_TEMPR5_3_net, QAX_TEMPR6_0_net,
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| 184 |
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QAX_TEMPR6_1_net, QAX_TEMPR6_2_net, QAX_TEMPR6_3_net,
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| 185 |
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QAX_TEMPR7_0_net, QAX_TEMPR7_1_net, QAX_TEMPR7_2_net,
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| 186 |
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QAX_TEMPR7_3_net, QAX_TEMPR8_0_net, QAX_TEMPR8_1_net,
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| 187 |
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QAX_TEMPR8_2_net, QAX_TEMPR8_3_net, QAX_TEMPR9_0_net,
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| 188 |
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QAX_TEMPR9_1_net, QAX_TEMPR9_2_net, QAX_TEMPR9_3_net,
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| 189 |
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QAX_TEMPR10_0_net, QAX_TEMPR10_1_net, QAX_TEMPR10_2_net,
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| 190 |
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QAX_TEMPR10_3_net, QAX_TEMPR11_0_net, QAX_TEMPR11_1_net,
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| 191 |
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QAX_TEMPR11_2_net, QAX_TEMPR11_3_net, QAX_TEMPR12_0_net,
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| 192 |
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QAX_TEMPR12_1_net, QAX_TEMPR12_2_net, QAX_TEMPR12_3_net,
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| 193 |
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QAX_TEMPR13_0_net, QAX_TEMPR13_1_net, QAX_TEMPR13_2_net,
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| 194 |
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QAX_TEMPR13_3_net, QAX_TEMPR14_0_net, QAX_TEMPR14_1_net,
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| 195 |
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QAX_TEMPR14_2_net, QAX_TEMPR14_3_net, QBX_TEMPR0_4_net,
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| 196 |
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QBX_TEMPR0_5_net, QBX_TEMPR0_6_net, QBX_TEMPR0_7_net,
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| 197 |
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QBX_TEMPR1_4_net, QBX_TEMPR1_5_net, QBX_TEMPR1_6_net,
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| 198 |
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QBX_TEMPR1_7_net, QBX_TEMPR2_4_net, QBX_TEMPR2_5_net,
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| 199 |
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QBX_TEMPR2_6_net, QBX_TEMPR2_7_net, QBX_TEMPR3_4_net,
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| 200 |
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QBX_TEMPR3_5_net, QBX_TEMPR3_6_net, QBX_TEMPR3_7_net,
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| 201 |
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QBX_TEMPR4_4_net, QBX_TEMPR4_5_net, QBX_TEMPR4_6_net,
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| 202 |
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QBX_TEMPR4_7_net, QBX_TEMPR5_4_net, QBX_TEMPR5_5_net,
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| 203 |
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QBX_TEMPR5_6_net, QBX_TEMPR5_7_net, QBX_TEMPR6_4_net,
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| 204 |
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QBX_TEMPR6_5_net, QBX_TEMPR6_6_net, QBX_TEMPR6_7_net,
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| 205 |
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QBX_TEMPR7_4_net, QBX_TEMPR7_5_net, QBX_TEMPR7_6_net,
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| 206 |
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QBX_TEMPR7_7_net, QBX_TEMPR8_4_net, QBX_TEMPR8_5_net,
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| 207 |
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QBX_TEMPR8_6_net, QBX_TEMPR8_7_net, QBX_TEMPR9_4_net,
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| 208 |
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QBX_TEMPR9_5_net, QBX_TEMPR9_6_net, QBX_TEMPR9_7_net,
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| 209 |
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QBX_TEMPR10_4_net, QBX_TEMPR10_5_net, QBX_TEMPR10_6_net,
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| 210 |
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QBX_TEMPR10_7_net, QBX_TEMPR11_4_net, QBX_TEMPR11_5_net,
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| 211 |
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QBX_TEMPR11_6_net, QBX_TEMPR11_7_net, QBX_TEMPR12_4_net,
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| 212 |
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QBX_TEMPR12_5_net, QBX_TEMPR12_6_net, QBX_TEMPR12_7_net,
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| 213 |
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QBX_TEMPR13_4_net, QBX_TEMPR13_5_net, QBX_TEMPR13_6_net,
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| 214 |
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QBX_TEMPR13_7_net, QBX_TEMPR14_4_net, QBX_TEMPR14_5_net,
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| 215 |
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QBX_TEMPR14_6_net, QBX_TEMPR14_7_net, QAX_TEMPR0_4_net,
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| 216 |
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QAX_TEMPR0_5_net, QAX_TEMPR0_6_net, QAX_TEMPR0_7_net,
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| 217 |
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QAX_TEMPR1_4_net, QAX_TEMPR1_5_net, QAX_TEMPR1_6_net,
|
| 218 |
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QAX_TEMPR1_7_net, QAX_TEMPR2_4_net, QAX_TEMPR2_5_net,
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| 219 |
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QAX_TEMPR2_6_net, QAX_TEMPR2_7_net, QAX_TEMPR3_4_net,
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| 220 |
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QAX_TEMPR3_5_net, QAX_TEMPR3_6_net, QAX_TEMPR3_7_net,
|
| 221 |
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QAX_TEMPR4_4_net, QAX_TEMPR4_5_net, QAX_TEMPR4_6_net,
|
| 222 |
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QAX_TEMPR4_7_net, QAX_TEMPR5_4_net, QAX_TEMPR5_5_net,
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| 223 |
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QAX_TEMPR5_6_net, QAX_TEMPR5_7_net, QAX_TEMPR6_4_net,
|
| 224 |
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QAX_TEMPR6_5_net, QAX_TEMPR6_6_net, QAX_TEMPR6_7_net,
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| 225 |
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QAX_TEMPR7_4_net, QAX_TEMPR7_5_net, QAX_TEMPR7_6_net,
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| 226 |
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QAX_TEMPR7_7_net, QAX_TEMPR8_4_net, QAX_TEMPR8_5_net,
|
| 227 |
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QAX_TEMPR8_6_net, QAX_TEMPR8_7_net, QAX_TEMPR9_4_net,
|
| 228 |
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QAX_TEMPR9_5_net, QAX_TEMPR9_6_net, QAX_TEMPR9_7_net,
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| 229 |
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QAX_TEMPR10_4_net, QAX_TEMPR10_5_net, QAX_TEMPR10_6_net,
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| 230 |
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QAX_TEMPR10_7_net, QAX_TEMPR11_4_net, QAX_TEMPR11_5_net,
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| 231 |
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QAX_TEMPR11_6_net, QAX_TEMPR11_7_net, QAX_TEMPR12_4_net,
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| 232 |
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QAX_TEMPR12_5_net, QAX_TEMPR12_6_net, QAX_TEMPR12_7_net,
|
| 233 |
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QAX_TEMPR13_4_net, QAX_TEMPR13_5_net, QAX_TEMPR13_6_net,
|
| 234 |
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QAX_TEMPR13_7_net, QAX_TEMPR14_4_net, QAX_TEMPR14_5_net,
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| 235 |
|
|
QAX_TEMPR14_6_net, QAX_TEMPR14_7_net, QBX_TEMPR0_8_net,
|
| 236 |
|
|
QBX_TEMPR0_9_net, QBX_TEMPR0_10_net, QBX_TEMPR0_11_net,
|
| 237 |
|
|
QBX_TEMPR1_8_net, QBX_TEMPR1_9_net, QBX_TEMPR1_10_net,
|
| 238 |
|
|
QBX_TEMPR1_11_net, QBX_TEMPR2_8_net, QBX_TEMPR2_9_net,
|
| 239 |
|
|
QBX_TEMPR2_10_net, QBX_TEMPR2_11_net, QBX_TEMPR3_8_net,
|
| 240 |
|
|
QBX_TEMPR3_9_net, QBX_TEMPR3_10_net, QBX_TEMPR3_11_net,
|
| 241 |
|
|
QBX_TEMPR4_8_net, QBX_TEMPR4_9_net, QBX_TEMPR4_10_net,
|
| 242 |
|
|
QBX_TEMPR4_11_net, QBX_TEMPR5_8_net, QBX_TEMPR5_9_net,
|
| 243 |
|
|
QBX_TEMPR5_10_net, QBX_TEMPR5_11_net, QBX_TEMPR6_8_net,
|
| 244 |
|
|
QBX_TEMPR6_9_net, QBX_TEMPR6_10_net, QBX_TEMPR6_11_net,
|
| 245 |
|
|
QBX_TEMPR7_8_net, QBX_TEMPR7_9_net, QBX_TEMPR7_10_net,
|
| 246 |
|
|
QBX_TEMPR7_11_net, QBX_TEMPR8_8_net, QBX_TEMPR8_9_net,
|
| 247 |
|
|
QBX_TEMPR8_10_net, QBX_TEMPR8_11_net, QBX_TEMPR9_8_net,
|
| 248 |
|
|
QBX_TEMPR9_9_net, QBX_TEMPR9_10_net, QBX_TEMPR9_11_net,
|
| 249 |
|
|
QBX_TEMPR10_8_net, QBX_TEMPR10_9_net, QBX_TEMPR10_10_net,
|
| 250 |
|
|
QBX_TEMPR10_11_net, QBX_TEMPR11_8_net, QBX_TEMPR11_9_net,
|
| 251 |
|
|
QBX_TEMPR11_10_net, QBX_TEMPR11_11_net, QBX_TEMPR12_8_net,
|
| 252 |
|
|
QBX_TEMPR12_9_net, QBX_TEMPR12_10_net, QBX_TEMPR12_11_net,
|
| 253 |
|
|
QBX_TEMPR13_8_net, QBX_TEMPR13_9_net, QBX_TEMPR13_10_net,
|
| 254 |
|
|
QBX_TEMPR13_11_net, QBX_TEMPR14_8_net, QBX_TEMPR14_9_net,
|
| 255 |
|
|
QBX_TEMPR14_10_net, QBX_TEMPR14_11_net, QAX_TEMPR0_8_net,
|
| 256 |
|
|
QAX_TEMPR0_9_net, QAX_TEMPR0_10_net, QAX_TEMPR0_11_net,
|
| 257 |
|
|
QAX_TEMPR1_8_net, QAX_TEMPR1_9_net, QAX_TEMPR1_10_net,
|
| 258 |
|
|
QAX_TEMPR1_11_net, QAX_TEMPR2_8_net, QAX_TEMPR2_9_net,
|
| 259 |
|
|
QAX_TEMPR2_10_net, QAX_TEMPR2_11_net, QAX_TEMPR3_8_net,
|
| 260 |
|
|
QAX_TEMPR3_9_net, QAX_TEMPR3_10_net, QAX_TEMPR3_11_net,
|
| 261 |
|
|
QAX_TEMPR4_8_net, QAX_TEMPR4_9_net, QAX_TEMPR4_10_net,
|
| 262 |
|
|
QAX_TEMPR4_11_net, QAX_TEMPR5_8_net, QAX_TEMPR5_9_net,
|
| 263 |
|
|
QAX_TEMPR5_10_net, QAX_TEMPR5_11_net, QAX_TEMPR6_8_net,
|
| 264 |
|
|
QAX_TEMPR6_9_net, QAX_TEMPR6_10_net, QAX_TEMPR6_11_net,
|
| 265 |
|
|
QAX_TEMPR7_8_net, QAX_TEMPR7_9_net, QAX_TEMPR7_10_net,
|
| 266 |
|
|
QAX_TEMPR7_11_net, QAX_TEMPR8_8_net, QAX_TEMPR8_9_net,
|
| 267 |
|
|
QAX_TEMPR8_10_net, QAX_TEMPR8_11_net, QAX_TEMPR9_8_net,
|
| 268 |
|
|
QAX_TEMPR9_9_net, QAX_TEMPR9_10_net, QAX_TEMPR9_11_net,
|
| 269 |
|
|
QAX_TEMPR10_8_net, QAX_TEMPR10_9_net, QAX_TEMPR10_10_net,
|
| 270 |
|
|
QAX_TEMPR10_11_net, QAX_TEMPR11_8_net, QAX_TEMPR11_9_net,
|
| 271 |
|
|
QAX_TEMPR11_10_net, QAX_TEMPR11_11_net, QAX_TEMPR12_8_net,
|
| 272 |
|
|
QAX_TEMPR12_9_net, QAX_TEMPR12_10_net, QAX_TEMPR12_11_net,
|
| 273 |
|
|
QAX_TEMPR13_8_net, QAX_TEMPR13_9_net, QAX_TEMPR13_10_net,
|
| 274 |
|
|
QAX_TEMPR13_11_net, QAX_TEMPR14_8_net, QAX_TEMPR14_9_net,
|
| 275 |
|
|
QAX_TEMPR14_10_net, QAX_TEMPR14_11_net, QBX_TEMPR0_12_net,
|
| 276 |
|
|
QBX_TEMPR0_13_net, QBX_TEMPR0_14_net, QBX_TEMPR0_15_net,
|
| 277 |
|
|
QBX_TEMPR1_12_net, QBX_TEMPR1_13_net, QBX_TEMPR1_14_net,
|
| 278 |
|
|
QBX_TEMPR1_15_net, QBX_TEMPR2_12_net, QBX_TEMPR2_13_net,
|
| 279 |
|
|
QBX_TEMPR2_14_net, QBX_TEMPR2_15_net, QBX_TEMPR3_12_net,
|
| 280 |
|
|
QBX_TEMPR3_13_net, QBX_TEMPR3_14_net, QBX_TEMPR3_15_net,
|
| 281 |
|
|
QBX_TEMPR4_12_net, QBX_TEMPR4_13_net, QBX_TEMPR4_14_net,
|
| 282 |
|
|
QBX_TEMPR4_15_net, QBX_TEMPR5_12_net, QBX_TEMPR5_13_net,
|
| 283 |
|
|
QBX_TEMPR5_14_net, QBX_TEMPR5_15_net, QBX_TEMPR6_12_net,
|
| 284 |
|
|
QBX_TEMPR6_13_net, QBX_TEMPR6_14_net, QBX_TEMPR6_15_net,
|
| 285 |
|
|
QBX_TEMPR7_12_net, QBX_TEMPR7_13_net, QBX_TEMPR7_14_net,
|
| 286 |
|
|
QBX_TEMPR7_15_net, QBX_TEMPR8_12_net, QBX_TEMPR8_13_net,
|
| 287 |
|
|
QBX_TEMPR8_14_net, QBX_TEMPR8_15_net, QBX_TEMPR9_12_net,
|
| 288 |
|
|
QBX_TEMPR9_13_net, QBX_TEMPR9_14_net, QBX_TEMPR9_15_net,
|
| 289 |
|
|
QBX_TEMPR10_12_net, QBX_TEMPR10_13_net,
|
| 290 |
|
|
QBX_TEMPR10_14_net, QBX_TEMPR10_15_net,
|
| 291 |
|
|
QBX_TEMPR11_12_net, QBX_TEMPR11_13_net,
|
| 292 |
|
|
QBX_TEMPR11_14_net, QBX_TEMPR11_15_net,
|
| 293 |
|
|
QBX_TEMPR12_12_net, QBX_TEMPR12_13_net,
|
| 294 |
|
|
QBX_TEMPR12_14_net, QBX_TEMPR12_15_net,
|
| 295 |
|
|
QBX_TEMPR13_12_net, QBX_TEMPR13_13_net,
|
| 296 |
|
|
QBX_TEMPR13_14_net, QBX_TEMPR13_15_net,
|
| 297 |
|
|
QBX_TEMPR14_12_net, QBX_TEMPR14_13_net,
|
| 298 |
|
|
QBX_TEMPR14_14_net, QBX_TEMPR14_15_net, QAX_TEMPR0_12_net,
|
| 299 |
|
|
QAX_TEMPR0_13_net, QAX_TEMPR0_14_net, QAX_TEMPR0_15_net,
|
| 300 |
|
|
QAX_TEMPR1_12_net, QAX_TEMPR1_13_net, QAX_TEMPR1_14_net,
|
| 301 |
|
|
QAX_TEMPR1_15_net, QAX_TEMPR2_12_net, QAX_TEMPR2_13_net,
|
| 302 |
|
|
QAX_TEMPR2_14_net, QAX_TEMPR2_15_net, QAX_TEMPR3_12_net,
|
| 303 |
|
|
QAX_TEMPR3_13_net, QAX_TEMPR3_14_net, QAX_TEMPR3_15_net,
|
| 304 |
|
|
QAX_TEMPR4_12_net, QAX_TEMPR4_13_net, QAX_TEMPR4_14_net,
|
| 305 |
|
|
QAX_TEMPR4_15_net, QAX_TEMPR5_12_net, QAX_TEMPR5_13_net,
|
| 306 |
|
|
QAX_TEMPR5_14_net, QAX_TEMPR5_15_net, QAX_TEMPR6_12_net,
|
| 307 |
|
|
QAX_TEMPR6_13_net, QAX_TEMPR6_14_net, QAX_TEMPR6_15_net,
|
| 308 |
|
|
QAX_TEMPR7_12_net, QAX_TEMPR7_13_net, QAX_TEMPR7_14_net,
|
| 309 |
|
|
QAX_TEMPR7_15_net, QAX_TEMPR8_12_net, QAX_TEMPR8_13_net,
|
| 310 |
|
|
QAX_TEMPR8_14_net, QAX_TEMPR8_15_net, QAX_TEMPR9_12_net,
|
| 311 |
|
|
QAX_TEMPR9_13_net, QAX_TEMPR9_14_net, QAX_TEMPR9_15_net,
|
| 312 |
|
|
QAX_TEMPR10_12_net, QAX_TEMPR10_13_net,
|
| 313 |
|
|
QAX_TEMPR10_14_net, QAX_TEMPR10_15_net,
|
| 314 |
|
|
QAX_TEMPR11_12_net, QAX_TEMPR11_13_net,
|
| 315 |
|
|
QAX_TEMPR11_14_net, QAX_TEMPR11_15_net,
|
| 316 |
|
|
QAX_TEMPR12_12_net, QAX_TEMPR12_13_net,
|
| 317 |
|
|
QAX_TEMPR12_14_net, QAX_TEMPR12_15_net,
|
| 318 |
|
|
QAX_TEMPR13_12_net, QAX_TEMPR13_13_net,
|
| 319 |
|
|
QAX_TEMPR13_14_net, QAX_TEMPR13_15_net,
|
| 320 |
|
|
QAX_TEMPR14_12_net, QAX_TEMPR14_13_net,
|
| 321 |
|
|
QAX_TEMPR14_14_net, QAX_TEMPR14_15_net, BUFF_22_Y,
|
| 322 |
|
|
BUFF_26_Y, BUFF_10_Y, BUFF_35_Y, BUFF_27_Y, MX2_117_Y,
|
| 323 |
|
|
MX2_291_Y, MX2_82_Y, MX2_362_Y, MX2_351_Y, MX2_276_Y,
|
| 324 |
|
|
MX2_90_Y, MX2_327_Y, MX2_36_Y, MX2_218_Y, MX2_118_Y,
|
| 325 |
|
|
MX2_363_Y, MX2_22_Y, MX2_146_Y, MX2_301_Y, MX2_384_Y,
|
| 326 |
|
|
MX2_371_Y, MX2_170_Y, MX2_101_Y, MX2_168_Y, MX2_216_Y,
|
| 327 |
|
|
MX2_37_Y, MX2_86_Y, MX2_163_Y, MX2_243_Y, MX2_309_Y,
|
| 328 |
|
|
MX2_317_Y, MX2_322_Y, MX2_110_Y, MX2_181_Y, MX2_271_Y,
|
| 329 |
|
|
MX2_124_Y, MX2_231_Y, MX2_346_Y, MX2_178_Y, MX2_235_Y,
|
| 330 |
|
|
MX2_98_Y, MX2_383_Y, MX2_40_Y, MX2_388_Y, MX2_305_Y,
|
| 331 |
|
|
MX2_413_Y, MX2_365_Y, MX2_128_Y, MX2_17_Y, MX2_31_Y,
|
| 332 |
|
|
MX2_237_Y, MX2_228_Y, MX2_132_Y, MX2_28_Y, MX2_268_Y,
|
| 333 |
|
|
MX2_334_Y, BUFF_12_Y, BUFF_6_Y, BUFF_3_Y, BUFF_29_Y,
|
| 334 |
|
|
BUFF_25_Y, MX2_134_Y, MX2_386_Y, MX2_249_Y, MX2_342_Y,
|
| 335 |
|
|
MX2_254_Y, MX2_10_Y, MX2_66_Y, MX2_340_Y, MX2_355_Y,
|
| 336 |
|
|
MX2_171_Y, MX2_201_Y, MX2_52_Y, MX2_325_Y, MX2_114_Y,
|
| 337 |
|
|
MX2_250_Y, MX2_133_Y, MX2_12_Y, MX2_385_Y, MX2_255_Y,
|
| 338 |
|
|
MX2_344_Y, MX2_222_Y, MX2_293_Y, MX2_32_Y, MX2_353_Y,
|
| 339 |
|
|
MX2_329_Y, MX2_211_Y, MX2_230_Y, MX2_119_Y, MX2_273_Y,
|
| 340 |
|
|
MX2_298_Y, MX2_205_Y, MX2_366_Y, MX2_277_Y, MX2_368_Y,
|
| 341 |
|
|
MX2_292_Y, MX2_196_Y, MX2_64_Y, MX2_65_Y, MX2_349_Y,
|
| 342 |
|
|
MX2_27_Y, MX2_4_Y, MX2_219_Y, MX2_415_Y, MX2_373_Y,
|
| 343 |
|
|
MX2_315_Y, MX2_109_Y, MX2_313_Y, MX2_112_Y, MX2_137_Y,
|
| 344 |
|
|
MX2_144_Y, MX2_20_Y, MX2_300_Y, NOR2_2_Y, AND2A_4_Y,
|
| 345 |
|
|
AND2A_2_Y, AND2_2_Y, NOR2_3_Y, AND2A_5_Y, AND2A_3_Y,
|
| 346 |
|
|
AND2_3_Y, BUFF_34_Y, BUFF_28_Y, BUFF_39_Y, BUFF_1_Y,
|
| 347 |
|
|
BUFF_19_Y, MX2_100_Y, MX2_360_Y, MX2_227_Y, MX2_321_Y,
|
| 348 |
|
|
MX2_233_Y, MX2_406_Y, MX2_57_Y, MX2_210_Y, MX2_331_Y,
|
| 349 |
|
|
MX2_405_Y, MX2_176_Y, MX2_159_Y, MX2_198_Y, MX2_80_Y,
|
| 350 |
|
|
MX2_229_Y, MX2_95_Y, MX2_407_Y, MX2_357_Y, MX2_234_Y,
|
| 351 |
|
|
MX2_323_Y, MX2_69_Y, MX2_275_Y, MX2_279_Y, MX2_330_Y,
|
| 352 |
|
|
MX2_19_Y, MX2_56_Y, MX2_215_Y, MX2_84_Y, MX2_252_Y,
|
| 353 |
|
|
MX2_278_Y, MX2_194_Y, MX2_341_Y, MX2_257_Y, MX2_225_Y,
|
| 354 |
|
|
MX2_272_Y, MX2_14_Y, MX2_49_Y, MX2_184_Y, MX2_212_Y,
|
| 355 |
|
|
MX2_3_Y, MX2_401_Y, MX2_204_Y, MX2_393_Y, MX2_347_Y,
|
| 356 |
|
|
MX2_299_Y, MX2_76_Y, MX2_188_Y, MX2_77_Y, MX2_372_Y,
|
| 357 |
|
|
MX2_111_Y, MX2_116_Y, MX2_164_Y, BUFF_23_Y, BUFF_33_Y,
|
| 358 |
|
|
BUFF_5_Y, BUFF_36_Y, BUFF_7_Y, MX2_283_Y, MX2_145_Y,
|
| 359 |
|
|
MX2_411_Y, MX2_85_Y, MX2_0_Y, MX2_190_Y, MX2_236_Y,
|
| 360 |
|
|
MX2_232_Y, MX2_103_Y, MX2_224_Y, MX2_336_Y, MX2_200_Y,
|
| 361 |
|
|
MX2_157_Y, MX2_270_Y, MX2_414_Y, MX2_281_Y, MX2_191_Y,
|
| 362 |
|
|
MX2_141_Y, MX2_1_Y, MX2_87_Y, MX2_104_Y, MX2_43_Y,
|
| 363 |
|
|
MX2_89_Y, MX2_102_Y, MX2_58_Y, MX2_18_Y, MX2_395_Y,
|
| 364 |
|
|
MX2_274_Y, MX2_21_Y, MX2_47_Y, MX2_352_Y, MX2_121_Y,
|
| 365 |
|
|
MX2_23_Y, MX2_258_Y, MX2_41_Y, MX2_247_Y, MX2_226_Y,
|
| 366 |
|
|
MX2_213_Y, MX2_182_Y, MX2_202_Y, MX2_180_Y, MX2_376_Y,
|
| 367 |
|
|
MX2_173_Y, MX2_131_Y, MX2_61_Y, MX2_265_Y, MX2_208_Y,
|
| 368 |
|
|
MX2_267_Y, MX2_203_Y, MX2_289_Y, MX2_165_Y, MX2_115_Y,
|
| 369 |
|
|
BUFF_11_Y, BUFF_20_Y, BUFF_14_Y, BUFF_31_Y, BUFF_32_Y,
|
| 370 |
|
|
MX2_140_Y, MX2_304_Y, MX2_107_Y, MX2_379_Y, MX2_370_Y,
|
| 371 |
|
|
MX2_290_Y, MX2_122_Y, MX2_78_Y, MX2_53_Y, MX2_394_Y,
|
| 372 |
|
|
MX2_142_Y, MX2_35_Y, MX2_263_Y, MX2_162_Y, MX2_314_Y,
|
| 373 |
|
|
MX2_400_Y, MX2_392_Y, MX2_186_Y, MX2_129_Y, MX2_185_Y,
|
| 374 |
|
|
MX2_380_Y, MX2_54_Y, MX2_266_Y, MX2_177_Y, MX2_320_Y,
|
| 375 |
|
|
MX2_158_Y, MX2_333_Y, MX2_337_Y, MX2_138_Y, MX2_199_Y,
|
| 376 |
|
|
MX2_288_Y, MX2_148_Y, MX2_248_Y, MX2_106_Y, MX2_197_Y,
|
| 377 |
|
|
MX2_410_Y, MX2_127_Y, MX2_55_Y, MX2_282_Y, MX2_402_Y,
|
| 378 |
|
|
MX2_319_Y, MX2_9_Y, MX2_387_Y, MX2_150_Y, MX2_33_Y,
|
| 379 |
|
|
MX2_48_Y, MX2_409_Y, MX2_246_Y, MX2_295_Y, MX2_46_Y,
|
| 380 |
|
|
MX2_350_Y, MX2_187_Y, BUFF_24_Y, BUFF_2_Y, BUFF_16_Y,
|
| 381 |
|
|
BUFF_4_Y, BUFF_13_Y, MX2_256_Y, MX2_94_Y, MX2_381_Y,
|
| 382 |
|
|
MX2_62_Y, MX2_390_Y, MX2_160_Y, MX2_214_Y, MX2_286_Y,
|
| 383 |
|
|
MX2_68_Y, MX2_6_Y, MX2_311_Y, MX2_60_Y, MX2_302_Y,
|
| 384 |
|
|
MX2_242_Y, MX2_382_Y, MX2_253_Y, MX2_161_Y, MX2_93_Y,
|
| 385 |
|
|
MX2_391_Y, MX2_63_Y, MX2_175_Y, MX2_8_Y, MX2_297_Y,
|
| 386 |
|
|
MX2_67_Y, MX2_339_Y, MX2_192_Y, MX2_359_Y, MX2_245_Y,
|
| 387 |
|
|
MX2_404_Y, MX2_13_Y, MX2_324_Y, MX2_74_Y, MX2_408_Y,
|
| 388 |
|
|
MX2_307_Y, MX2_7_Y, MX2_34_Y, MX2_206_Y, MX2_72_Y,
|
| 389 |
|
|
MX2_318_Y, MX2_172_Y, MX2_152_Y, MX2_343_Y, MX2_143_Y,
|
| 390 |
|
|
MX2_83_Y, MX2_38_Y, MX2_238_Y, MX2_259_Y, MX2_241_Y,
|
| 391 |
|
|
MX2_396_Y, MX2_261_Y, MX2_30_Y, MX2_269_Y, NOR2_1_Y,
|
| 392 |
|
|
AND2A_1_Y, AND2A_7_Y, AND2_1_Y, NOR2_0_Y, AND2A_0_Y,
|
| 393 |
|
|
AND2A_6_Y, AND2_0_Y, BUFF_37_Y, BUFF_15_Y, BUFF_9_Y,
|
| 394 |
|
|
BUFF_8_Y, BUFF_30_Y, MX2_91_Y, MX2_280_Y, MX2_70_Y,
|
| 395 |
|
|
MX2_345_Y, MX2_335_Y, MX2_262_Y, MX2_75_Y, MX2_126_Y,
|
| 396 |
|
|
MX2_24_Y, MX2_358_Y, MX2_92_Y, MX2_209_Y, MX2_294_Y,
|
| 397 |
|
|
MX2_125_Y, MX2_287_Y, MX2_367_Y, MX2_356_Y, MX2_156_Y,
|
| 398 |
|
|
MX2_81_Y, MX2_154_Y, MX2_412_Y, MX2_25_Y, MX2_239_Y,
|
| 399 |
|
|
MX2_149_Y, MX2_71_Y, MX2_189_Y, MX2_306_Y, MX2_312_Y,
|
| 400 |
|
|
MX2_88_Y, MX2_167_Y, MX2_260_Y, MX2_97_Y, MX2_220_Y,
|
| 401 |
|
|
MX2_151_Y, MX2_166_Y, MX2_378_Y, MX2_79_Y, MX2_221_Y,
|
| 402 |
|
|
MX2_308_Y, MX2_369_Y, MX2_296_Y, MX2_399_Y, MX2_348_Y,
|
| 403 |
|
|
MX2_105_Y, MX2_2_Y, MX2_16_Y, MX2_26_Y, MX2_217_Y,
|
| 404 |
|
|
MX2_264_Y, MX2_11_Y, MX2_108_Y, MX2_207_Y, BUFF_18_Y,
|
| 405 |
|
|
BUFF_21_Y, BUFF_0_Y, BUFF_38_Y, BUFF_17_Y, MX2_135_Y,
|
| 406 |
|
|
MX2_303_Y, MX2_99_Y, MX2_374_Y, MX2_364_Y, MX2_285_Y,
|
| 407 |
|
|
MX2_113_Y, MX2_44_Y, MX2_50_Y, MX2_338_Y, MX2_136_Y,
|
| 408 |
|
|
MX2_153_Y, MX2_73_Y, MX2_155_Y, MX2_310_Y, MX2_397_Y,
|
| 409 |
|
|
MX2_389_Y, MX2_183_Y, MX2_123_Y, MX2_179_Y, MX2_326_Y,
|
| 410 |
|
|
MX2_51_Y, MX2_223_Y, MX2_174_Y, MX2_15_Y, MX2_375_Y,
|
| 411 |
|
|
MX2_328_Y, MX2_332_Y, MX2_130_Y, MX2_195_Y, MX2_284_Y,
|
| 412 |
|
|
MX2_139_Y, MX2_244_Y, MX2_59_Y, MX2_193_Y, MX2_361_Y,
|
| 413 |
|
|
MX2_120_Y, MX2_169_Y, MX2_96_Y, MX2_398_Y, MX2_316_Y,
|
| 414 |
|
|
MX2_5_Y, MX2_377_Y, MX2_147_Y, MX2_29_Y, MX2_42_Y,
|
| 415 |
|
|
MX2_354_Y, MX2_240_Y, MX2_251_Y, MX2_39_Y, MX2_45_Y,
|
| 416 |
|
|
MX2_403_Y, VCC_1_net, GND_1_net : std_logic ;
|
| 417 |
|
|
begin
|
| 418 |
|
|
|
| 419 |
|
|
VCC_2_net : VCC port map(Y => VCC_1_net);
|
| 420 |
|
|
GND_2_net : GND port map(Y => GND_1_net);
|
| 421 |
|
|
BUFF_8 : BUFF
|
| 422 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_8_Y);
|
| 423 |
|
|
dual_port_memory_R0C3 : RAM4K9
|
| 424 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 425 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 426 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 427 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 428 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 429 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 430 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 431 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 432 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 433 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 434 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 435 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 436 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 437 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 438 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 439 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 440 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 441 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 442 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 443 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_0_net,
|
| 444 |
|
|
BLKB => BLKB_EN_0_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 445 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 446 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 447 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR0_15_net, DOUTA2 =>
|
| 448 |
|
|
QAX_TEMPR0_14_net, DOUTA1 => QAX_TEMPR0_13_net, DOUTA0 =>
|
| 449 |
|
|
QAX_TEMPR0_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 450 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 451 |
|
|
DOUTB3 => QBX_TEMPR0_15_net, DOUTB2 => QBX_TEMPR0_14_net,
|
| 452 |
|
|
DOUTB1 => QBX_TEMPR0_13_net, DOUTB0 => QBX_TEMPR0_12_net);
|
| 453 |
|
|
ORB_GATE_11_inst : OR2
|
| 454 |
|
|
port map(A => ENABLE_ADDRB_11_net, B => WEBP, Y =>
|
| 455 |
|
|
BLKB_EN_11_net);
|
| 456 |
|
|
MX2_113 : MX2
|
| 457 |
|
|
port map(A => QAX_TEMPR6_3_net, B => QAX_TEMPR7_3_net, S =>
|
| 458 |
|
|
BUFF_0_Y, Y => MX2_113_Y);
|
| 459 |
|
|
MX2_279 : MX2
|
| 460 |
|
|
port map(A => QBX_TEMPR10_10_net, B => QBX_TEMPR11_10_net,
|
| 461 |
|
|
S => BUFF_39_Y, Y => MX2_279_Y);
|
| 462 |
|
|
ORB_GATE_4_inst : OR2
|
| 463 |
|
|
port map(A => ENABLE_ADDRB_4_net, B => WEBP, Y =>
|
| 464 |
|
|
BLKB_EN_4_net);
|
| 465 |
|
|
dual_port_memory_R9C0 : RAM4K9
|
| 466 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 467 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 468 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 469 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 470 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 471 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 472 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 473 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 474 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 475 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 476 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 477 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 478 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 479 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 480 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 481 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 482 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 483 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 484 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 485 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_9_net,
|
| 486 |
|
|
BLKB => BLKB_EN_9_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 487 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 488 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 489 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR9_3_net, DOUTA2 =>
|
| 490 |
|
|
QAX_TEMPR9_2_net, DOUTA1 => QAX_TEMPR9_1_net, DOUTA0 =>
|
| 491 |
|
|
QAX_TEMPR9_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 492 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 493 |
|
|
DOUTB3 => QBX_TEMPR9_3_net, DOUTB2 => QBX_TEMPR9_2_net,
|
| 494 |
|
|
DOUTB1 => QBX_TEMPR9_1_net, DOUTB0 => QBX_TEMPR9_0_net);
|
| 495 |
|
|
MX2_319 : MX2
|
| 496 |
|
|
port map(A => QAX_TEMPR2_9_net, B => QAX_TEMPR3_9_net, S =>
|
| 497 |
|
|
BUFF_11_Y, Y => MX2_319_Y);
|
| 498 |
|
|
MX2_226 : MX2
|
| 499 |
|
|
port map(A => MX2_41_Y, B => MX2_247_Y, S => BUFF_36_Y,
|
| 500 |
|
|
Y => MX2_226_Y);
|
| 501 |
|
|
MX2_304 : MX2
|
| 502 |
|
|
port map(A => QAX_TEMPR2_11_net, B => QAX_TEMPR3_11_net,
|
| 503 |
|
|
S => BUFF_14_Y, Y => MX2_304_Y);
|
| 504 |
|
|
MX2_382 : MX2
|
| 505 |
|
|
port map(A => QBX_TEMPR2_14_net, B => QBX_TEMPR3_14_net,
|
| 506 |
|
|
S => BUFF_2_Y, Y => MX2_382_Y);
|
| 507 |
|
|
MX2_183 : MX2
|
| 508 |
|
|
port map(A => MX2_397_Y, B => MX2_389_Y, S =>
|
| 509 |
|
|
ADDRA_FF2_2_net, Y => MX2_183_Y);
|
| 510 |
|
|
dual_port_memory_R13C3 : RAM4K9
|
| 511 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 512 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 513 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 514 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 515 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 516 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 517 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 518 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 519 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 520 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 521 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 522 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 523 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 524 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 525 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 526 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 527 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 528 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 529 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 530 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_13_net,
|
| 531 |
|
|
BLKB => BLKB_EN_13_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 532 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 533 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 534 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR13_15_net, DOUTA2 =>
|
| 535 |
|
|
QAX_TEMPR13_14_net, DOUTA1 => QAX_TEMPR13_13_net,
|
| 536 |
|
|
DOUTA0 => QAX_TEMPR13_12_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 537 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 538 |
|
|
DOUTB3 => QBX_TEMPR13_15_net, DOUTB2 =>
|
| 539 |
|
|
QBX_TEMPR13_14_net, DOUTB1 => QBX_TEMPR13_13_net,
|
| 540 |
|
|
DOUTB0 => QBX_TEMPR13_12_net);
|
| 541 |
|
|
dual_port_memory_R6C3 : RAM4K9
|
| 542 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 543 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 544 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 545 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 546 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 547 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 548 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 549 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 550 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 551 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 552 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 553 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 554 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 555 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 556 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 557 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 558 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 559 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 560 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 561 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_6_net,
|
| 562 |
|
|
BLKB => BLKB_EN_6_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 563 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 564 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 565 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR6_15_net, DOUTA2 =>
|
| 566 |
|
|
QAX_TEMPR6_14_net, DOUTA1 => QAX_TEMPR6_13_net, DOUTA0 =>
|
| 567 |
|
|
QAX_TEMPR6_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 568 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 569 |
|
|
DOUTB3 => QBX_TEMPR6_15_net, DOUTB2 => QBX_TEMPR6_14_net,
|
| 570 |
|
|
DOUTB1 => QBX_TEMPR6_13_net, DOUTB0 => QBX_TEMPR6_12_net);
|
| 571 |
|
|
MX2_389 : MX2
|
| 572 |
|
|
port map(A => MX2_123_Y, B => MX2_179_Y, S => BUFF_17_Y,
|
| 573 |
|
|
Y => MX2_389_Y);
|
| 574 |
|
|
MX2_405 : MX2
|
| 575 |
|
|
port map(A => QBX_TEMPR10_11_net, B => QBX_TEMPR11_11_net,
|
| 576 |
|
|
S => BUFF_39_Y, Y => MX2_405_Y);
|
| 577 |
|
|
MX2_377 : MX2
|
| 578 |
|
|
port map(A => MX2_29_Y, B => MX2_42_Y, S => BUFF_38_Y, Y =>
|
| 579 |
|
|
MX2_377_Y);
|
| 580 |
|
|
BUFF_7 : BUFF
|
| 581 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_7_Y);
|
| 582 |
|
|
MX2_273 : MX2
|
| 583 |
|
|
port map(A => MX2_230_Y, B => MX2_119_Y, S => BUFF_29_Y,
|
| 584 |
|
|
Y => MX2_273_Y);
|
| 585 |
|
|
NAND2_ENABLE_ADDRA_7_inst : NAND2
|
| 586 |
|
|
port map(A => AND2_2_Y, B => AND2A_5_Y, Y =>
|
| 587 |
|
|
ENABLE_ADDRA_7_net);
|
| 588 |
|
|
MX2_408 : MX2
|
| 589 |
|
|
port map(A => QBX_TEMPR6_12_net, B => QBX_TEMPR7_12_net,
|
| 590 |
|
|
S => BUFF_24_Y, Y => MX2_408_Y);
|
| 591 |
|
|
MX2_124 : MX2
|
| 592 |
|
|
port map(A => QAX_TEMPR4_4_net, B => QAX_TEMPR5_4_net, S =>
|
| 593 |
|
|
BUFF_22_Y, Y => MX2_124_Y);
|
| 594 |
|
|
MX2_89 : MX2
|
| 595 |
|
|
port map(A => QBX_TEMPR10_2_net, B => QBX_TEMPR11_2_net,
|
| 596 |
|
|
S => BUFF_5_Y, Y => MX2_89_Y);
|
| 597 |
|
|
MX2_37 : MX2
|
| 598 |
|
|
port map(A => QAX_TEMPR8_6_net, B => QAX_TEMPR9_6_net, S =>
|
| 599 |
|
|
BUFF_26_Y, Y => MX2_37_Y);
|
| 600 |
|
|
MX2_54 : MX2
|
| 601 |
|
|
port map(A => QAX_TEMPR8_10_net, B => QAX_TEMPR9_10_net,
|
| 602 |
|
|
S => BUFF_20_Y, Y => MX2_54_Y);
|
| 603 |
|
|
MX2_328 : MX2
|
| 604 |
|
|
port map(A => QAX_TEMPR0_0_net, B => QAX_TEMPR1_0_net, S =>
|
| 605 |
|
|
BUFF_18_Y, Y => MX2_328_Y);
|
| 606 |
|
|
MX2_75 : MX2
|
| 607 |
|
|
port map(A => QAX_TEMPR6_15_net, B => QAX_TEMPR7_15_net,
|
| 608 |
|
|
S => BUFF_9_Y, Y => MX2_75_Y);
|
| 609 |
|
|
dual_port_memory_R3C1 : RAM4K9
|
| 610 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 611 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 612 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 613 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 614 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 615 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 616 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 617 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 618 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 619 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 620 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 621 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 622 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 623 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 624 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 625 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 626 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 627 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 628 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 629 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_3_net,
|
| 630 |
|
|
BLKB => BLKB_EN_3_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 631 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 632 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 633 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR3_7_net, DOUTA2 =>
|
| 634 |
|
|
QAX_TEMPR3_6_net, DOUTA1 => QAX_TEMPR3_5_net, DOUTA0 =>
|
| 635 |
|
|
QAX_TEMPR3_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 636 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 637 |
|
|
DOUTB3 => QBX_TEMPR3_7_net, DOUTB2 => QBX_TEMPR3_6_net,
|
| 638 |
|
|
DOUTB1 => QBX_TEMPR3_5_net, DOUTB0 => QBX_TEMPR3_4_net);
|
| 639 |
|
|
MX2_23 : MX2
|
| 640 |
|
|
port map(A => QBX_TEMPR6_0_net, B => QBX_TEMPR7_0_net, S =>
|
| 641 |
|
|
BUFF_23_Y, Y => MX2_23_Y);
|
| 642 |
|
|
MX2_112 : MX2
|
| 643 |
|
|
port map(A => QBX_TEMPR8_5_net, B => QBX_TEMPR9_5_net, S =>
|
| 644 |
|
|
BUFF_6_Y, Y => MX2_112_Y);
|
| 645 |
|
|
MX2_323 : MX2
|
| 646 |
|
|
port map(A => QBX_TEMPR6_10_net, B => QBX_TEMPR7_10_net,
|
| 647 |
|
|
S => BUFF_28_Y, Y => MX2_323_Y);
|
| 648 |
|
|
MX2_296 : MX2
|
| 649 |
|
|
port map(A => QAX_TEMPR2_13_net, B => QAX_TEMPR3_13_net,
|
| 650 |
|
|
S => BUFF_37_Y, Y => MX2_296_Y);
|
| 651 |
|
|
MX2_94 : MX2
|
| 652 |
|
|
port map(A => QBX_TEMPR2_15_net, B => QBX_TEMPR3_15_net,
|
| 653 |
|
|
S => BUFF_16_Y, Y => MX2_94_Y);
|
| 654 |
|
|
MX2_65 : MX2
|
| 655 |
|
|
port map(A => MX2_349_Y, B => QBX_TEMPR14_4_net, S =>
|
| 656 |
|
|
BUFF_29_Y, Y => MX2_65_Y);
|
| 657 |
|
|
AFF1_0_inst : DFN1
|
| 658 |
|
|
port map(D => ADDRA(10), CLK => CLKA, Q => ADDRA_FF2_0_net);
|
| 659 |
|
|
MX2_1 : MX2
|
| 660 |
|
|
port map(A => QBX_TEMPR4_2_net, B => QBX_TEMPR5_2_net, S =>
|
| 661 |
|
|
BUFF_33_Y, Y => MX2_1_Y);
|
| 662 |
|
|
MX2_364 : MX2
|
| 663 |
|
|
port map(A => MX2_99_Y, B => MX2_374_Y, S =>
|
| 664 |
|
|
ADDRA_FF2_2_net, Y => MX2_364_Y);
|
| 665 |
|
|
MX2_182 : MX2
|
| 666 |
|
|
port map(A => QBX_TEMPR12_0_net, B => QBX_TEMPR13_0_net,
|
| 667 |
|
|
S => BUFF_23_Y, Y => MX2_182_Y);
|
| 668 |
|
|
MX2_414 : MX2
|
| 669 |
|
|
port map(A => QBX_TEMPR2_2_net, B => QBX_TEMPR3_2_net, S =>
|
| 670 |
|
|
BUFF_33_Y, Y => MX2_414_Y);
|
| 671 |
|
|
MX2_278 : MX2
|
| 672 |
|
|
port map(A => MX2_341_Y, B => MX2_257_Y, S => BUFF_1_Y,
|
| 673 |
|
|
Y => MX2_278_Y);
|
| 674 |
|
|
MX2_251 : MX2
|
| 675 |
|
|
port map(A => QAX_TEMPR10_1_net, B => QAX_TEMPR11_1_net,
|
| 676 |
|
|
S => BUFF_21_Y, Y => MX2_251_Y);
|
| 677 |
|
|
MX2_257 : MX2
|
| 678 |
|
|
port map(A => QBX_TEMPR6_8_net, B => QBX_TEMPR7_8_net, S =>
|
| 679 |
|
|
BUFF_34_Y, Y => MX2_257_Y);
|
| 680 |
|
|
BUFF_12 : BUFF
|
| 681 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_12_Y);
|
| 682 |
|
|
MX2_176 : MX2
|
| 683 |
|
|
port map(A => MX2_331_Y, B => MX2_405_Y, S => BUFF_19_Y,
|
| 684 |
|
|
Y => MX2_176_Y);
|
| 685 |
|
|
dual_port_memory_R7C2 : RAM4K9
|
| 686 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 687 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 688 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 689 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 690 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 691 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 692 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 693 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 694 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 695 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 696 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 697 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 698 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 699 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 700 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 701 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 702 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 703 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 704 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 705 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_7_net,
|
| 706 |
|
|
BLKB => BLKB_EN_7_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 707 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 708 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 709 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR7_11_net, DOUTA2 =>
|
| 710 |
|
|
QAX_TEMPR7_10_net, DOUTA1 => QAX_TEMPR7_9_net, DOUTA0 =>
|
| 711 |
|
|
QAX_TEMPR7_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 712 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 713 |
|
|
DOUTB3 => QBX_TEMPR7_11_net, DOUTB2 => QBX_TEMPR7_10_net,
|
| 714 |
|
|
DOUTB1 => QBX_TEMPR7_9_net, DOUTB0 => QBX_TEMPR7_8_net);
|
| 715 |
|
|
ORA_GATE_12_inst : OR2
|
| 716 |
|
|
port map(A => ENABLE_ADDRA_12_net, B => WEAP, Y =>
|
| 717 |
|
|
BLKA_EN_12_net);
|
| 718 |
|
|
MX2_220 : MX2
|
| 719 |
|
|
port map(A => QAX_TEMPR6_12_net, B => QAX_TEMPR7_12_net,
|
| 720 |
|
|
S => BUFF_37_Y, Y => MX2_220_Y);
|
| 721 |
|
|
MX2_175 : MX2
|
| 722 |
|
|
port map(A => MX2_67_Y, B => MX2_339_Y, S =>
|
| 723 |
|
|
ADDRB_FF2_2_net, Y => MX2_175_Y);
|
| 724 |
|
|
MX2_121 : MX2
|
| 725 |
|
|
port map(A => QBX_TEMPR4_0_net, B => QBX_TEMPR5_0_net, S =>
|
| 726 |
|
|
BUFF_23_Y, Y => MX2_121_Y);
|
| 727 |
|
|
BUFF_33 : BUFF
|
| 728 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_33_Y);
|
| 729 |
|
|
BUFF_31 : BUFF
|
| 730 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_31_Y);
|
| 731 |
|
|
MX2_239 : MX2
|
| 732 |
|
|
port map(A => QAX_TEMPR10_14_net, B => QAX_TEMPR11_14_net,
|
| 733 |
|
|
S => BUFF_9_Y, Y => MX2_239_Y);
|
| 734 |
|
|
MX2_DOUTB_10_inst : MX2
|
| 735 |
|
|
port map(A => MX2_357_Y, B => MX2_69_Y, S =>
|
| 736 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(10));
|
| 737 |
|
|
MX2_370 : MX2
|
| 738 |
|
|
port map(A => MX2_107_Y, B => MX2_379_Y, S =>
|
| 739 |
|
|
ADDRA_FF2_2_net, Y => MX2_370_Y);
|
| 740 |
|
|
MX2_100 : MX2
|
| 741 |
|
|
port map(A => QBX_TEMPR0_11_net, B => QBX_TEMPR1_11_net,
|
| 742 |
|
|
S => BUFF_39_Y, Y => MX2_100_Y);
|
| 743 |
|
|
MX2_DOUTB_4_inst : MX2
|
| 744 |
|
|
port map(A => MX2_205_Y, B => MX2_368_Y, S =>
|
| 745 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(4));
|
| 746 |
|
|
MX2_194 : MX2
|
| 747 |
|
|
port map(A => MX2_252_Y, B => MX2_278_Y, S =>
|
| 748 |
|
|
ADDRB_FF2_2_net, Y => MX2_194_Y);
|
| 749 |
|
|
RESETBUBBLE : INV
|
| 750 |
|
|
port map(A => RESET, Y => RESETP);
|
| 751 |
|
|
BUFF_22 : BUFF
|
| 752 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_22_Y);
|
| 753 |
|
|
ORB_GATE_6_inst : OR2
|
| 754 |
|
|
port map(A => ENABLE_ADDRB_6_net, B => WEBP, Y =>
|
| 755 |
|
|
BLKB_EN_6_net);
|
| 756 |
|
|
MX2_398 : MX2
|
| 757 |
|
|
port map(A => QAX_TEMPR0_1_net, B => QAX_TEMPR1_1_net, S =>
|
| 758 |
|
|
BUFF_18_Y, Y => MX2_398_Y);
|
| 759 |
|
|
MX2_225 : MX2
|
| 760 |
|
|
port map(A => MX2_49_Y, B => MX2_184_Y, S =>
|
| 761 |
|
|
ADDRB_FF2_2_net, Y => MX2_225_Y);
|
| 762 |
|
|
MX2_393 : MX2
|
| 763 |
|
|
port map(A => MX2_299_Y, B => MX2_76_Y, S => BUFF_1_Y, Y =>
|
| 764 |
|
|
MX2_393_Y);
|
| 765 |
|
|
MX2_147 : MX2
|
| 766 |
|
|
port map(A => MX2_5_Y, B => MX2_377_Y, S => ADDRA_FF2_2_net,
|
| 767 |
|
|
Y => MX2_147_Y);
|
| 768 |
|
|
MX2_321 : MX2
|
| 769 |
|
|
port map(A => MX2_406_Y, B => MX2_57_Y, S => BUFF_19_Y,
|
| 770 |
|
|
Y => MX2_321_Y);
|
| 771 |
|
|
MX2_0 : MX2
|
| 772 |
|
|
port map(A => MX2_411_Y, B => MX2_85_Y, S =>
|
| 773 |
|
|
ADDRB_FF2_2_net, Y => MX2_0_Y);
|
| 774 |
|
|
MX2_DOUTB_3_inst : MX2
|
| 775 |
|
|
port map(A => MX2_0_Y, B => MX2_232_Y, S => ADDRB_FF2_3_net,
|
| 776 |
|
|
Y => DOUTB(3));
|
| 777 |
|
|
BUFF_4 : BUFF
|
| 778 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_4_Y);
|
| 779 |
|
|
MX2_337 : MX2
|
| 780 |
|
|
port map(A => QAX_TEMPR2_8_net, B => QAX_TEMPR3_8_net, S =>
|
| 781 |
|
|
BUFF_11_Y, Y => MX2_337_Y);
|
| 782 |
|
|
MX2_233 : MX2
|
| 783 |
|
|
port map(A => MX2_227_Y, B => MX2_321_Y, S =>
|
| 784 |
|
|
ADDRB_FF2_2_net, Y => MX2_233_Y);
|
| 785 |
|
|
MX2_21 : MX2
|
| 786 |
|
|
port map(A => MX2_395_Y, B => MX2_274_Y, S => BUFF_36_Y,
|
| 787 |
|
|
Y => MX2_21_Y);
|
| 788 |
|
|
MX2_14 : MX2
|
| 789 |
|
|
port map(A => QBX_TEMPR10_8_net, B => QBX_TEMPR11_8_net,
|
| 790 |
|
|
S => BUFF_34_Y, Y => MX2_14_Y);
|
| 791 |
|
|
MX2_33 : MX2
|
| 792 |
|
|
port map(A => QAX_TEMPR4_9_net, B => QAX_TEMPR5_9_net, S =>
|
| 793 |
|
|
BUFF_11_Y, Y => MX2_33_Y);
|
| 794 |
|
|
MX2_290 : MX2
|
| 795 |
|
|
port map(A => QAX_TEMPR4_11_net, B => QAX_TEMPR5_11_net,
|
| 796 |
|
|
S => BUFF_14_Y, Y => MX2_290_Y);
|
| 797 |
|
|
MX2_129 : MX2
|
| 798 |
|
|
port map(A => QAX_TEMPR4_10_net, B => QAX_TEMPR5_10_net,
|
| 799 |
|
|
S => BUFF_20_Y, Y => MX2_129_Y);
|
| 800 |
|
|
MX2_28 : MX2
|
| 801 |
|
|
port map(A => MX2_228_Y, B => MX2_132_Y, S => BUFF_35_Y,
|
| 802 |
|
|
Y => MX2_28_Y);
|
| 803 |
|
|
MX2_191 : MX2
|
| 804 |
|
|
port map(A => MX2_1_Y, B => MX2_87_Y, S => BUFF_7_Y, Y =>
|
| 805 |
|
|
MX2_191_Y);
|
| 806 |
|
|
dual_port_memory_R9C2 : RAM4K9
|
| 807 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 808 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 809 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 810 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 811 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 812 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 813 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 814 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 815 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 816 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 817 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 818 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 819 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 820 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 821 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 822 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 823 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 824 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 825 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 826 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_9_net,
|
| 827 |
|
|
BLKB => BLKB_EN_9_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 828 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 829 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 830 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR9_11_net, DOUTA2 =>
|
| 831 |
|
|
QAX_TEMPR9_10_net, DOUTA1 => QAX_TEMPR9_9_net, DOUTA0 =>
|
| 832 |
|
|
QAX_TEMPR9_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 833 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 834 |
|
|
DOUTB3 => QBX_TEMPR9_11_net, DOUTB2 => QBX_TEMPR9_10_net,
|
| 835 |
|
|
DOUTB1 => QBX_TEMPR9_9_net, DOUTB0 => QBX_TEMPR9_8_net);
|
| 836 |
|
|
MX2_DOUTA_2_inst : MX2
|
| 837 |
|
|
port map(A => MX2_183_Y, B => MX2_326_Y, S =>
|
| 838 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(2));
|
| 839 |
|
|
MX2_160 : MX2
|
| 840 |
|
|
port map(A => QBX_TEMPR4_15_net, B => QBX_TEMPR5_15_net,
|
| 841 |
|
|
S => BUFF_16_Y, Y => MX2_160_Y);
|
| 842 |
|
|
MX2_325 : MX2
|
| 843 |
|
|
port map(A => QBX_TEMPR12_7_net, B => QBX_TEMPR13_7_net,
|
| 844 |
|
|
S => BUFF_3_Y, Y => MX2_325_Y);
|
| 845 |
|
|
MX2_DOUTB_9_inst : MX2
|
| 846 |
|
|
port map(A => MX2_347_Y, B => MX2_188_Y, S =>
|
| 847 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(9));
|
| 848 |
|
|
NAND2_ENABLE_ADDRA_8_inst : NAND2
|
| 849 |
|
|
port map(A => NOR2_2_Y, B => AND2A_3_Y, Y =>
|
| 850 |
|
|
ENABLE_ADDRA_8_net);
|
| 851 |
|
|
MX2_238 : MX2
|
| 852 |
|
|
port map(A => QBX_TEMPR6_13_net, B => QBX_TEMPR7_13_net,
|
| 853 |
|
|
S => BUFF_2_Y, Y => MX2_238_Y);
|
| 854 |
|
|
MX2_295 : MX2
|
| 855 |
|
|
port map(A => QAX_TEMPR10_9_net, B => QAX_TEMPR11_9_net,
|
| 856 |
|
|
S => BUFF_20_Y, Y => MX2_295_Y);
|
| 857 |
|
|
MX2_391 : MX2
|
| 858 |
|
|
port map(A => QBX_TEMPR4_14_net, B => QBX_TEMPR5_14_net,
|
| 859 |
|
|
S => BUFF_2_Y, Y => MX2_391_Y);
|
| 860 |
|
|
MX2_50 : MX2
|
| 861 |
|
|
port map(A => QAX_TEMPR8_3_net, B => QAX_TEMPR9_3_net, S =>
|
| 862 |
|
|
BUFF_0_Y, Y => MX2_50_Y);
|
| 863 |
|
|
MX2_7 : MX2
|
| 864 |
|
|
port map(A => QBX_TEMPR8_12_net, B => QBX_TEMPR9_12_net,
|
| 865 |
|
|
S => BUFF_24_Y, Y => MX2_7_Y);
|
| 866 |
|
|
MX2_219 : MX2
|
| 867 |
|
|
port map(A => MX2_27_Y, B => MX2_4_Y, S => BUFF_29_Y, Y =>
|
| 868 |
|
|
MX2_219_Y);
|
| 869 |
|
|
MX2_374 : MX2
|
| 870 |
|
|
port map(A => MX2_285_Y, B => MX2_113_Y, S => BUFF_17_Y,
|
| 871 |
|
|
Y => MX2_374_Y);
|
| 872 |
|
|
AND2A_7 : AND2A
|
| 873 |
|
|
port map(A => ADDRB(10), B => ADDRB(11), Y => AND2A_7_Y);
|
| 874 |
|
|
MX2_403 : MX2
|
| 875 |
|
|
port map(A => QAX_TEMPR12_1_net, B => QAX_TEMPR13_1_net,
|
| 876 |
|
|
S => BUFF_21_Y, Y => MX2_403_Y);
|
| 877 |
|
|
MX2_136 : MX2
|
| 878 |
|
|
port map(A => MX2_50_Y, B => MX2_338_Y, S => BUFF_17_Y,
|
| 879 |
|
|
Y => MX2_136_Y);
|
| 880 |
|
|
BUFF_16 : BUFF
|
| 881 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_16_Y);
|
| 882 |
|
|
NOR2_2 : NOR2
|
| 883 |
|
|
port map(A => ADDRA(11), B => ADDRA(10), Y => NOR2_2_Y);
|
| 884 |
|
|
MX2_90 : MX2
|
| 885 |
|
|
port map(A => QAX_TEMPR6_7_net, B => QAX_TEMPR7_7_net, S =>
|
| 886 |
|
|
BUFF_10_Y, Y => MX2_90_Y);
|
| 887 |
|
|
MX2_135 : MX2
|
| 888 |
|
|
port map(A => QAX_TEMPR0_3_net, B => QAX_TEMPR1_3_net, S =>
|
| 889 |
|
|
BUFF_0_Y, Y => MX2_135_Y);
|
| 890 |
|
|
MX2_6 : MX2
|
| 891 |
|
|
port map(A => QBX_TEMPR10_15_net, B => QBX_TEMPR11_15_net,
|
| 892 |
|
|
S => BUFF_16_Y, Y => MX2_6_Y);
|
| 893 |
|
|
NOR2_3 : NOR2
|
| 894 |
|
|
port map(A => ADDRA(13), B => ADDRA(12), Y => NOR2_3_Y);
|
| 895 |
|
|
MX2_289 : MX2
|
| 896 |
|
|
port map(A => MX2_267_Y, B => MX2_203_Y, S => BUFF_36_Y,
|
| 897 |
|
|
Y => MX2_289_Y);
|
| 898 |
|
|
NAND2_ENABLE_ADDRA_2_inst : NAND2
|
| 899 |
|
|
port map(A => AND2A_2_Y, B => NOR2_3_Y, Y =>
|
| 900 |
|
|
ENABLE_ADDRA_2_net);
|
| 901 |
|
|
MX2_DOUTA_3_inst : MX2
|
| 902 |
|
|
port map(A => MX2_364_Y, B => MX2_44_Y, S =>
|
| 903 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(3));
|
| 904 |
|
|
dual_port_memory_R11C2 : RAM4K9
|
| 905 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 906 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 907 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 908 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 909 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 910 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 911 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 912 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 913 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 914 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 915 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 916 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 917 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 918 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 919 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 920 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 921 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 922 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 923 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 924 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_11_net,
|
| 925 |
|
|
BLKB => BLKB_EN_11_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 926 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 927 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 928 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR11_11_net, DOUTA2 =>
|
| 929 |
|
|
QAX_TEMPR11_10_net, DOUTA1 => QAX_TEMPR11_9_net,
|
| 930 |
|
|
DOUTA0 => QAX_TEMPR11_8_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 931 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 932 |
|
|
DOUTB3 => QBX_TEMPR11_11_net, DOUTB2 =>
|
| 933 |
|
|
QBX_TEMPR11_10_net, DOUTB1 => QBX_TEMPR11_9_net,
|
| 934 |
|
|
DOUTB0 => QBX_TEMPR11_8_net);
|
| 935 |
|
|
MX2_330 : MX2
|
| 936 |
|
|
port map(A => MX2_275_Y, B => MX2_279_Y, S => BUFF_19_Y,
|
| 937 |
|
|
Y => MX2_330_Y);
|
| 938 |
|
|
BUFF_26 : BUFF
|
| 939 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_26_Y);
|
| 940 |
|
|
MX2_199 : MX2
|
| 941 |
|
|
port map(A => MX2_148_Y, B => MX2_248_Y, S => BUFF_31_Y,
|
| 942 |
|
|
Y => MX2_199_Y);
|
| 943 |
|
|
MX2_401 : MX2
|
| 944 |
|
|
port map(A => QBX_TEMPR2_9_net, B => QBX_TEMPR3_9_net, S =>
|
| 945 |
|
|
BUFF_34_Y, Y => MX2_401_Y);
|
| 946 |
|
|
MX2_317 : MX2
|
| 947 |
|
|
port map(A => QAX_TEMPR0_4_net, B => QAX_TEMPR1_4_net, S =>
|
| 948 |
|
|
BUFF_22_Y, Y => MX2_317_Y);
|
| 949 |
|
|
NAND2_ENABLE_ADDRB_14_inst : NAND2
|
| 950 |
|
|
port map(A => AND2A_7_Y, B => AND2_0_Y, Y =>
|
| 951 |
|
|
ENABLE_ADDRB_14_net);
|
| 952 |
|
|
MX2_222 : MX2
|
| 953 |
|
|
port map(A => MX2_353_Y, B => MX2_329_Y, S =>
|
| 954 |
|
|
ADDRB_FF2_2_net, Y => MX2_222_Y);
|
| 955 |
|
|
MX2_213 : MX2
|
| 956 |
|
|
port map(A => MX2_182_Y, B => QBX_TEMPR14_0_net, S =>
|
| 957 |
|
|
BUFF_36_Y, Y => MX2_213_Y);
|
| 958 |
|
|
MX2_42 : MX2
|
| 959 |
|
|
port map(A => QAX_TEMPR6_1_net, B => QAX_TEMPR7_1_net, S =>
|
| 960 |
|
|
BUFF_21_Y, Y => MX2_42_Y);
|
| 961 |
|
|
NAND2_ENABLE_ADDRB_6_inst : NAND2
|
| 962 |
|
|
port map(A => AND2A_7_Y, B => AND2A_0_Y, Y =>
|
| 963 |
|
|
ENABLE_ADDRB_6_net);
|
| 964 |
|
|
MX2_128 : MX2
|
| 965 |
|
|
port map(A => MX2_413_Y, B => MX2_365_Y, S =>
|
| 966 |
|
|
ADDRA_FF2_2_net, Y => MX2_128_Y);
|
| 967 |
|
|
dual_port_memory_R3C2 : RAM4K9
|
| 968 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 969 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 970 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 971 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 972 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 973 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 974 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 975 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 976 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 977 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 978 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 979 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 980 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 981 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 982 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 983 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 984 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 985 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 986 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 987 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_3_net,
|
| 988 |
|
|
BLKB => BLKB_EN_3_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 989 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 990 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 991 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR3_11_net, DOUTA2 =>
|
| 992 |
|
|
QAX_TEMPR3_10_net, DOUTA1 => QAX_TEMPR3_9_net, DOUTA0 =>
|
| 993 |
|
|
QAX_TEMPR3_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 994 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 995 |
|
|
DOUTB3 => QBX_TEMPR3_11_net, DOUTB2 => QBX_TEMPR3_10_net,
|
| 996 |
|
|
DOUTB1 => QBX_TEMPR3_9_net, DOUTB0 => QBX_TEMPR3_8_net);
|
| 997 |
|
|
MX2_387 : MX2
|
| 998 |
|
|
port map(A => MX2_33_Y, B => MX2_48_Y, S => BUFF_31_Y, Y =>
|
| 999 |
|
|
MX2_387_Y);
|
| 1000 |
|
|
BUFF_37 : BUFF
|
| 1001 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_37_Y);
|
| 1002 |
|
|
MX2_31 : MX2
|
| 1003 |
|
|
port map(A => QAX_TEMPR6_5_net, B => QAX_TEMPR7_5_net, S =>
|
| 1004 |
|
|
BUFF_26_Y, Y => MX2_31_Y);
|
| 1005 |
|
|
MX2_395 : MX2
|
| 1006 |
|
|
port map(A => QBX_TEMPR0_0_net, B => QBX_TEMPR1_0_net, S =>
|
| 1007 |
|
|
BUFF_23_Y, Y => MX2_395_Y);
|
| 1008 |
|
|
MX2_283 : MX2
|
| 1009 |
|
|
port map(A => QBX_TEMPR0_3_net, B => QBX_TEMPR1_3_net, S =>
|
| 1010 |
|
|
BUFF_5_Y, Y => MX2_283_Y);
|
| 1011 |
|
|
MX2_85 : MX2
|
| 1012 |
|
|
port map(A => MX2_190_Y, B => MX2_236_Y, S => BUFF_7_Y,
|
| 1013 |
|
|
Y => MX2_85_Y);
|
| 1014 |
|
|
MX2_DOUTA_14_inst : MX2
|
| 1015 |
|
|
port map(A => MX2_156_Y, B => MX2_412_Y, S =>
|
| 1016 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(14));
|
| 1017 |
|
|
MX2_56 : MX2
|
| 1018 |
|
|
port map(A => QBX_TEMPR12_10_net, B => QBX_TEMPR13_10_net,
|
| 1019 |
|
|
S => BUFF_39_Y, Y => MX2_56_Y);
|
| 1020 |
|
|
MX2_DOUTB_15_inst : MX2
|
| 1021 |
|
|
port map(A => MX2_390_Y, B => MX2_286_Y, S =>
|
| 1022 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(15));
|
| 1023 |
|
|
MX2_38 : MX2
|
| 1024 |
|
|
port map(A => QBX_TEMPR4_13_net, B => QBX_TEMPR5_13_net,
|
| 1025 |
|
|
S => BUFF_24_Y, Y => MX2_38_Y);
|
| 1026 |
|
|
MX2_107 : MX2
|
| 1027 |
|
|
port map(A => MX2_140_Y, B => MX2_304_Y, S => BUFF_32_Y,
|
| 1028 |
|
|
Y => MX2_107_Y);
|
| 1029 |
|
|
ORA_GATE_9_inst : OR2
|
| 1030 |
|
|
port map(A => ENABLE_ADDRA_9_net, B => WEAP, Y =>
|
| 1031 |
|
|
BLKA_EN_9_net);
|
| 1032 |
|
|
MX2_256 : MX2
|
| 1033 |
|
|
port map(A => QBX_TEMPR0_15_net, B => QBX_TEMPR1_15_net,
|
| 1034 |
|
|
S => BUFF_16_Y, Y => MX2_256_Y);
|
| 1035 |
|
|
MX2_96 : MX2
|
| 1036 |
|
|
port map(A => QAX_TEMPR12_0_net, B => QAX_TEMPR13_0_net,
|
| 1037 |
|
|
S => BUFF_18_Y, Y => MX2_96_Y);
|
| 1038 |
|
|
MX2_218 : MX2
|
| 1039 |
|
|
port map(A => QAX_TEMPR10_7_net, B => QAX_TEMPR11_7_net,
|
| 1040 |
|
|
S => BUFF_10_Y, Y => MX2_218_Y);
|
| 1041 |
|
|
NAND2_ENABLE_ADDRB_4_inst : NAND2
|
| 1042 |
|
|
port map(A => NOR2_1_Y, B => AND2A_0_Y, Y =>
|
| 1043 |
|
|
ENABLE_ADDRB_4_net);
|
| 1044 |
|
|
MX2_74 : MX2
|
| 1045 |
|
|
port map(A => QBX_TEMPR4_12_net, B => QBX_TEMPR5_12_net,
|
| 1046 |
|
|
S => BUFF_24_Y, Y => MX2_74_Y);
|
| 1047 |
|
|
AND2_0 : AND2
|
| 1048 |
|
|
port map(A => ADDRB(13), B => ADDRB(12), Y => AND2_0_Y);
|
| 1049 |
|
|
dual_port_memory_R2C1 : RAM4K9
|
| 1050 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1051 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1052 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1053 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1054 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1055 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1056 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1057 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1058 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1059 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1060 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1061 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 1062 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 1063 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1064 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1065 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 1066 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1067 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1068 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1069 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_2_net,
|
| 1070 |
|
|
BLKB => BLKB_EN_2_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1071 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1072 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1073 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR2_7_net, DOUTA2 =>
|
| 1074 |
|
|
QAX_TEMPR2_6_net, DOUTA1 => QAX_TEMPR2_5_net, DOUTA0 =>
|
| 1075 |
|
|
QAX_TEMPR2_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1076 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1077 |
|
|
DOUTB3 => QBX_TEMPR2_7_net, DOUTB2 => QBX_TEMPR2_6_net,
|
| 1078 |
|
|
DOUTB1 => QBX_TEMPR2_5_net, DOUTB0 => QBX_TEMPR2_4_net);
|
| 1079 |
|
|
MX2_116 : MX2
|
| 1080 |
|
|
port map(A => MX2_164_Y, B => QBX_TEMPR14_9_net, S =>
|
| 1081 |
|
|
BUFF_1_Y, Y => MX2_116_Y);
|
| 1082 |
|
|
MX2_64 : MX2
|
| 1083 |
|
|
port map(A => MX2_292_Y, B => MX2_196_Y, S => BUFF_29_Y,
|
| 1084 |
|
|
Y => MX2_64_Y);
|
| 1085 |
|
|
MX2_288 : MX2
|
| 1086 |
|
|
port map(A => MX2_138_Y, B => MX2_199_Y, S =>
|
| 1087 |
|
|
ADDRA_FF2_2_net, Y => MX2_288_Y);
|
| 1088 |
|
|
MX2_10 : MX2
|
| 1089 |
|
|
port map(A => QBX_TEMPR4_7_net, B => QBX_TEMPR5_7_net, S =>
|
| 1090 |
|
|
BUFF_3_Y, Y => MX2_10_Y);
|
| 1091 |
|
|
MX2_115 : MX2
|
| 1092 |
|
|
port map(A => QBX_TEMPR12_1_net, B => QBX_TEMPR13_1_net,
|
| 1093 |
|
|
S => BUFF_33_Y, Y => MX2_115_Y);
|
| 1094 |
|
|
MX2_170 : MX2
|
| 1095 |
|
|
port map(A => MX2_384_Y, B => MX2_371_Y, S =>
|
| 1096 |
|
|
ADDRA_FF2_2_net, Y => MX2_170_Y);
|
| 1097 |
|
|
MX2_292 : MX2
|
| 1098 |
|
|
port map(A => QBX_TEMPR8_4_net, B => QBX_TEMPR9_4_net, S =>
|
| 1099 |
|
|
BUFF_12_Y, Y => MX2_292_Y);
|
| 1100 |
|
|
MX2_224 : MX2
|
| 1101 |
|
|
port map(A => QBX_TEMPR10_3_net, B => QBX_TEMPR11_3_net,
|
| 1102 |
|
|
S => BUFF_5_Y, Y => MX2_224_Y);
|
| 1103 |
|
|
MX2_49 : MX2
|
| 1104 |
|
|
port map(A => MX2_272_Y, B => MX2_14_Y, S => BUFF_1_Y, Y =>
|
| 1105 |
|
|
MX2_49_Y);
|
| 1106 |
|
|
MX2_241 : MX2
|
| 1107 |
|
|
port map(A => QBX_TEMPR8_13_net, B => QBX_TEMPR9_13_net,
|
| 1108 |
|
|
S => BUFF_2_Y, Y => MX2_241_Y);
|
| 1109 |
|
|
MX2_247 : MX2
|
| 1110 |
|
|
port map(A => QBX_TEMPR10_0_net, B => QBX_TEMPR11_0_net,
|
| 1111 |
|
|
S => BUFF_23_Y, Y => MX2_247_Y);
|
| 1112 |
|
|
NAND2_ENABLE_ADDRA_3_inst : NAND2
|
| 1113 |
|
|
port map(A => AND2_2_Y, B => NOR2_3_Y, Y =>
|
| 1114 |
|
|
ENABLE_ADDRA_3_net);
|
| 1115 |
|
|
MX2_334 : MX2
|
| 1116 |
|
|
port map(A => QAX_TEMPR12_5_net, B => QAX_TEMPR13_5_net,
|
| 1117 |
|
|
S => BUFF_26_Y, Y => MX2_334_Y);
|
| 1118 |
|
|
MX2_186 : MX2
|
| 1119 |
|
|
port map(A => MX2_400_Y, B => MX2_392_Y, S =>
|
| 1120 |
|
|
ADDRA_FF2_2_net, Y => MX2_186_Y);
|
| 1121 |
|
|
MX2_310 : MX2
|
| 1122 |
|
|
port map(A => QAX_TEMPR2_2_net, B => QAX_TEMPR3_2_net, S =>
|
| 1123 |
|
|
BUFF_21_Y, Y => MX2_310_Y);
|
| 1124 |
|
|
MX2_198 : MX2
|
| 1125 |
|
|
port map(A => QBX_TEMPR12_11_net, B => QBX_TEMPR13_11_net,
|
| 1126 |
|
|
S => BUFF_39_Y, Y => MX2_198_Y);
|
| 1127 |
|
|
MX2_185 : MX2
|
| 1128 |
|
|
port map(A => QAX_TEMPR6_10_net, B => QAX_TEMPR7_10_net,
|
| 1129 |
|
|
S => BUFF_20_Y, Y => MX2_185_Y);
|
| 1130 |
|
|
MX2_407 : MX2
|
| 1131 |
|
|
port map(A => MX2_234_Y, B => MX2_323_Y, S => BUFF_19_Y,
|
| 1132 |
|
|
Y => MX2_407_Y);
|
| 1133 |
|
|
MX2_154 : MX2
|
| 1134 |
|
|
port map(A => QAX_TEMPR6_14_net, B => QAX_TEMPR7_14_net,
|
| 1135 |
|
|
S => BUFF_15_Y, Y => MX2_154_Y);
|
| 1136 |
|
|
NAND2_ENABLE_ADDRA_14_inst : NAND2
|
| 1137 |
|
|
port map(A => AND2A_2_Y, B => AND2_3_Y, Y =>
|
| 1138 |
|
|
ENABLE_ADDRA_14_net);
|
| 1139 |
|
|
NAND2_ENABLE_ADDRB_1_inst : NAND2
|
| 1140 |
|
|
port map(A => AND2A_1_Y, B => NOR2_0_Y, Y =>
|
| 1141 |
|
|
ENABLE_ADDRB_1_net);
|
| 1142 |
|
|
MX2_DOUTA_5_inst : MX2
|
| 1143 |
|
|
port map(A => MX2_128_Y, B => MX2_237_Y, S =>
|
| 1144 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(5));
|
| 1145 |
|
|
NAND2_ENABLE_ADDRA_1_inst : NAND2
|
| 1146 |
|
|
port map(A => AND2A_4_Y, B => NOR2_3_Y, Y =>
|
| 1147 |
|
|
ENABLE_ADDRA_1_net);
|
| 1148 |
|
|
MX2_380 : MX2
|
| 1149 |
|
|
port map(A => MX2_177_Y, B => MX2_320_Y, S =>
|
| 1150 |
|
|
ADDRA_FF2_2_net, Y => MX2_380_Y);
|
| 1151 |
|
|
MX2_358 : MX2
|
| 1152 |
|
|
port map(A => QAX_TEMPR10_15_net, B => QAX_TEMPR11_15_net,
|
| 1153 |
|
|
S => BUFF_9_Y, Y => MX2_358_Y);
|
| 1154 |
|
|
NAND2_ENABLE_ADDRA_9_inst : NAND2
|
| 1155 |
|
|
port map(A => AND2A_4_Y, B => AND2A_3_Y, Y =>
|
| 1156 |
|
|
ENABLE_ADDRA_9_net);
|
| 1157 |
|
|
MX2_353 : MX2
|
| 1158 |
|
|
port map(A => MX2_293_Y, B => MX2_32_Y, S => BUFF_25_Y,
|
| 1159 |
|
|
Y => MX2_353_Y);
|
| 1160 |
|
|
MX2_167 : MX2
|
| 1161 |
|
|
port map(A => MX2_97_Y, B => MX2_220_Y, S => BUFF_8_Y, Y =>
|
| 1162 |
|
|
MX2_167_Y);
|
| 1163 |
|
|
BUFF_6 : BUFF
|
| 1164 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_6_Y);
|
| 1165 |
|
|
MX2_DOUTB_6_inst : MX2
|
| 1166 |
|
|
port map(A => MX2_385_Y, B => MX2_222_Y, S =>
|
| 1167 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(6));
|
| 1168 |
|
|
MX2_DOUTA_1_inst : MX2
|
| 1169 |
|
|
port map(A => MX2_147_Y, B => MX2_354_Y, S =>
|
| 1170 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(1));
|
| 1171 |
|
|
MX2_406 : MX2
|
| 1172 |
|
|
port map(A => QBX_TEMPR4_11_net, B => QBX_TEMPR5_11_net,
|
| 1173 |
|
|
S => BUFF_39_Y, Y => MX2_406_Y);
|
| 1174 |
|
|
ORB_GATE_5_inst : OR2
|
| 1175 |
|
|
port map(A => ENABLE_ADDRB_5_net, B => WEBP, Y =>
|
| 1176 |
|
|
BLKB_EN_5_net);
|
| 1177 |
|
|
MX2_16 : MX2
|
| 1178 |
|
|
port map(A => QAX_TEMPR6_13_net, B => QAX_TEMPR7_13_net,
|
| 1179 |
|
|
S => BUFF_15_Y, Y => MX2_16_Y);
|
| 1180 |
|
|
MX2_294 : MX2
|
| 1181 |
|
|
port map(A => QAX_TEMPR12_15_net, B => QAX_TEMPR13_15_net,
|
| 1182 |
|
|
S => BUFF_9_Y, Y => MX2_294_Y);
|
| 1183 |
|
|
MX2_250 : MX2
|
| 1184 |
|
|
port map(A => QBX_TEMPR2_6_net, B => QBX_TEMPR3_6_net, S =>
|
| 1185 |
|
|
BUFF_6_Y, Y => MX2_250_Y);
|
| 1186 |
|
|
BUFF_39 : BUFF
|
| 1187 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_39_Y);
|
| 1188 |
|
|
MX2_151 : MX2
|
| 1189 |
|
|
port map(A => MX2_79_Y, B => MX2_221_Y, S =>
|
| 1190 |
|
|
ADDRA_FF2_2_net, Y => MX2_151_Y);
|
| 1191 |
|
|
MX2_326 : MX2
|
| 1192 |
|
|
port map(A => MX2_174_Y, B => MX2_15_Y, S =>
|
| 1193 |
|
|
ADDRA_FF2_2_net, Y => MX2_326_Y);
|
| 1194 |
|
|
ORA_GATE_1_inst : OR2
|
| 1195 |
|
|
port map(A => ENABLE_ADDRA_1_net, B => WEAP, Y =>
|
| 1196 |
|
|
BLKA_EN_1_net);
|
| 1197 |
|
|
MX2_57 : MX2
|
| 1198 |
|
|
port map(A => QBX_TEMPR6_11_net, B => QBX_TEMPR7_11_net,
|
| 1199 |
|
|
S => BUFF_39_Y, Y => MX2_57_Y);
|
| 1200 |
|
|
dual_port_memory_R8C0 : RAM4K9
|
| 1201 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1202 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1203 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1204 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1205 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1206 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1207 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1208 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1209 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1210 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1211 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1212 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 1213 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 1214 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1215 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1216 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 1217 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1218 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1219 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1220 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_8_net,
|
| 1221 |
|
|
BLKB => BLKB_EN_8_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1222 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1223 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1224 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR8_3_net, DOUTA2 =>
|
| 1225 |
|
|
QAX_TEMPR8_2_net, DOUTA1 => QAX_TEMPR8_1_net, DOUTA0 =>
|
| 1226 |
|
|
QAX_TEMPR8_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1227 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1228 |
|
|
DOUTB3 => QBX_TEMPR8_3_net, DOUTB2 => QBX_TEMPR8_2_net,
|
| 1229 |
|
|
DOUTB1 => QBX_TEMPR8_1_net, DOUTB0 => QBX_TEMPR8_0_net);
|
| 1230 |
|
|
dual_port_memory_R8C2 : RAM4K9
|
| 1231 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1232 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1233 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1234 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1235 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1236 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1237 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1238 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1239 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1240 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1241 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1242 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 1243 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 1244 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1245 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1246 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 1247 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1248 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1249 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1250 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_8_net,
|
| 1251 |
|
|
BLKB => BLKB_EN_8_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1252 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1253 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1254 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR8_11_net, DOUTA2 =>
|
| 1255 |
|
|
QAX_TEMPR8_10_net, DOUTA1 => QAX_TEMPR8_9_net, DOUTA0 =>
|
| 1256 |
|
|
QAX_TEMPR8_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1257 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1258 |
|
|
DOUTB3 => QBX_TEMPR8_11_net, DOUTB2 => QBX_TEMPR8_10_net,
|
| 1259 |
|
|
DOUTB1 => QBX_TEMPR8_9_net, DOUTB0 => QBX_TEMPR8_8_net);
|
| 1260 |
|
|
MX2_DOUTB_0_inst : MX2
|
| 1261 |
|
|
port map(A => MX2_352_Y, B => MX2_258_Y, S =>
|
| 1262 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(0));
|
| 1263 |
|
|
MX2_8 : MX2
|
| 1264 |
|
|
port map(A => QBX_TEMPR8_14_net, B => QBX_TEMPR9_14_net,
|
| 1265 |
|
|
S => BUFF_2_Y, Y => MX2_8_Y);
|
| 1266 |
|
|
MX2_314 : MX2
|
| 1267 |
|
|
port map(A => QAX_TEMPR2_10_net, B => QAX_TEMPR3_10_net,
|
| 1268 |
|
|
S => BUFF_20_Y, Y => MX2_314_Y);
|
| 1269 |
|
|
MX2_255 : MX2
|
| 1270 |
|
|
port map(A => QBX_TEMPR4_6_net, B => QBX_TEMPR5_6_net, S =>
|
| 1271 |
|
|
BUFF_6_Y, Y => MX2_255_Y);
|
| 1272 |
|
|
dual_port_memory_R0C2 : RAM4K9
|
| 1273 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1274 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1275 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1276 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1277 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1278 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1279 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1280 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1281 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1282 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1283 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1284 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 1285 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 1286 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1287 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1288 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 1289 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1290 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1291 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1292 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_0_net,
|
| 1293 |
|
|
BLKB => BLKB_EN_0_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1294 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1295 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1296 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR0_11_net, DOUTA2 =>
|
| 1297 |
|
|
QAX_TEMPR0_10_net, DOUTA1 => QAX_TEMPR0_9_net, DOUTA0 =>
|
| 1298 |
|
|
QAX_TEMPR0_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1299 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1300 |
|
|
DOUTB3 => QBX_TEMPR0_11_net, DOUTB2 => QBX_TEMPR0_10_net,
|
| 1301 |
|
|
DOUTB1 => QBX_TEMPR0_9_net, DOUTB0 => QBX_TEMPR0_8_net);
|
| 1302 |
|
|
MX2_351 : MX2
|
| 1303 |
|
|
port map(A => MX2_82_Y, B => MX2_362_Y, S =>
|
| 1304 |
|
|
ADDRA_FF2_2_net, Y => MX2_351_Y);
|
| 1305 |
|
|
MX2_97 : MX2
|
| 1306 |
|
|
port map(A => QAX_TEMPR4_12_net, B => QAX_TEMPR5_12_net,
|
| 1307 |
|
|
S => BUFF_37_Y, Y => MX2_97_Y);
|
| 1308 |
|
|
BUFF_13 : BUFF
|
| 1309 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_13_Y);
|
| 1310 |
|
|
BUFF_11 : BUFF
|
| 1311 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_11_Y);
|
| 1312 |
|
|
dual_port_memory_R5C1 : RAM4K9
|
| 1313 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1314 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1315 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1316 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1317 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1318 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1319 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1320 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1321 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1322 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1323 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1324 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 1325 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 1326 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1327 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1328 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 1329 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1330 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1331 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1332 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_5_net,
|
| 1333 |
|
|
BLKB => BLKB_EN_5_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1334 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1335 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1336 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR5_7_net, DOUTA2 =>
|
| 1337 |
|
|
QAX_TEMPR5_6_net, DOUTA1 => QAX_TEMPR5_5_net, DOUTA0 =>
|
| 1338 |
|
|
QAX_TEMPR5_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1339 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1340 |
|
|
DOUTB3 => QBX_TEMPR5_7_net, DOUTB2 => QBX_TEMPR5_6_net,
|
| 1341 |
|
|
DOUTB1 => QBX_TEMPR5_5_net, DOUTB0 => QBX_TEMPR5_4_net);
|
| 1342 |
|
|
ORA_GATE_0_inst : OR2
|
| 1343 |
|
|
port map(A => ENABLE_ADDRA_0_net, B => WEAP, Y =>
|
| 1344 |
|
|
BLKA_EN_0_net);
|
| 1345 |
|
|
ORB_GATE_2_inst : OR2
|
| 1346 |
|
|
port map(A => ENABLE_ADDRB_2_net, B => WEBP, Y =>
|
| 1347 |
|
|
BLKB_EN_2_net);
|
| 1348 |
|
|
AND2A_2 : AND2A
|
| 1349 |
|
|
port map(A => ADDRA(10), B => ADDRA(11), Y => AND2A_2_Y);
|
| 1350 |
|
|
MX2_130 : MX2
|
| 1351 |
|
|
port map(A => MX2_328_Y, B => MX2_332_Y, S => BUFF_38_Y,
|
| 1352 |
|
|
Y => MX2_130_Y);
|
| 1353 |
|
|
dual_port_memory_R11C0 : RAM4K9
|
| 1354 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1355 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1356 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1357 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1358 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1359 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1360 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1361 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1362 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1363 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1364 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1365 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 1366 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 1367 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1368 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1369 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 1370 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1371 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1372 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1373 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_11_net,
|
| 1374 |
|
|
BLKB => BLKB_EN_11_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1375 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1376 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1377 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR11_3_net, DOUTA2 =>
|
| 1378 |
|
|
QAX_TEMPR11_2_net, DOUTA1 => QAX_TEMPR11_1_net, DOUTA0 =>
|
| 1379 |
|
|
QAX_TEMPR11_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1380 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1381 |
|
|
DOUTB3 => QBX_TEMPR11_3_net, DOUTB2 => QBX_TEMPR11_2_net,
|
| 1382 |
|
|
DOUTB1 => QBX_TEMPR11_1_net, DOUTB0 => QBX_TEMPR11_0_net);
|
| 1383 |
|
|
MX2_384 : MX2
|
| 1384 |
|
|
port map(A => MX2_146_Y, B => MX2_301_Y, S => BUFF_27_Y,
|
| 1385 |
|
|
Y => MX2_384_Y);
|
| 1386 |
|
|
MX2_322 : MX2
|
| 1387 |
|
|
port map(A => QAX_TEMPR2_4_net, B => QAX_TEMPR3_4_net, S =>
|
| 1388 |
|
|
BUFF_22_Y, Y => MX2_322_Y);
|
| 1389 |
|
|
MX2_123 : MX2
|
| 1390 |
|
|
port map(A => QAX_TEMPR4_2_net, B => QAX_TEMPR5_2_net, S =>
|
| 1391 |
|
|
BUFF_21_Y, Y => MX2_123_Y);
|
| 1392 |
|
|
dual_port_memory_R8C1 : RAM4K9
|
| 1393 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1394 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1395 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1396 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1397 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1398 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1399 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1400 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1401 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1402 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1403 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1404 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 1405 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 1406 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1407 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1408 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 1409 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1410 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1411 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1412 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_8_net,
|
| 1413 |
|
|
BLKB => BLKB_EN_8_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1414 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1415 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1416 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR8_7_net, DOUTA2 =>
|
| 1417 |
|
|
QAX_TEMPR8_6_net, DOUTA1 => QAX_TEMPR8_5_net, DOUTA0 =>
|
| 1418 |
|
|
QAX_TEMPR8_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1419 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1420 |
|
|
DOUTB3 => QBX_TEMPR8_7_net, DOUTB2 => QBX_TEMPR8_6_net,
|
| 1421 |
|
|
DOUTB1 => QBX_TEMPR8_5_net, DOUTB0 => QBX_TEMPR8_4_net);
|
| 1422 |
|
|
AND2A_1 : AND2A
|
| 1423 |
|
|
port map(A => ADDRB(11), B => ADDRB(10), Y => AND2A_1_Y);
|
| 1424 |
|
|
MX2_415 : MX2
|
| 1425 |
|
|
port map(A => MX2_315_Y, B => MX2_109_Y, S => BUFF_29_Y,
|
| 1426 |
|
|
Y => MX2_415_Y);
|
| 1427 |
|
|
MX2_70 : MX2
|
| 1428 |
|
|
port map(A => MX2_91_Y, B => MX2_280_Y, S => BUFF_30_Y,
|
| 1429 |
|
|
Y => MX2_70_Y);
|
| 1430 |
|
|
ORB_GATE_14_inst : OR2
|
| 1431 |
|
|
port map(A => ENABLE_ADDRB_14_net, B => WEBP, Y =>
|
| 1432 |
|
|
BLKB_EN_14_net);
|
| 1433 |
|
|
MX2_329 : MX2
|
| 1434 |
|
|
port map(A => MX2_211_Y, B => QBX_TEMPR14_6_net, S =>
|
| 1435 |
|
|
BUFF_25_Y, Y => MX2_329_Y);
|
| 1436 |
|
|
BUFF_23 : BUFF
|
| 1437 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_23_Y);
|
| 1438 |
|
|
BUFF_21 : BUFF
|
| 1439 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_21_Y);
|
| 1440 |
|
|
BFF1_3_inst : DFN1
|
| 1441 |
|
|
port map(D => ADDRB(13), CLK => CLKB, Q => ADDRB_FF2_3_net);
|
| 1442 |
|
|
MX2_60 : MX2
|
| 1443 |
|
|
port map(A => MX2_302_Y, B => QBX_TEMPR14_15_net, S =>
|
| 1444 |
|
|
BUFF_13_Y, Y => MX2_60_Y);
|
| 1445 |
|
|
MX2_159 : MX2
|
| 1446 |
|
|
port map(A => MX2_198_Y, B => QBX_TEMPR14_11_net, S =>
|
| 1447 |
|
|
BUFF_19_Y, Y => MX2_159_Y);
|
| 1448 |
|
|
MX2_396 : MX2
|
| 1449 |
|
|
port map(A => QBX_TEMPR10_13_net, B => QBX_TEMPR11_13_net,
|
| 1450 |
|
|
S => BUFF_2_Y, Y => MX2_396_Y);
|
| 1451 |
|
|
MX2_201 : MX2
|
| 1452 |
|
|
port map(A => MX2_355_Y, B => MX2_171_Y, S => BUFF_25_Y,
|
| 1453 |
|
|
Y => MX2_201_Y);
|
| 1454 |
|
|
MX2_207 : MX2
|
| 1455 |
|
|
port map(A => QAX_TEMPR12_13_net, B => QAX_TEMPR13_13_net,
|
| 1456 |
|
|
S => BUFF_15_Y, Y => MX2_207_Y);
|
| 1457 |
|
|
ORA_GATE_4_inst : OR2
|
| 1458 |
|
|
port map(A => ENABLE_ADDRA_4_net, B => WEAP, Y =>
|
| 1459 |
|
|
BLKA_EN_4_net);
|
| 1460 |
|
|
MX2_355 : MX2
|
| 1461 |
|
|
port map(A => QBX_TEMPR8_7_net, B => QBX_TEMPR9_7_net, S =>
|
| 1462 |
|
|
BUFF_3_Y, Y => MX2_355_Y);
|
| 1463 |
|
|
MX2_177 : MX2
|
| 1464 |
|
|
port map(A => MX2_54_Y, B => MX2_266_Y, S => BUFF_32_Y,
|
| 1465 |
|
|
Y => MX2_177_Y);
|
| 1466 |
|
|
NAND2_ENABLE_ADDRB_2_inst : NAND2
|
| 1467 |
|
|
port map(A => AND2A_7_Y, B => NOR2_0_Y, Y =>
|
| 1468 |
|
|
ENABLE_ADDRB_2_net);
|
| 1469 |
|
|
MX2_84 : MX2
|
| 1470 |
|
|
port map(A => QBX_TEMPR2_8_net, B => QBX_TEMPR3_8_net, S =>
|
| 1471 |
|
|
BUFF_34_Y, Y => MX2_84_Y);
|
| 1472 |
|
|
ORA_GATE_14_inst : OR2
|
| 1473 |
|
|
port map(A => ENABLE_ADDRA_14_net, B => WEAP, Y =>
|
| 1474 |
|
|
BLKA_EN_14_net);
|
| 1475 |
|
|
MX2_392 : MX2
|
| 1476 |
|
|
port map(A => MX2_129_Y, B => MX2_185_Y, S => BUFF_32_Y,
|
| 1477 |
|
|
Y => MX2_392_Y);
|
| 1478 |
|
|
dual_port_memory_R6C2 : RAM4K9
|
| 1479 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1480 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1481 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1482 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1483 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1484 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1485 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1486 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1487 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1488 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1489 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1490 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 1491 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 1492 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1493 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1494 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 1495 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1496 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1497 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1498 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_6_net,
|
| 1499 |
|
|
BLKB => BLKB_EN_6_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1500 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1501 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1502 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR6_11_net, DOUTA2 =>
|
| 1503 |
|
|
QAX_TEMPR6_10_net, DOUTA1 => QAX_TEMPR6_9_net, DOUTA0 =>
|
| 1504 |
|
|
QAX_TEMPR6_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1505 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1506 |
|
|
DOUTB3 => QBX_TEMPR6_11_net, DOUTB2 => QBX_TEMPR6_10_net,
|
| 1507 |
|
|
DOUTB1 => QBX_TEMPR6_9_net, DOUTB0 => QBX_TEMPR6_8_net);
|
| 1508 |
|
|
ORB_GATE_7_inst : OR2
|
| 1509 |
|
|
port map(A => ENABLE_ADDRB_7_net, B => WEBP, Y =>
|
| 1510 |
|
|
BLKB_EN_7_net);
|
| 1511 |
|
|
MX2_193 : MX2
|
| 1512 |
|
|
port map(A => QAX_TEMPR8_0_net, B => QAX_TEMPR9_0_net, S =>
|
| 1513 |
|
|
BUFF_18_Y, Y => MX2_193_Y);
|
| 1514 |
|
|
dual_port_memory_R6C1 : RAM4K9
|
| 1515 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1516 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1517 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1518 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1519 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1520 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1521 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1522 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1523 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1524 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1525 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1526 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 1527 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 1528 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1529 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1530 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 1531 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1532 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1533 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1534 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_6_net,
|
| 1535 |
|
|
BLKB => BLKB_EN_6_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1536 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1537 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1538 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR6_7_net, DOUTA2 =>
|
| 1539 |
|
|
QAX_TEMPR6_6_net, DOUTA1 => QAX_TEMPR6_5_net, DOUTA0 =>
|
| 1540 |
|
|
QAX_TEMPR6_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1541 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1542 |
|
|
DOUTB3 => QBX_TEMPR6_7_net, DOUTB2 => QBX_TEMPR6_6_net,
|
| 1543 |
|
|
DOUTB1 => QBX_TEMPR6_5_net, DOUTB0 => QBX_TEMPR6_4_net);
|
| 1544 |
|
|
AFF1_2_inst : DFN1
|
| 1545 |
|
|
port map(D => ADDRA(12), CLK => CLKA, Q => ADDRA_FF2_2_net);
|
| 1546 |
|
|
MX2_122 : MX2
|
| 1547 |
|
|
port map(A => QAX_TEMPR6_11_net, B => QAX_TEMPR7_11_net,
|
| 1548 |
|
|
S => BUFF_14_Y, Y => MX2_122_Y);
|
| 1549 |
|
|
MX2_399 : MX2
|
| 1550 |
|
|
port map(A => MX2_369_Y, B => MX2_296_Y, S => BUFF_8_Y,
|
| 1551 |
|
|
Y => MX2_399_Y);
|
| 1552 |
|
|
MX2_17 : MX2
|
| 1553 |
|
|
port map(A => QAX_TEMPR4_5_net, B => QAX_TEMPR5_5_net, S =>
|
| 1554 |
|
|
BUFF_22_Y, Y => MX2_17_Y);
|
| 1555 |
|
|
MX2_76 : MX2
|
| 1556 |
|
|
port map(A => QBX_TEMPR6_9_net, B => QBX_TEMPR7_9_net, S =>
|
| 1557 |
|
|
BUFF_28_Y, Y => MX2_76_Y);
|
| 1558 |
|
|
MX2_246 : MX2
|
| 1559 |
|
|
port map(A => QAX_TEMPR8_9_net, B => QAX_TEMPR9_9_net, S =>
|
| 1560 |
|
|
BUFF_20_Y, Y => MX2_246_Y);
|
| 1561 |
|
|
dual_port_memory_R13C0 : RAM4K9
|
| 1562 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1563 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1564 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1565 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1566 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1567 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1568 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1569 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1570 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1571 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1572 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1573 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 1574 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 1575 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1576 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1577 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 1578 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1579 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1580 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1581 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_13_net,
|
| 1582 |
|
|
BLKB => BLKB_EN_13_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1583 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1584 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1585 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR13_3_net, DOUTA2 =>
|
| 1586 |
|
|
QAX_TEMPR13_2_net, DOUTA1 => QAX_TEMPR13_1_net, DOUTA0 =>
|
| 1587 |
|
|
QAX_TEMPR13_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1588 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1589 |
|
|
DOUTB3 => QBX_TEMPR13_3_net, DOUTB2 => QBX_TEMPR13_2_net,
|
| 1590 |
|
|
DOUTB1 => QBX_TEMPR13_1_net, DOUTB0 => QBX_TEMPR13_0_net);
|
| 1591 |
|
|
MX2_53 : MX2
|
| 1592 |
|
|
port map(A => QAX_TEMPR8_11_net, B => QAX_TEMPR9_11_net,
|
| 1593 |
|
|
S => BUFF_14_Y, Y => MX2_53_Y);
|
| 1594 |
|
|
MX2_110 : MX2
|
| 1595 |
|
|
port map(A => MX2_317_Y, B => MX2_322_Y, S => BUFF_35_Y,
|
| 1596 |
|
|
Y => MX2_110_Y);
|
| 1597 |
|
|
MX2_66 : MX2
|
| 1598 |
|
|
port map(A => QBX_TEMPR6_7_net, B => QBX_TEMPR7_7_net, S =>
|
| 1599 |
|
|
BUFF_3_Y, Y => MX2_66_Y);
|
| 1600 |
|
|
MX2_252 : MX2
|
| 1601 |
|
|
port map(A => MX2_215_Y, B => MX2_84_Y, S => BUFF_1_Y, Y =>
|
| 1602 |
|
|
MX2_252_Y);
|
| 1603 |
|
|
MX2_45 : MX2
|
| 1604 |
|
|
port map(A => MX2_403_Y, B => QAX_TEMPR14_1_net, S =>
|
| 1605 |
|
|
BUFF_38_Y, Y => MX2_45_Y);
|
| 1606 |
|
|
MX2_93 : MX2
|
| 1607 |
|
|
port map(A => MX2_253_Y, B => MX2_161_Y, S =>
|
| 1608 |
|
|
ADDRB_FF2_2_net, Y => MX2_93_Y);
|
| 1609 |
|
|
MX2_261 : MX2
|
| 1610 |
|
|
port map(A => MX2_241_Y, B => MX2_396_Y, S => BUFF_4_Y,
|
| 1611 |
|
|
Y => MX2_261_Y);
|
| 1612 |
|
|
MX2_267 : MX2
|
| 1613 |
|
|
port map(A => QBX_TEMPR8_1_net, B => QBX_TEMPR9_1_net, S =>
|
| 1614 |
|
|
BUFF_33_Y, Y => MX2_267_Y);
|
| 1615 |
|
|
MX2_158 : MX2
|
| 1616 |
|
|
port map(A => QAX_TEMPR12_10_net, B => QAX_TEMPR13_10_net,
|
| 1617 |
|
|
S => BUFF_14_Y, Y => MX2_158_Y);
|
| 1618 |
|
|
MX2_180 : MX2
|
| 1619 |
|
|
port map(A => QBX_TEMPR2_1_net, B => QBX_TEMPR3_1_net, S =>
|
| 1620 |
|
|
BUFF_23_Y, Y => MX2_180_Y);
|
| 1621 |
|
|
AND2A_4 : AND2A
|
| 1622 |
|
|
port map(A => ADDRA(11), B => ADDRA(10), Y => AND2A_4_Y);
|
| 1623 |
|
|
dual_port_memory_R9C1 : RAM4K9
|
| 1624 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1625 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1626 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1627 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1628 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1629 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1630 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1631 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1632 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1633 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1634 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1635 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 1636 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 1637 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1638 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1639 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 1640 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1641 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1642 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1643 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_9_net,
|
| 1644 |
|
|
BLKB => BLKB_EN_9_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1645 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1646 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1647 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR9_7_net, DOUTA2 =>
|
| 1648 |
|
|
QAX_TEMPR9_6_net, DOUTA1 => QAX_TEMPR9_5_net, DOUTA0 =>
|
| 1649 |
|
|
QAX_TEMPR9_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1650 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1651 |
|
|
DOUTB3 => QBX_TEMPR9_7_net, DOUTB2 => QBX_TEMPR9_6_net,
|
| 1652 |
|
|
DOUTB1 => QBX_TEMPR9_5_net, DOUTB0 => QBX_TEMPR9_4_net);
|
| 1653 |
|
|
MX2_DOUTB_14_inst : MX2
|
| 1654 |
|
|
port map(A => MX2_93_Y, B => MX2_175_Y, S =>
|
| 1655 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(14));
|
| 1656 |
|
|
MX2_144 : MX2
|
| 1657 |
|
|
port map(A => MX2_112_Y, B => MX2_137_Y, S => BUFF_29_Y,
|
| 1658 |
|
|
Y => MX2_144_Y);
|
| 1659 |
|
|
BUFF_17 : BUFF
|
| 1660 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_17_Y);
|
| 1661 |
|
|
MX2_348 : MX2
|
| 1662 |
|
|
port map(A => MX2_2_Y, B => MX2_16_Y, S => BUFF_8_Y, Y =>
|
| 1663 |
|
|
MX2_348_Y);
|
| 1664 |
|
|
MX2_192 : MX2
|
| 1665 |
|
|
port map(A => QBX_TEMPR12_14_net, B => QBX_TEMPR13_14_net,
|
| 1666 |
|
|
S => BUFF_16_Y, Y => MX2_192_Y);
|
| 1667 |
|
|
MX2_343 : MX2
|
| 1668 |
|
|
port map(A => MX2_172_Y, B => MX2_152_Y, S => BUFF_4_Y,
|
| 1669 |
|
|
Y => MX2_343_Y);
|
| 1670 |
|
|
dual_port_memory_R7C3 : RAM4K9
|
| 1671 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1672 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1673 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1674 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1675 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1676 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1677 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1678 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1679 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1680 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1681 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1682 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 1683 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 1684 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1685 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1686 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 1687 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1688 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1689 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1690 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_7_net,
|
| 1691 |
|
|
BLKB => BLKB_EN_7_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1692 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1693 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1694 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR7_15_net, DOUTA2 =>
|
| 1695 |
|
|
QAX_TEMPR7_14_net, DOUTA1 => QAX_TEMPR7_13_net, DOUTA0 =>
|
| 1696 |
|
|
QAX_TEMPR7_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1697 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1698 |
|
|
DOUTB3 => QBX_TEMPR7_15_net, DOUTB2 => QBX_TEMPR7_14_net,
|
| 1699 |
|
|
DOUTB1 => QBX_TEMPR7_13_net, DOUTB0 => QBX_TEMPR7_12_net);
|
| 1700 |
|
|
MX2_400 : MX2
|
| 1701 |
|
|
port map(A => MX2_162_Y, B => MX2_314_Y, S => BUFF_32_Y,
|
| 1702 |
|
|
Y => MX2_400_Y);
|
| 1703 |
|
|
dual_port_memory_R14C0 : RAM4K9
|
| 1704 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1705 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1706 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1707 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1708 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1709 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1710 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1711 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1712 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1713 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1714 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1715 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 1716 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 1717 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1718 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1719 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 1720 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1721 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1722 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1723 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_14_net,
|
| 1724 |
|
|
BLKB => BLKB_EN_14_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1725 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1726 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1727 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR14_3_net, DOUTA2 =>
|
| 1728 |
|
|
QAX_TEMPR14_2_net, DOUTA1 => QAX_TEMPR14_1_net, DOUTA0 =>
|
| 1729 |
|
|
QAX_TEMPR14_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1730 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1731 |
|
|
DOUTB3 => QBX_TEMPR14_3_net, DOUTB2 => QBX_TEMPR14_2_net,
|
| 1732 |
|
|
DOUTB1 => QBX_TEMPR14_1_net, DOUTB0 => QBX_TEMPR14_0_net);
|
| 1733 |
|
|
BUFF_27 : BUFF
|
| 1734 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_27_Y);
|
| 1735 |
|
|
MX2_137 : MX2
|
| 1736 |
|
|
port map(A => QBX_TEMPR10_5_net, B => QBX_TEMPR11_5_net,
|
| 1737 |
|
|
S => BUFF_6_Y, Y => MX2_137_Y);
|
| 1738 |
|
|
BUFF_3 : BUFF
|
| 1739 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_3_Y);
|
| 1740 |
|
|
MX2_254 : MX2
|
| 1741 |
|
|
port map(A => MX2_249_Y, B => MX2_342_Y, S =>
|
| 1742 |
|
|
ADDRB_FF2_2_net, Y => MX2_254_Y);
|
| 1743 |
|
|
MX2_22 : MX2
|
| 1744 |
|
|
port map(A => QAX_TEMPR12_7_net, B => QAX_TEMPR13_7_net,
|
| 1745 |
|
|
S => BUFF_10_Y, Y => MX2_22_Y);
|
| 1746 |
|
|
ORA_GATE_6_inst : OR2
|
| 1747 |
|
|
port map(A => ENABLE_ADDRA_6_net, B => WEAP, Y =>
|
| 1748 |
|
|
BLKA_EN_6_net);
|
| 1749 |
|
|
BUFF_38 : BUFF
|
| 1750 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_38_Y);
|
| 1751 |
|
|
MX2_51 : MX2
|
| 1752 |
|
|
port map(A => QAX_TEMPR8_2_net, B => QAX_TEMPR9_2_net, S =>
|
| 1753 |
|
|
BUFF_21_Y, Y => MX2_51_Y);
|
| 1754 |
|
|
MX2_240 : MX2
|
| 1755 |
|
|
port map(A => QAX_TEMPR8_1_net, B => QAX_TEMPR9_1_net, S =>
|
| 1756 |
|
|
BUFF_21_Y, Y => MX2_240_Y);
|
| 1757 |
|
|
MX2_413 : MX2
|
| 1758 |
|
|
port map(A => MX2_388_Y, B => MX2_305_Y, S => BUFF_35_Y,
|
| 1759 |
|
|
Y => MX2_413_Y);
|
| 1760 |
|
|
MX2_13 : MX2
|
| 1761 |
|
|
port map(A => MX2_74_Y, B => MX2_408_Y, S => BUFF_4_Y, Y =>
|
| 1762 |
|
|
MX2_13_Y);
|
| 1763 |
|
|
MX2_91 : MX2
|
| 1764 |
|
|
port map(A => QAX_TEMPR0_15_net, B => QAX_TEMPR1_15_net,
|
| 1765 |
|
|
S => BUFF_9_Y, Y => MX2_91_Y);
|
| 1766 |
|
|
MX2_141 : MX2
|
| 1767 |
|
|
port map(A => MX2_281_Y, B => MX2_191_Y, S =>
|
| 1768 |
|
|
ADDRB_FF2_2_net, Y => MX2_141_Y);
|
| 1769 |
|
|
MX2_58 : MX2
|
| 1770 |
|
|
port map(A => MX2_18_Y, B => QBX_TEMPR14_2_net, S =>
|
| 1771 |
|
|
BUFF_7_Y, Y => MX2_58_Y);
|
| 1772 |
|
|
dual_port_memory_R1C3 : RAM4K9
|
| 1773 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1774 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1775 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1776 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1777 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1778 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1779 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1780 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1781 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1782 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1783 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1784 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 1785 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 1786 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1787 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1788 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 1789 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1790 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1791 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1792 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_1_net,
|
| 1793 |
|
|
BLKB => BLKB_EN_1_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1794 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1795 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1796 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR1_15_net, DOUTA2 =>
|
| 1797 |
|
|
QAX_TEMPR1_14_net, DOUTA1 => QAX_TEMPR1_13_net, DOUTA0 =>
|
| 1798 |
|
|
QAX_TEMPR1_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1799 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1800 |
|
|
DOUTB3 => QBX_TEMPR1_15_net, DOUTB2 => QBX_TEMPR1_14_net,
|
| 1801 |
|
|
DOUTB1 => QBX_TEMPR1_13_net, DOUTB0 => QBX_TEMPR1_12_net);
|
| 1802 |
|
|
MX2_77 : MX2
|
| 1803 |
|
|
port map(A => QBX_TEMPR8_9_net, B => QBX_TEMPR9_9_net, S =>
|
| 1804 |
|
|
BUFF_28_Y, Y => MX2_77_Y);
|
| 1805 |
|
|
dual_port_memory_R3C3 : RAM4K9
|
| 1806 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1807 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1808 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1809 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1810 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1811 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1812 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1813 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1814 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1815 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1816 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1817 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 1818 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 1819 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1820 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1821 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 1822 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1823 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1824 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1825 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_3_net,
|
| 1826 |
|
|
BLKB => BLKB_EN_3_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1827 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1828 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1829 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR3_15_net, DOUTA2 =>
|
| 1830 |
|
|
QAX_TEMPR3_14_net, DOUTA1 => QAX_TEMPR3_13_net, DOUTA0 =>
|
| 1831 |
|
|
QAX_TEMPR3_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1832 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1833 |
|
|
DOUTB3 => QBX_TEMPR3_15_net, DOUTB2 => QBX_TEMPR3_14_net,
|
| 1834 |
|
|
DOUTB1 => QBX_TEMPR3_13_net, DOUTB0 => QBX_TEMPR3_12_net);
|
| 1835 |
|
|
MX2_98 : MX2
|
| 1836 |
|
|
port map(A => MX2_178_Y, B => MX2_235_Y, S => BUFF_35_Y,
|
| 1837 |
|
|
Y => MX2_98_Y);
|
| 1838 |
|
|
MX2_80 : MX2
|
| 1839 |
|
|
port map(A => QBX_TEMPR0_10_net, B => QBX_TEMPR1_10_net,
|
| 1840 |
|
|
S => BUFF_28_Y, Y => MX2_80_Y);
|
| 1841 |
|
|
MX2_245 : MX2
|
| 1842 |
|
|
port map(A => QBX_TEMPR2_12_net, B => QBX_TEMPR3_12_net,
|
| 1843 |
|
|
S => BUFF_24_Y, Y => MX2_245_Y);
|
| 1844 |
|
|
MX2_229 : MX2
|
| 1845 |
|
|
port map(A => QBX_TEMPR2_10_net, B => QBX_TEMPR3_10_net,
|
| 1846 |
|
|
S => BUFF_28_Y, Y => MX2_229_Y);
|
| 1847 |
|
|
MX2_341 : MX2
|
| 1848 |
|
|
port map(A => QBX_TEMPR4_8_net, B => QBX_TEMPR5_8_net, S =>
|
| 1849 |
|
|
BUFF_34_Y, Y => MX2_341_Y);
|
| 1850 |
|
|
MX2_DOUTA_11_inst : MX2
|
| 1851 |
|
|
port map(A => MX2_370_Y, B => MX2_78_Y, S =>
|
| 1852 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(11));
|
| 1853 |
|
|
MX2_411 : MX2
|
| 1854 |
|
|
port map(A => MX2_283_Y, B => MX2_145_Y, S => BUFF_7_Y,
|
| 1855 |
|
|
Y => MX2_411_Y);
|
| 1856 |
|
|
AND2_1 : AND2
|
| 1857 |
|
|
port map(A => ADDRB(11), B => ADDRB(10), Y => AND2_1_Y);
|
| 1858 |
|
|
ORB_GATE_8_inst : OR2
|
| 1859 |
|
|
port map(A => ENABLE_ADDRB_8_net, B => WEBP, Y =>
|
| 1860 |
|
|
BLKB_EN_8_net);
|
| 1861 |
|
|
MX2_67 : MX2
|
| 1862 |
|
|
port map(A => MX2_8_Y, B => MX2_297_Y, S => BUFF_13_Y, Y =>
|
| 1863 |
|
|
MX2_67_Y);
|
| 1864 |
|
|
NAND2_ENABLE_ADDRB_10_inst : NAND2
|
| 1865 |
|
|
port map(A => AND2A_7_Y, B => AND2A_6_Y, Y =>
|
| 1866 |
|
|
ENABLE_ADDRB_10_net);
|
| 1867 |
|
|
NAND2_ENABLE_ADDRB_11_inst : NAND2
|
| 1868 |
|
|
port map(A => AND2_1_Y, B => AND2A_6_Y, Y =>
|
| 1869 |
|
|
ENABLE_ADDRB_11_net);
|
| 1870 |
|
|
MX2_206 : MX2
|
| 1871 |
|
|
port map(A => MX2_7_Y, B => MX2_34_Y, S => BUFF_4_Y, Y =>
|
| 1872 |
|
|
MX2_206_Y);
|
| 1873 |
|
|
MX2_271 : MX2
|
| 1874 |
|
|
port map(A => MX2_110_Y, B => MX2_181_Y, S =>
|
| 1875 |
|
|
ADDRA_FF2_2_net, Y => MX2_271_Y);
|
| 1876 |
|
|
BUFF_5 : BUFF
|
| 1877 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_5_Y);
|
| 1878 |
|
|
MX2_29 : MX2
|
| 1879 |
|
|
port map(A => QAX_TEMPR4_1_net, B => QAX_TEMPR5_1_net, S =>
|
| 1880 |
|
|
BUFF_18_Y, Y => MX2_29_Y);
|
| 1881 |
|
|
MX2_277 : MX2
|
| 1882 |
|
|
port map(A => QBX_TEMPR6_4_net, B => QBX_TEMPR7_4_net, S =>
|
| 1883 |
|
|
BUFF_12_Y, Y => MX2_277_Y);
|
| 1884 |
|
|
dual_port_memory_R1C0 : RAM4K9
|
| 1885 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1886 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1887 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1888 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1889 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1890 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1891 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1892 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1893 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1894 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1895 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1896 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 1897 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 1898 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1899 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1900 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 1901 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1902 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1903 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1904 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_1_net,
|
| 1905 |
|
|
BLKB => BLKB_EN_1_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1906 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1907 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1908 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR1_3_net, DOUTA2 =>
|
| 1909 |
|
|
QAX_TEMPR1_2_net, DOUTA1 => QAX_TEMPR1_1_net, DOUTA0 =>
|
| 1910 |
|
|
QAX_TEMPR1_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1911 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1912 |
|
|
DOUTB3 => QBX_TEMPR1_3_net, DOUTB2 => QBX_TEMPR1_2_net,
|
| 1913 |
|
|
DOUTB1 => QBX_TEMPR1_1_net, DOUTB0 => QBX_TEMPR1_0_net);
|
| 1914 |
|
|
MX2_356 : MX2
|
| 1915 |
|
|
port map(A => MX2_81_Y, B => MX2_154_Y, S => BUFF_30_Y,
|
| 1916 |
|
|
Y => MX2_356_Y);
|
| 1917 |
|
|
MX2_4 : MX2
|
| 1918 |
|
|
port map(A => QBX_TEMPR2_5_net, B => QBX_TEMPR3_5_net, S =>
|
| 1919 |
|
|
BUFF_12_Y, Y => MX2_4_Y);
|
| 1920 |
|
|
MX2_DOUTA_6_inst : MX2
|
| 1921 |
|
|
port map(A => MX2_170_Y, B => MX2_216_Y, S =>
|
| 1922 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(6));
|
| 1923 |
|
|
MX2_327 : MX2
|
| 1924 |
|
|
port map(A => MX2_118_Y, B => MX2_363_Y, S =>
|
| 1925 |
|
|
ADDRA_FF2_2_net, Y => MX2_327_Y);
|
| 1926 |
|
|
NAND2_ENABLE_ADDRB_12_inst : NAND2
|
| 1927 |
|
|
port map(A => NOR2_1_Y, B => AND2_0_Y, Y =>
|
| 1928 |
|
|
ENABLE_ADDRB_12_net);
|
| 1929 |
|
|
MX2_149 : MX2
|
| 1930 |
|
|
port map(A => MX2_25_Y, B => MX2_239_Y, S => BUFF_30_Y,
|
| 1931 |
|
|
Y => MX2_149_Y);
|
| 1932 |
|
|
NOR2_1 : NOR2
|
| 1933 |
|
|
port map(A => ADDRB(11), B => ADDRB(10), Y => NOR2_1_Y);
|
| 1934 |
|
|
MX2_117 : MX2
|
| 1935 |
|
|
port map(A => QAX_TEMPR0_7_net, B => QAX_TEMPR1_7_net, S =>
|
| 1936 |
|
|
BUFF_10_Y, Y => MX2_117_Y);
|
| 1937 |
|
|
dual_port_memory_R2C3 : RAM4K9
|
| 1938 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1939 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1940 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1941 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1942 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1943 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1944 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1945 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1946 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1947 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1948 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1949 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 1950 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 1951 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1952 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1953 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 1954 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1955 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1956 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1957 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_2_net,
|
| 1958 |
|
|
BLKB => BLKB_EN_2_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1959 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1960 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1961 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR2_15_net, DOUTA2 =>
|
| 1962 |
|
|
QAX_TEMPR2_14_net, DOUTA1 => QAX_TEMPR2_13_net, DOUTA0 =>
|
| 1963 |
|
|
QAX_TEMPR2_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1964 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1965 |
|
|
DOUTB3 => QBX_TEMPR2_15_net, DOUTB2 => QBX_TEMPR2_14_net,
|
| 1966 |
|
|
DOUTB1 => QBX_TEMPR2_13_net, DOUTB0 => QBX_TEMPR2_12_net);
|
| 1967 |
|
|
dual_port_memory_R0C0 : RAM4K9
|
| 1968 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 1969 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 1970 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 1971 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 1972 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 1973 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 1974 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 1975 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 1976 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 1977 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 1978 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 1979 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 1980 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 1981 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 1982 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 1983 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 1984 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 1985 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 1986 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 1987 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_0_net,
|
| 1988 |
|
|
BLKB => BLKB_EN_0_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 1989 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 1990 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 1991 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR0_3_net, DOUTA2 =>
|
| 1992 |
|
|
QAX_TEMPR0_2_net, DOUTA1 => QAX_TEMPR0_1_net, DOUTA0 =>
|
| 1993 |
|
|
QAX_TEMPR0_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 1994 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 1995 |
|
|
DOUTB3 => QBX_TEMPR0_3_net, DOUTB2 => QBX_TEMPR0_2_net,
|
| 1996 |
|
|
DOUTB1 => QBX_TEMPR0_1_net, DOUTB0 => QBX_TEMPR0_0_net);
|
| 1997 |
|
|
MX2_223 : MX2
|
| 1998 |
|
|
port map(A => QAX_TEMPR10_2_net, B => QAX_TEMPR11_2_net,
|
| 1999 |
|
|
S => BUFF_0_Y, Y => MX2_223_Y);
|
| 2000 |
|
|
BUFF_19 : BUFF
|
| 2001 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_19_Y);
|
| 2002 |
|
|
dual_port_memory_R13C2 : RAM4K9
|
| 2003 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2004 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2005 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2006 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2007 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2008 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2009 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2010 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2011 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2012 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2013 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2014 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 2015 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 2016 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2017 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2018 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 2019 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2020 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2021 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2022 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_13_net,
|
| 2023 |
|
|
BLKB => BLKB_EN_13_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2024 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2025 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2026 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR13_11_net, DOUTA2 =>
|
| 2027 |
|
|
QAX_TEMPR13_10_net, DOUTA1 => QAX_TEMPR13_9_net,
|
| 2028 |
|
|
DOUTA0 => QAX_TEMPR13_8_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 2029 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2030 |
|
|
DOUTB3 => QBX_TEMPR13_11_net, DOUTB2 =>
|
| 2031 |
|
|
QBX_TEMPR13_10_net, DOUTB1 => QBX_TEMPR13_9_net,
|
| 2032 |
|
|
DOUTB0 => QBX_TEMPR13_8_net);
|
| 2033 |
|
|
MX2_DOUTA_12_inst : MX2
|
| 2034 |
|
|
port map(A => MX2_260_Y, B => MX2_151_Y, S =>
|
| 2035 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(12));
|
| 2036 |
|
|
MX2_32 : MX2
|
| 2037 |
|
|
port map(A => QBX_TEMPR10_6_net, B => QBX_TEMPR11_6_net,
|
| 2038 |
|
|
S => BUFF_3_Y, Y => MX2_32_Y);
|
| 2039 |
|
|
MX2_187 : MX2
|
| 2040 |
|
|
port map(A => QAX_TEMPR12_9_net, B => QAX_TEMPR13_9_net,
|
| 2041 |
|
|
S => BUFF_20_Y, Y => MX2_187_Y);
|
| 2042 |
|
|
BFF1_1_inst : DFN1
|
| 2043 |
|
|
port map(D => ADDRB(11), CLK => CLKB, Q => ADDRB_FF2_1_net);
|
| 2044 |
|
|
MX2_345 : MX2
|
| 2045 |
|
|
port map(A => MX2_262_Y, B => MX2_75_Y, S => BUFF_30_Y,
|
| 2046 |
|
|
Y => MX2_345_Y);
|
| 2047 |
|
|
AND2A_6 : AND2A
|
| 2048 |
|
|
port map(A => ADDRB(12), B => ADDRB(13), Y => AND2A_6_Y);
|
| 2049 |
|
|
MX2_104 : MX2
|
| 2050 |
|
|
port map(A => MX2_102_Y, B => MX2_58_Y, S =>
|
| 2051 |
|
|
ADDRB_FF2_2_net, Y => MX2_104_Y);
|
| 2052 |
|
|
MX2_299 : MX2
|
| 2053 |
|
|
port map(A => QBX_TEMPR4_9_net, B => QBX_TEMPR5_9_net, S =>
|
| 2054 |
|
|
BUFF_34_Y, Y => MX2_299_Y);
|
| 2055 |
|
|
MX2_352 : MX2
|
| 2056 |
|
|
port map(A => MX2_21_Y, B => MX2_47_Y, S => ADDRB_FF2_2_net,
|
| 2057 |
|
|
Y => MX2_352_Y);
|
| 2058 |
|
|
MX2_86 : MX2
|
| 2059 |
|
|
port map(A => QAX_TEMPR10_6_net, B => QAX_TEMPR11_6_net,
|
| 2060 |
|
|
S => BUFF_10_Y, Y => MX2_86_Y);
|
| 2061 |
|
|
MX2_11 : MX2
|
| 2062 |
|
|
port map(A => MX2_217_Y, B => MX2_264_Y, S => BUFF_8_Y,
|
| 2063 |
|
|
Y => MX2_11_Y);
|
| 2064 |
|
|
MX2_153 : MX2
|
| 2065 |
|
|
port map(A => MX2_73_Y, B => QAX_TEMPR14_3_net, S =>
|
| 2066 |
|
|
BUFF_17_Y, Y => MX2_153_Y);
|
| 2067 |
|
|
MX2_308 : MX2
|
| 2068 |
|
|
port map(A => QAX_TEMPR12_12_net, B => QAX_TEMPR13_12_net,
|
| 2069 |
|
|
S => BUFF_37_Y, Y => MX2_308_Y);
|
| 2070 |
|
|
BUFF_29 : BUFF
|
| 2071 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_29_Y);
|
| 2072 |
|
|
MX2_359 : MX2
|
| 2073 |
|
|
port map(A => QBX_TEMPR0_12_net, B => QBX_TEMPR1_12_net,
|
| 2074 |
|
|
S => BUFF_24_Y, Y => MX2_359_Y);
|
| 2075 |
|
|
dual_port_memory_R12C0 : RAM4K9
|
| 2076 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2077 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2078 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2079 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2080 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2081 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2082 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2083 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2084 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2085 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2086 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2087 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 2088 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 2089 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2090 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2091 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 2092 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2093 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2094 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2095 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_12_net,
|
| 2096 |
|
|
BLKB => BLKB_EN_12_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2097 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2098 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2099 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR12_3_net, DOUTA2 =>
|
| 2100 |
|
|
QAX_TEMPR12_2_net, DOUTA1 => QAX_TEMPR12_1_net, DOUTA0 =>
|
| 2101 |
|
|
QAX_TEMPR12_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2102 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2103 |
|
|
DOUTB3 => QBX_TEMPR12_3_net, DOUTB2 => QBX_TEMPR12_2_net,
|
| 2104 |
|
|
DOUTB1 => QBX_TEMPR12_1_net, DOUTB0 => QBX_TEMPR12_0_net);
|
| 2105 |
|
|
MX2_303 : MX2
|
| 2106 |
|
|
port map(A => QAX_TEMPR2_3_net, B => QAX_TEMPR3_3_net, S =>
|
| 2107 |
|
|
BUFF_0_Y, Y => MX2_303_Y);
|
| 2108 |
|
|
MX2_228 : MX2
|
| 2109 |
|
|
port map(A => QAX_TEMPR8_5_net, B => QAX_TEMPR9_5_net, S =>
|
| 2110 |
|
|
BUFF_26_Y, Y => MX2_228_Y);
|
| 2111 |
|
|
MX2_402 : MX2
|
| 2112 |
|
|
port map(A => QAX_TEMPR0_9_net, B => QAX_TEMPR1_9_net, S =>
|
| 2113 |
|
|
BUFF_11_Y, Y => MX2_402_Y);
|
| 2114 |
|
|
MX2_18 : MX2
|
| 2115 |
|
|
port map(A => QBX_TEMPR12_2_net, B => QBX_TEMPR13_2_net,
|
| 2116 |
|
|
S => BUFF_5_Y, Y => MX2_18_Y);
|
| 2117 |
|
|
MX2_266 : MX2
|
| 2118 |
|
|
port map(A => QAX_TEMPR10_10_net, B => QAX_TEMPR11_10_net,
|
| 2119 |
|
|
S => BUFF_14_Y, Y => MX2_266_Y);
|
| 2120 |
|
|
dual_port_memory_R12C2 : RAM4K9
|
| 2121 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2122 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2123 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2124 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2125 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2126 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2127 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2128 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2129 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2130 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2131 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2132 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 2133 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 2134 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2135 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2136 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 2137 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2138 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2139 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2140 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_12_net,
|
| 2141 |
|
|
BLKB => BLKB_EN_12_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2142 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2143 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2144 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR12_11_net, DOUTA2 =>
|
| 2145 |
|
|
QAX_TEMPR12_10_net, DOUTA1 => QAX_TEMPR12_9_net,
|
| 2146 |
|
|
DOUTA0 => QAX_TEMPR12_8_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 2147 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2148 |
|
|
DOUTB3 => QBX_TEMPR12_11_net, DOUTB2 =>
|
| 2149 |
|
|
QBX_TEMPR12_10_net, DOUTB1 => QBX_TEMPR12_9_net,
|
| 2150 |
|
|
DOUTB0 => QBX_TEMPR12_8_net);
|
| 2151 |
|
|
NAND2_ENABLE_ADDRA_10_inst : NAND2
|
| 2152 |
|
|
port map(A => AND2A_2_Y, B => AND2A_3_Y, Y =>
|
| 2153 |
|
|
ENABLE_ADDRA_10_net);
|
| 2154 |
|
|
NAND2_ENABLE_ADDRA_11_inst : NAND2
|
| 2155 |
|
|
port map(A => AND2_2_Y, B => AND2A_3_Y, Y =>
|
| 2156 |
|
|
ENABLE_ADDRA_11_net);
|
| 2157 |
|
|
MX2_126 : MX2
|
| 2158 |
|
|
port map(A => MX2_92_Y, B => MX2_209_Y, S =>
|
| 2159 |
|
|
ADDRA_FF2_2_net, Y => MX2_126_Y);
|
| 2160 |
|
|
dual_port_memory_R10C0 : RAM4K9
|
| 2161 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2162 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2163 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2164 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2165 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2166 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2167 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2168 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2169 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2170 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2171 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2172 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 2173 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 2174 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2175 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2176 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 2177 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2178 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2179 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2180 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_10_net,
|
| 2181 |
|
|
BLKB => BLKB_EN_10_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2182 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2183 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2184 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR10_3_net, DOUTA2 =>
|
| 2185 |
|
|
QAX_TEMPR10_2_net, DOUTA1 => QAX_TEMPR10_1_net, DOUTA0 =>
|
| 2186 |
|
|
QAX_TEMPR10_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2187 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2188 |
|
|
DOUTB3 => QBX_TEMPR10_3_net, DOUTB2 => QBX_TEMPR10_2_net,
|
| 2189 |
|
|
DOUTB1 => QBX_TEMPR10_1_net, DOUTB0 => QBX_TEMPR10_0_net);
|
| 2190 |
|
|
ORA_GATE_13_inst : OR2
|
| 2191 |
|
|
port map(A => ENABLE_ADDRA_13_net, B => WEAP, Y =>
|
| 2192 |
|
|
BLKA_EN_13_net);
|
| 2193 |
|
|
MX2_125 : MX2
|
| 2194 |
|
|
port map(A => QAX_TEMPR0_14_net, B => QAX_TEMPR1_14_net,
|
| 2195 |
|
|
S => BUFF_15_Y, Y => MX2_125_Y);
|
| 2196 |
|
|
MX2_397 : MX2
|
| 2197 |
|
|
port map(A => MX2_155_Y, B => MX2_310_Y, S => BUFF_17_Y,
|
| 2198 |
|
|
Y => MX2_397_Y);
|
| 2199 |
|
|
dual_port_memory_R11C3 : RAM4K9
|
| 2200 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2201 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2202 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2203 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2204 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2205 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2206 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2207 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2208 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2209 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2210 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2211 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 2212 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 2213 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2214 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2215 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 2216 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2217 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2218 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2219 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_11_net,
|
| 2220 |
|
|
BLKB => BLKB_EN_11_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2221 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2222 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2223 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR11_15_net, DOUTA2 =>
|
| 2224 |
|
|
QAX_TEMPR11_14_net, DOUTA1 => QAX_TEMPR11_13_net,
|
| 2225 |
|
|
DOUTA0 => QAX_TEMPR11_12_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 2226 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2227 |
|
|
DOUTB3 => QBX_TEMPR11_15_net, DOUTB2 =>
|
| 2228 |
|
|
QBX_TEMPR11_14_net, DOUTB1 => QBX_TEMPR11_13_net,
|
| 2229 |
|
|
DOUTB0 => QBX_TEMPR11_12_net);
|
| 2230 |
|
|
MX2_73 : MX2
|
| 2231 |
|
|
port map(A => QAX_TEMPR12_3_net, B => QAX_TEMPR13_3_net,
|
| 2232 |
|
|
S => BUFF_0_Y, Y => MX2_73_Y);
|
| 2233 |
|
|
NAND2_ENABLE_ADDRA_5_inst : NAND2
|
| 2234 |
|
|
port map(A => AND2A_4_Y, B => AND2A_5_Y, Y =>
|
| 2235 |
|
|
ENABLE_ADDRA_5_net);
|
| 2236 |
|
|
MX2_293 : MX2
|
| 2237 |
|
|
port map(A => QBX_TEMPR8_6_net, B => QBX_TEMPR9_6_net, S =>
|
| 2238 |
|
|
BUFF_6_Y, Y => MX2_293_Y);
|
| 2239 |
|
|
MX2_242 : MX2
|
| 2240 |
|
|
port map(A => QBX_TEMPR0_14_net, B => QBX_TEMPR1_14_net,
|
| 2241 |
|
|
S => BUFF_2_Y, Y => MX2_242_Y);
|
| 2242 |
|
|
MX2_200 : MX2
|
| 2243 |
|
|
port map(A => MX2_157_Y, B => QBX_TEMPR14_3_net, S =>
|
| 2244 |
|
|
BUFF_7_Y, Y => MX2_200_Y);
|
| 2245 |
|
|
MX2_44 : MX2
|
| 2246 |
|
|
port map(A => MX2_136_Y, B => MX2_153_Y, S =>
|
| 2247 |
|
|
ADDRA_FF2_2_net, Y => MX2_44_Y);
|
| 2248 |
|
|
MX2_320 : MX2
|
| 2249 |
|
|
port map(A => MX2_158_Y, B => QAX_TEMPR14_10_net, S =>
|
| 2250 |
|
|
BUFF_32_Y, Y => MX2_320_Y);
|
| 2251 |
|
|
BUFF_34 : BUFF
|
| 2252 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_34_Y);
|
| 2253 |
|
|
MX2_DOUTA_9_inst : MX2
|
| 2254 |
|
|
port map(A => MX2_150_Y, B => MX2_409_Y, S =>
|
| 2255 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(9));
|
| 2256 |
|
|
MX2_DOUTB_2_inst : MX2
|
| 2257 |
|
|
port map(A => MX2_141_Y, B => MX2_104_Y, S =>
|
| 2258 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(2));
|
| 2259 |
|
|
MX2_63 : MX2
|
| 2260 |
|
|
port map(A => QBX_TEMPR6_14_net, B => QBX_TEMPR7_14_net,
|
| 2261 |
|
|
S => BUFF_2_Y, Y => MX2_63_Y);
|
| 2262 |
|
|
MX2_39 : MX2
|
| 2263 |
|
|
port map(A => MX2_240_Y, B => MX2_251_Y, S => BUFF_38_Y,
|
| 2264 |
|
|
Y => MX2_39_Y);
|
| 2265 |
|
|
MX2_148 : MX2
|
| 2266 |
|
|
port map(A => QAX_TEMPR4_8_net, B => QAX_TEMPR5_8_net, S =>
|
| 2267 |
|
|
BUFF_11_Y, Y => MX2_148_Y);
|
| 2268 |
|
|
MX2_101 : MX2
|
| 2269 |
|
|
port map(A => QAX_TEMPR4_6_net, B => QAX_TEMPR5_6_net, S =>
|
| 2270 |
|
|
BUFF_26_Y, Y => MX2_101_Y);
|
| 2271 |
|
|
NAND2_ENABLE_ADDRA_12_inst : NAND2
|
| 2272 |
|
|
port map(A => NOR2_2_Y, B => AND2_3_Y, Y =>
|
| 2273 |
|
|
ENABLE_ADDRA_12_net);
|
| 2274 |
|
|
AND2_3 : AND2
|
| 2275 |
|
|
port map(A => ADDRA(13), B => ADDRA(12), Y => AND2_3_Y);
|
| 2276 |
|
|
MX2_231 : MX2
|
| 2277 |
|
|
port map(A => QAX_TEMPR6_4_net, B => QAX_TEMPR7_4_net, S =>
|
| 2278 |
|
|
BUFF_22_Y, Y => MX2_231_Y);
|
| 2279 |
|
|
MX2_164 : MX2
|
| 2280 |
|
|
port map(A => QBX_TEMPR12_9_net, B => QBX_TEMPR13_9_net,
|
| 2281 |
|
|
S => BUFF_28_Y, Y => MX2_164_Y);
|
| 2282 |
|
|
MX2_237 : MX2
|
| 2283 |
|
|
port map(A => MX2_28_Y, B => MX2_268_Y, S =>
|
| 2284 |
|
|
ADDRA_FF2_2_net, Y => MX2_237_Y);
|
| 2285 |
|
|
MX2_152 : MX2
|
| 2286 |
|
|
port map(A => QBX_TEMPR2_13_net, B => QBX_TEMPR3_13_net,
|
| 2287 |
|
|
S => BUFF_24_Y, Y => MX2_152_Y);
|
| 2288 |
|
|
MX2_368 : MX2
|
| 2289 |
|
|
port map(A => MX2_64_Y, B => MX2_65_Y, S => ADDRB_FF2_2_net,
|
| 2290 |
|
|
Y => MX2_368_Y);
|
| 2291 |
|
|
MX2_205 : MX2
|
| 2292 |
|
|
port map(A => MX2_273_Y, B => MX2_298_Y, S =>
|
| 2293 |
|
|
ADDRB_FF2_2_net, Y => MX2_205_Y);
|
| 2294 |
|
|
dual_port_memory_R1C2 : RAM4K9
|
| 2295 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2296 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2297 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2298 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2299 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2300 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2301 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2302 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2303 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2304 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2305 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2306 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 2307 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 2308 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2309 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2310 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 2311 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2312 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2313 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2314 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_1_net,
|
| 2315 |
|
|
BLKB => BLKB_EN_1_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2316 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2317 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2318 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR1_11_net, DOUTA2 =>
|
| 2319 |
|
|
QAX_TEMPR1_10_net, DOUTA1 => QAX_TEMPR1_9_net, DOUTA0 =>
|
| 2320 |
|
|
QAX_TEMPR1_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2321 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2322 |
|
|
DOUTB3 => QBX_TEMPR1_11_net, DOUTB2 => QBX_TEMPR1_10_net,
|
| 2323 |
|
|
DOUTB1 => QBX_TEMPR1_9_net, DOUTB0 => QBX_TEMPR1_8_net);
|
| 2324 |
|
|
MX2_301 : MX2
|
| 2325 |
|
|
port map(A => QAX_TEMPR2_6_net, B => QAX_TEMPR3_6_net, S =>
|
| 2326 |
|
|
BUFF_26_Y, Y => MX2_301_Y);
|
| 2327 |
|
|
MX2_363 : MX2
|
| 2328 |
|
|
port map(A => MX2_22_Y, B => QAX_TEMPR14_7_net, S =>
|
| 2329 |
|
|
BUFF_27_Y, Y => MX2_363_Y);
|
| 2330 |
|
|
NAND2_ENABLE_ADDRB_5_inst : NAND2
|
| 2331 |
|
|
port map(A => AND2A_1_Y, B => AND2A_0_Y, Y =>
|
| 2332 |
|
|
ENABLE_ADDRB_5_net);
|
| 2333 |
|
|
MX2_298 : MX2
|
| 2334 |
|
|
port map(A => MX2_366_Y, B => MX2_277_Y, S => BUFF_29_Y,
|
| 2335 |
|
|
Y => MX2_298_Y);
|
| 2336 |
|
|
NAND2_ENABLE_ADDRA_6_inst : NAND2
|
| 2337 |
|
|
port map(A => AND2A_2_Y, B => AND2A_5_Y, Y =>
|
| 2338 |
|
|
ENABLE_ADDRA_6_net);
|
| 2339 |
|
|
NAND2_ENABLE_ADDRB_13_inst : NAND2
|
| 2340 |
|
|
port map(A => AND2A_1_Y, B => AND2_0_Y, Y =>
|
| 2341 |
|
|
ENABLE_ADDRB_13_net);
|
| 2342 |
|
|
MX2_196 : MX2
|
| 2343 |
|
|
port map(A => QBX_TEMPR10_4_net, B => QBX_TEMPR11_4_net,
|
| 2344 |
|
|
S => BUFF_12_Y, Y => MX2_196_Y);
|
| 2345 |
|
|
AND2A_0 : AND2A
|
| 2346 |
|
|
port map(A => ADDRB(13), B => ADDRB(12), Y => AND2A_0_Y);
|
| 2347 |
|
|
MX2_195 : MX2
|
| 2348 |
|
|
port map(A => MX2_139_Y, B => MX2_244_Y, S => BUFF_38_Y,
|
| 2349 |
|
|
Y => MX2_195_Y);
|
| 2350 |
|
|
ORB_GATE_10_inst : OR2
|
| 2351 |
|
|
port map(A => ENABLE_ADDRB_10_net, B => WEBP, Y =>
|
| 2352 |
|
|
BLKB_EN_10_net);
|
| 2353 |
|
|
MX2_244 : MX2
|
| 2354 |
|
|
port map(A => QAX_TEMPR6_0_net, B => QAX_TEMPR7_0_net, S =>
|
| 2355 |
|
|
BUFF_18_Y, Y => MX2_244_Y);
|
| 2356 |
|
|
MX2_390 : MX2
|
| 2357 |
|
|
port map(A => MX2_381_Y, B => MX2_62_Y, S =>
|
| 2358 |
|
|
ADDRB_FF2_2_net, Y => MX2_390_Y);
|
| 2359 |
|
|
MX2_260 : MX2
|
| 2360 |
|
|
port map(A => MX2_88_Y, B => MX2_167_Y, S =>
|
| 2361 |
|
|
ADDRA_FF2_2_net, Y => MX2_260_Y);
|
| 2362 |
|
|
MX2_109 : MX2
|
| 2363 |
|
|
port map(A => QBX_TEMPR6_5_net, B => QBX_TEMPR7_5_net, S =>
|
| 2364 |
|
|
BUFF_6_Y, Y => MX2_109_Y);
|
| 2365 |
|
|
MX2_DOUTA_4_inst : MX2
|
| 2366 |
|
|
port map(A => MX2_271_Y, B => MX2_346_Y, S =>
|
| 2367 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(4));
|
| 2368 |
|
|
MX2_161 : MX2
|
| 2369 |
|
|
port map(A => MX2_391_Y, B => MX2_63_Y, S => BUFF_13_Y,
|
| 2370 |
|
|
Y => MX2_161_Y);
|
| 2371 |
|
|
MX2_87 : MX2
|
| 2372 |
|
|
port map(A => QBX_TEMPR6_2_net, B => QBX_TEMPR7_2_net, S =>
|
| 2373 |
|
|
BUFF_33_Y, Y => MX2_87_Y);
|
| 2374 |
|
|
MX2_71 : MX2
|
| 2375 |
|
|
port map(A => MX2_189_Y, B => QAX_TEMPR14_14_net, S =>
|
| 2376 |
|
|
BUFF_30_Y, Y => MX2_71_Y);
|
| 2377 |
|
|
ORA_GATE_5_inst : OR2
|
| 2378 |
|
|
port map(A => ENABLE_ADDRA_5_net, B => WEAP, Y =>
|
| 2379 |
|
|
BLKA_EN_5_net);
|
| 2380 |
|
|
WEBUBBLEB : INV
|
| 2381 |
|
|
port map(A => BLKB, Y => WEBP);
|
| 2382 |
|
|
MX2_305 : MX2
|
| 2383 |
|
|
port map(A => QAX_TEMPR2_5_net, B => QAX_TEMPR3_5_net, S =>
|
| 2384 |
|
|
BUFF_22_Y, Y => MX2_305_Y);
|
| 2385 |
|
|
dual_port_memory_R6C0 : RAM4K9
|
| 2386 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2387 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2388 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2389 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2390 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2391 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2392 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2393 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2394 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2395 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2396 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2397 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 2398 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 2399 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2400 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2401 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 2402 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2403 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2404 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2405 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_6_net,
|
| 2406 |
|
|
BLKB => BLKB_EN_6_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2407 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2408 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2409 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR6_3_net, DOUTA2 =>
|
| 2410 |
|
|
QAX_TEMPR6_2_net, DOUTA1 => QAX_TEMPR6_1_net, DOUTA0 =>
|
| 2411 |
|
|
QAX_TEMPR6_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2412 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2413 |
|
|
DOUTB3 => QBX_TEMPR6_3_net, DOUTB2 => QBX_TEMPR6_2_net,
|
| 2414 |
|
|
DOUTB1 => QBX_TEMPR6_1_net, DOUTB0 => QBX_TEMPR6_0_net);
|
| 2415 |
|
|
MX2_324 : MX2
|
| 2416 |
|
|
port map(A => MX2_404_Y, B => MX2_13_Y, S =>
|
| 2417 |
|
|
ADDRB_FF2_2_net, Y => MX2_324_Y);
|
| 2418 |
|
|
MX2_61 : MX2
|
| 2419 |
|
|
port map(A => QBX_TEMPR4_1_net, B => QBX_TEMPR5_1_net, S =>
|
| 2420 |
|
|
BUFF_23_Y, Y => MX2_61_Y);
|
| 2421 |
|
|
MX2_276 : MX2
|
| 2422 |
|
|
port map(A => QAX_TEMPR4_7_net, B => QAX_TEMPR5_7_net, S =>
|
| 2423 |
|
|
BUFF_10_Y, Y => MX2_276_Y);
|
| 2424 |
|
|
MX2_78 : MX2
|
| 2425 |
|
|
port map(A => MX2_142_Y, B => MX2_35_Y, S =>
|
| 2426 |
|
|
ADDRA_FF2_2_net, Y => MX2_78_Y);
|
| 2427 |
|
|
MX2_265 : MX2
|
| 2428 |
|
|
port map(A => QBX_TEMPR6_1_net, B => QBX_TEMPR7_1_net, S =>
|
| 2429 |
|
|
BUFF_33_Y, Y => MX2_265_Y);
|
| 2430 |
|
|
MX2_361 : MX2
|
| 2431 |
|
|
port map(A => QAX_TEMPR10_0_net, B => QAX_TEMPR11_0_net,
|
| 2432 |
|
|
S => BUFF_18_Y, Y => MX2_361_Y);
|
| 2433 |
|
|
BUFF_9 : BUFF
|
| 2434 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_9_Y);
|
| 2435 |
|
|
MX2_211 : MX2
|
| 2436 |
|
|
port map(A => QBX_TEMPR12_6_net, B => QBX_TEMPR13_6_net,
|
| 2437 |
|
|
S => BUFF_3_Y, Y => MX2_211_Y);
|
| 2438 |
|
|
BUFF_35 : BUFF
|
| 2439 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_35_Y);
|
| 2440 |
|
|
MX2_217 : MX2
|
| 2441 |
|
|
port map(A => QAX_TEMPR8_13_net, B => QAX_TEMPR9_13_net,
|
| 2442 |
|
|
S => BUFF_15_Y, Y => MX2_217_Y);
|
| 2443 |
|
|
BUFF_30 : BUFF
|
| 2444 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_30_Y);
|
| 2445 |
|
|
ORB_GATE_3_inst : OR2
|
| 2446 |
|
|
port map(A => ENABLE_ADDRB_3_net, B => WEBP, Y =>
|
| 2447 |
|
|
BLKB_EN_3_net);
|
| 2448 |
|
|
MX2_68 : MX2
|
| 2449 |
|
|
port map(A => QBX_TEMPR8_15_net, B => QBX_TEMPR9_15_net,
|
| 2450 |
|
|
S => BUFF_16_Y, Y => MX2_68_Y);
|
| 2451 |
|
|
MX2_25 : MX2
|
| 2452 |
|
|
port map(A => QAX_TEMPR8_14_net, B => QAX_TEMPR9_14_net,
|
| 2453 |
|
|
S => BUFF_15_Y, Y => MX2_25_Y);
|
| 2454 |
|
|
MX2_DOUTB_8_inst : MX2
|
| 2455 |
|
|
port map(A => MX2_194_Y, B => MX2_225_Y, S =>
|
| 2456 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(8));
|
| 2457 |
|
|
MX2_281 : MX2
|
| 2458 |
|
|
port map(A => MX2_270_Y, B => MX2_414_Y, S => BUFF_7_Y,
|
| 2459 |
|
|
Y => MX2_281_Y);
|
| 2460 |
|
|
MX2_287 : MX2
|
| 2461 |
|
|
port map(A => QAX_TEMPR2_14_net, B => QAX_TEMPR3_14_net,
|
| 2462 |
|
|
S => BUFF_15_Y, Y => MX2_287_Y);
|
| 2463 |
|
|
NAND2_ENABLE_ADDRA_13_inst : NAND2
|
| 2464 |
|
|
port map(A => AND2A_4_Y, B => AND2_3_Y, Y =>
|
| 2465 |
|
|
ENABLE_ADDRA_13_net);
|
| 2466 |
|
|
ORA_GATE_2_inst : OR2
|
| 2467 |
|
|
port map(A => ENABLE_ADDRA_2_net, B => WEAP, Y =>
|
| 2468 |
|
|
BLKA_EN_2_net);
|
| 2469 |
|
|
BUFF_1 : BUFF
|
| 2470 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_1_Y);
|
| 2471 |
|
|
MX2_169 : MX2
|
| 2472 |
|
|
port map(A => MX2_96_Y, B => QAX_TEMPR14_0_net, S =>
|
| 2473 |
|
|
BUFF_38_Y, Y => MX2_169_Y);
|
| 2474 |
|
|
BUFF_18 : BUFF
|
| 2475 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_18_Y);
|
| 2476 |
|
|
MX2_202 : MX2
|
| 2477 |
|
|
port map(A => QBX_TEMPR0_1_net, B => QBX_TEMPR1_1_net, S =>
|
| 2478 |
|
|
BUFF_23_Y, Y => MX2_202_Y);
|
| 2479 |
|
|
MX2_346 : MX2
|
| 2480 |
|
|
port map(A => MX2_98_Y, B => MX2_383_Y, S =>
|
| 2481 |
|
|
ADDRA_FF2_2_net, Y => MX2_346_Y);
|
| 2482 |
|
|
MX2_40 : MX2
|
| 2483 |
|
|
port map(A => QAX_TEMPR12_4_net, B => QAX_TEMPR13_4_net,
|
| 2484 |
|
|
S => BUFF_22_Y, Y => MX2_40_Y);
|
| 2485 |
|
|
MX2_174 : MX2
|
| 2486 |
|
|
port map(A => MX2_51_Y, B => MX2_223_Y, S => BUFF_17_Y,
|
| 2487 |
|
|
Y => MX2_174_Y);
|
| 2488 |
|
|
MX2_108 : MX2
|
| 2489 |
|
|
port map(A => MX2_207_Y, B => QAX_TEMPR14_13_net, S =>
|
| 2490 |
|
|
BUFF_8_Y, Y => MX2_108_Y);
|
| 2491 |
|
|
MX2_378 : MX2
|
| 2492 |
|
|
port map(A => QAX_TEMPR10_12_net, B => QAX_TEMPR11_12_net,
|
| 2493 |
|
|
S => BUFF_37_Y, Y => MX2_378_Y);
|
| 2494 |
|
|
MX2_394 : MX2
|
| 2495 |
|
|
port map(A => QAX_TEMPR10_11_net, B => QAX_TEMPR11_11_net,
|
| 2496 |
|
|
S => BUFF_14_Y, Y => MX2_394_Y);
|
| 2497 |
|
|
MX2_373 : MX2
|
| 2498 |
|
|
port map(A => MX2_219_Y, B => MX2_415_Y, S =>
|
| 2499 |
|
|
ADDRB_FF2_2_net, Y => MX2_373_Y);
|
| 2500 |
|
|
MX2_365 : MX2
|
| 2501 |
|
|
port map(A => MX2_17_Y, B => MX2_31_Y, S => BUFF_35_Y, Y =>
|
| 2502 |
|
|
MX2_365_Y);
|
| 2503 |
|
|
ORB_GATE_13_inst : OR2
|
| 2504 |
|
|
port map(A => ENABLE_ADDRB_13_net, B => WEBP, Y =>
|
| 2505 |
|
|
BLKB_EN_13_net);
|
| 2506 |
|
|
MX2_259 : MX2
|
| 2507 |
|
|
port map(A => MX2_261_Y, B => MX2_30_Y, S =>
|
| 2508 |
|
|
ADDRB_FF2_2_net, Y => MX2_259_Y);
|
| 2509 |
|
|
BUFF_2 : BUFF
|
| 2510 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_2_Y);
|
| 2511 |
|
|
BUFF_28 : BUFF
|
| 2512 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_28_Y);
|
| 2513 |
|
|
BUFF_0 : BUFF
|
| 2514 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_0_Y);
|
| 2515 |
|
|
MX2_DOUTB_11_inst : MX2
|
| 2516 |
|
|
port map(A => MX2_233_Y, B => MX2_210_Y, S =>
|
| 2517 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(11));
|
| 2518 |
|
|
MX2_342 : MX2
|
| 2519 |
|
|
port map(A => MX2_10_Y, B => MX2_66_Y, S => BUFF_25_Y, Y =>
|
| 2520 |
|
|
MX2_342_Y);
|
| 2521 |
|
|
dual_port_memory_R1C1 : RAM4K9
|
| 2522 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2523 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2524 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2525 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2526 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2527 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2528 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2529 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2530 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2531 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2532 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2533 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 2534 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 2535 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2536 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2537 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 2538 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2539 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2540 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2541 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_1_net,
|
| 2542 |
|
|
BLKB => BLKB_EN_1_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2543 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2544 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2545 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR1_7_net, DOUTA2 =>
|
| 2546 |
|
|
QAX_TEMPR1_6_net, DOUTA1 => QAX_TEMPR1_5_net, DOUTA0 =>
|
| 2547 |
|
|
QAX_TEMPR1_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2548 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2549 |
|
|
DOUTB3 => QBX_TEMPR1_7_net, DOUTB2 => QBX_TEMPR1_6_net,
|
| 2550 |
|
|
DOUTB1 => QBX_TEMPR1_5_net, DOUTB0 => QBX_TEMPR1_4_net);
|
| 2551 |
|
|
MX2_143 : MX2
|
| 2552 |
|
|
port map(A => MX2_38_Y, B => MX2_238_Y, S => BUFF_4_Y, Y =>
|
| 2553 |
|
|
MX2_143_Y);
|
| 2554 |
|
|
MX2_349 : MX2
|
| 2555 |
|
|
port map(A => QBX_TEMPR12_4_net, B => QBX_TEMPR13_4_net,
|
| 2556 |
|
|
S => BUFF_12_Y, Y => MX2_349_Y);
|
| 2557 |
|
|
MX2_83 : MX2
|
| 2558 |
|
|
port map(A => MX2_343_Y, B => MX2_143_Y, S =>
|
| 2559 |
|
|
ADDRB_FF2_2_net, Y => MX2_83_Y);
|
| 2560 |
|
|
MX2_270 : MX2
|
| 2561 |
|
|
port map(A => QBX_TEMPR0_2_net, B => QBX_TEMPR1_2_net, S =>
|
| 2562 |
|
|
BUFF_33_Y, Y => MX2_270_Y);
|
| 2563 |
|
|
dual_port_memory_R13C1 : RAM4K9
|
| 2564 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2565 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2566 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2567 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2568 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2569 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2570 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2571 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2572 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2573 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2574 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2575 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 2576 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 2577 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2578 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2579 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 2580 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2581 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2582 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2583 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_13_net,
|
| 2584 |
|
|
BLKB => BLKB_EN_13_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2585 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2586 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2587 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR13_7_net, DOUTA2 =>
|
| 2588 |
|
|
QAX_TEMPR13_6_net, DOUTA1 => QAX_TEMPR13_5_net, DOUTA0 =>
|
| 2589 |
|
|
QAX_TEMPR13_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2590 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2591 |
|
|
DOUTB3 => QBX_TEMPR13_7_net, DOUTB2 => QBX_TEMPR13_6_net,
|
| 2592 |
|
|
DOUTB1 => QBX_TEMPR13_5_net, DOUTB0 => QBX_TEMPR13_4_net);
|
| 2593 |
|
|
MX2_120 : MX2
|
| 2594 |
|
|
port map(A => MX2_193_Y, B => MX2_361_Y, S => BUFF_38_Y,
|
| 2595 |
|
|
Y => MX2_120_Y);
|
| 2596 |
|
|
MX2_357 : MX2
|
| 2597 |
|
|
port map(A => MX2_95_Y, B => MX2_407_Y, S =>
|
| 2598 |
|
|
ADDRB_FF2_2_net, Y => MX2_357_Y);
|
| 2599 |
|
|
MX2_DOUTA_0_inst : MX2
|
| 2600 |
|
|
port map(A => MX2_284_Y, B => MX2_59_Y, S =>
|
| 2601 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(0));
|
| 2602 |
|
|
dual_port_memory_R4C0 : RAM4K9
|
| 2603 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2604 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2605 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2606 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2607 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2608 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2609 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2610 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2611 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2612 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2613 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2614 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 2615 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 2616 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2617 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2618 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 2619 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2620 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2621 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2622 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_4_net,
|
| 2623 |
|
|
BLKB => BLKB_EN_4_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2624 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2625 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2626 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR4_3_net, DOUTA2 =>
|
| 2627 |
|
|
QAX_TEMPR4_2_net, DOUTA1 => QAX_TEMPR4_1_net, DOUTA0 =>
|
| 2628 |
|
|
QAX_TEMPR4_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2629 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2630 |
|
|
DOUTB3 => QBX_TEMPR4_3_net, DOUTB2 => QBX_TEMPR4_2_net,
|
| 2631 |
|
|
DOUTB1 => QBX_TEMPR4_1_net, DOUTB0 => QBX_TEMPR4_0_net);
|
| 2632 |
|
|
MX2_171 : MX2
|
| 2633 |
|
|
port map(A => QBX_TEMPR10_7_net, B => QBX_TEMPR11_7_net,
|
| 2634 |
|
|
S => BUFF_3_Y, Y => MX2_171_Y);
|
| 2635 |
|
|
MX2_253 : MX2
|
| 2636 |
|
|
port map(A => MX2_242_Y, B => MX2_382_Y, S => BUFF_13_Y,
|
| 2637 |
|
|
Y => MX2_253_Y);
|
| 2638 |
|
|
MX2_204 : MX2
|
| 2639 |
|
|
port map(A => MX2_3_Y, B => MX2_401_Y, S => BUFF_1_Y, Y =>
|
| 2640 |
|
|
MX2_204_Y);
|
| 2641 |
|
|
ORA_GATE_7_inst : OR2
|
| 2642 |
|
|
port map(A => ENABLE_ADDRA_7_net, B => WEAP, Y =>
|
| 2643 |
|
|
BLKA_EN_7_net);
|
| 2644 |
|
|
AFF1_3_inst : DFN1
|
| 2645 |
|
|
port map(D => ADDRA(13), CLK => CLKA, Q => ADDRA_FF2_3_net);
|
| 2646 |
|
|
MX2_236 : MX2
|
| 2647 |
|
|
port map(A => QBX_TEMPR6_3_net, B => QBX_TEMPR7_3_net, S =>
|
| 2648 |
|
|
BUFF_5_Y, Y => MX2_236_Y);
|
| 2649 |
|
|
MX2_262 : MX2
|
| 2650 |
|
|
port map(A => QAX_TEMPR4_15_net, B => QAX_TEMPR5_15_net,
|
| 2651 |
|
|
S => BUFF_9_Y, Y => MX2_262_Y);
|
| 2652 |
|
|
MX2_46 : MX2
|
| 2653 |
|
|
port map(A => MX2_246_Y, B => MX2_295_Y, S => BUFF_31_Y,
|
| 2654 |
|
|
Y => MX2_46_Y);
|
| 2655 |
|
|
dual_port_memory_R4C1 : RAM4K9
|
| 2656 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2657 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2658 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2659 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2660 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2661 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2662 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2663 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2664 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2665 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2666 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2667 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 2668 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 2669 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2670 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2671 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 2672 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2673 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2674 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2675 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_4_net,
|
| 2676 |
|
|
BLKB => BLKB_EN_4_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2677 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2678 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2679 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR4_7_net, DOUTA2 =>
|
| 2680 |
|
|
QAX_TEMPR4_6_net, DOUTA1 => QAX_TEMPR4_5_net, DOUTA0 =>
|
| 2681 |
|
|
QAX_TEMPR4_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2682 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2683 |
|
|
DOUTB3 => QBX_TEMPR4_7_net, DOUTB2 => QBX_TEMPR4_6_net,
|
| 2684 |
|
|
DOUTB1 => QBX_TEMPR4_5_net, DOUTB0 => QBX_TEMPR4_4_net);
|
| 2685 |
|
|
MX2_35 : MX2
|
| 2686 |
|
|
port map(A => MX2_263_Y, B => QAX_TEMPR14_11_net, S =>
|
| 2687 |
|
|
BUFF_32_Y, Y => MX2_35_Y);
|
| 2688 |
|
|
MX2_168 : MX2
|
| 2689 |
|
|
port map(A => QAX_TEMPR6_6_net, B => QAX_TEMPR7_6_net, S =>
|
| 2690 |
|
|
BUFF_26_Y, Y => MX2_168_Y);
|
| 2691 |
|
|
MX2_275 : MX2
|
| 2692 |
|
|
port map(A => QBX_TEMPR8_10_net, B => QBX_TEMPR9_10_net,
|
| 2693 |
|
|
S => BUFF_28_Y, Y => MX2_275_Y);
|
| 2694 |
|
|
MX2_DOUTB_12_inst : MX2
|
| 2695 |
|
|
port map(A => MX2_324_Y, B => MX2_307_Y, S =>
|
| 2696 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(12));
|
| 2697 |
|
|
MX2_371 : MX2
|
| 2698 |
|
|
port map(A => MX2_101_Y, B => MX2_168_Y, S => BUFF_27_Y,
|
| 2699 |
|
|
Y => MX2_371_Y);
|
| 2700 |
|
|
MX2_410 : MX2
|
| 2701 |
|
|
port map(A => QAX_TEMPR10_8_net, B => QAX_TEMPR11_8_net,
|
| 2702 |
|
|
S => BUFF_11_Y, Y => MX2_410_Y);
|
| 2703 |
|
|
NAND2_ENABLE_ADDRA_0_inst : NAND2
|
| 2704 |
|
|
port map(A => NOR2_2_Y, B => NOR2_3_Y, Y =>
|
| 2705 |
|
|
ENABLE_ADDRA_0_net);
|
| 2706 |
|
|
MX2_258 : MX2
|
| 2707 |
|
|
port map(A => MX2_226_Y, B => MX2_213_Y, S =>
|
| 2708 |
|
|
ADDRB_FF2_2_net, Y => MX2_258_Y);
|
| 2709 |
|
|
dual_port_memory_R7C1 : RAM4K9
|
| 2710 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2711 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2712 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2713 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2714 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2715 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2716 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2717 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2718 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2719 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2720 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2721 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 2722 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 2723 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2724 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2725 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 2726 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2727 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2728 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2729 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_7_net,
|
| 2730 |
|
|
BLKB => BLKB_EN_7_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2731 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2732 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2733 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR7_7_net, DOUTA2 =>
|
| 2734 |
|
|
QAX_TEMPR7_6_net, DOUTA1 => QAX_TEMPR7_5_net, DOUTA0 =>
|
| 2735 |
|
|
QAX_TEMPR7_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2736 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2737 |
|
|
DOUTB3 => QBX_TEMPR7_7_net, DOUTB2 => QBX_TEMPR7_6_net,
|
| 2738 |
|
|
DOUTB1 => QBX_TEMPR7_5_net, DOUTB0 => QBX_TEMPR7_4_net);
|
| 2739 |
|
|
MX2_142 : MX2
|
| 2740 |
|
|
port map(A => MX2_53_Y, B => MX2_394_Y, S => BUFF_32_Y,
|
| 2741 |
|
|
Y => MX2_142_Y);
|
| 2742 |
|
|
MX2_134 : MX2
|
| 2743 |
|
|
port map(A => QBX_TEMPR0_7_net, B => QBX_TEMPR1_7_net, S =>
|
| 2744 |
|
|
BUFF_3_Y, Y => MX2_134_Y);
|
| 2745 |
|
|
MX2_2 : MX2
|
| 2746 |
|
|
port map(A => QAX_TEMPR4_13_net, B => QAX_TEMPR5_13_net,
|
| 2747 |
|
|
S => BUFF_37_Y, Y => MX2_2_Y);
|
| 2748 |
|
|
MX2_156 : MX2
|
| 2749 |
|
|
port map(A => MX2_367_Y, B => MX2_356_Y, S =>
|
| 2750 |
|
|
ADDRA_FF2_2_net, Y => MX2_156_Y);
|
| 2751 |
|
|
dual_port_memory_R10C1 : RAM4K9
|
| 2752 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2753 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2754 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2755 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2756 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2757 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2758 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2759 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2760 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2761 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2762 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2763 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 2764 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 2765 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2766 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2767 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 2768 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2769 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2770 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2771 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_10_net,
|
| 2772 |
|
|
BLKB => BLKB_EN_10_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2773 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2774 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2775 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR10_7_net, DOUTA2 =>
|
| 2776 |
|
|
QAX_TEMPR10_6_net, DOUTA1 => QAX_TEMPR10_5_net, DOUTA0 =>
|
| 2777 |
|
|
QAX_TEMPR10_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2778 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2779 |
|
|
DOUTB3 => QBX_TEMPR10_7_net, DOUTB2 => QBX_TEMPR10_6_net,
|
| 2780 |
|
|
DOUTB1 => QBX_TEMPR10_5_net, DOUTB0 => QBX_TEMPR10_4_net);
|
| 2781 |
|
|
MX2_DOUTB_1_inst : MX2
|
| 2782 |
|
|
port map(A => MX2_131_Y, B => MX2_208_Y, S =>
|
| 2783 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(1));
|
| 2784 |
|
|
MX2_190 : MX2
|
| 2785 |
|
|
port map(A => QBX_TEMPR4_3_net, B => QBX_TEMPR5_3_net, S =>
|
| 2786 |
|
|
BUFF_5_Y, Y => MX2_190_Y);
|
| 2787 |
|
|
MX2_155 : MX2
|
| 2788 |
|
|
port map(A => QAX_TEMPR0_2_net, B => QAX_TEMPR1_2_net, S =>
|
| 2789 |
|
|
BUFF_21_Y, Y => MX2_155_Y);
|
| 2790 |
|
|
MX2_179 : MX2
|
| 2791 |
|
|
port map(A => QAX_TEMPR6_2_net, B => QAX_TEMPR7_2_net, S =>
|
| 2792 |
|
|
BUFF_21_Y, Y => MX2_179_Y);
|
| 2793 |
|
|
MX2_338 : MX2
|
| 2794 |
|
|
port map(A => QAX_TEMPR10_3_net, B => QAX_TEMPR11_3_net,
|
| 2795 |
|
|
S => BUFF_0_Y, Y => MX2_338_Y);
|
| 2796 |
|
|
dual_port_memory_R10C2 : RAM4K9
|
| 2797 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2798 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2799 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2800 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2801 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2802 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2803 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2804 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2805 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2806 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2807 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2808 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 2809 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 2810 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2811 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2812 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 2813 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2814 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2815 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2816 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_10_net,
|
| 2817 |
|
|
BLKB => BLKB_EN_10_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2818 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2819 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2820 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR10_11_net, DOUTA2 =>
|
| 2821 |
|
|
QAX_TEMPR10_10_net, DOUTA1 => QAX_TEMPR10_9_net,
|
| 2822 |
|
|
DOUTA0 => QAX_TEMPR10_8_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 2823 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2824 |
|
|
DOUTB3 => QBX_TEMPR10_11_net, DOUTB2 =>
|
| 2825 |
|
|
QBX_TEMPR10_10_net, DOUTB1 => QBX_TEMPR10_9_net,
|
| 2826 |
|
|
DOUTB0 => QBX_TEMPR10_8_net);
|
| 2827 |
|
|
MX2_333 : MX2
|
| 2828 |
|
|
port map(A => QAX_TEMPR0_8_net, B => QAX_TEMPR1_8_net, S =>
|
| 2829 |
|
|
BUFF_11_Y, Y => MX2_333_Y);
|
| 2830 |
|
|
MX2_350 : MX2
|
| 2831 |
|
|
port map(A => MX2_187_Y, B => QAX_TEMPR14_9_net, S =>
|
| 2832 |
|
|
BUFF_31_Y, Y => MX2_350_Y);
|
| 2833 |
|
|
MX2_264 : MX2
|
| 2834 |
|
|
port map(A => QAX_TEMPR10_13_net, B => QAX_TEMPR11_13_net,
|
| 2835 |
|
|
S => BUFF_15_Y, Y => MX2_264_Y);
|
| 2836 |
|
|
MX2_52 : MX2
|
| 2837 |
|
|
port map(A => MX2_325_Y, B => QBX_TEMPR14_7_net, S =>
|
| 2838 |
|
|
BUFF_25_Y, Y => MX2_52_Y);
|
| 2839 |
|
|
NAND2_ENABLE_ADDRB_0_inst : NAND2
|
| 2840 |
|
|
port map(A => NOR2_1_Y, B => NOR2_0_Y, Y =>
|
| 2841 |
|
|
ENABLE_ADDRB_0_net);
|
| 2842 |
|
|
MX2_81 : MX2
|
| 2843 |
|
|
port map(A => QAX_TEMPR4_14_net, B => QAX_TEMPR5_14_net,
|
| 2844 |
|
|
S => BUFF_15_Y, Y => MX2_81_Y);
|
| 2845 |
|
|
MX2_375 : MX2
|
| 2846 |
|
|
port map(A => QAX_TEMPR12_2_net, B => QAX_TEMPR13_2_net,
|
| 2847 |
|
|
S => BUFF_0_Y, Y => MX2_375_Y);
|
| 2848 |
|
|
MX2_306 : MX2
|
| 2849 |
|
|
port map(A => QAX_TEMPR0_12_net, B => QAX_TEMPR1_12_net,
|
| 2850 |
|
|
S => BUFF_37_Y, Y => MX2_306_Y);
|
| 2851 |
|
|
BFF1_0_inst : DFN1
|
| 2852 |
|
|
port map(D => ADDRB(10), CLK => CLKB, Q => ADDRB_FF2_0_net);
|
| 2853 |
|
|
MX2_92 : MX2
|
| 2854 |
|
|
port map(A => MX2_24_Y, B => MX2_358_Y, S => BUFF_30_Y,
|
| 2855 |
|
|
Y => MX2_92_Y);
|
| 2856 |
|
|
dual_port_memory_R12C3 : RAM4K9
|
| 2857 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2858 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2859 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2860 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2861 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2862 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2863 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2864 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2865 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2866 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2867 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2868 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 2869 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 2870 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2871 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2872 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 2873 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2874 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2875 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2876 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_12_net,
|
| 2877 |
|
|
BLKB => BLKB_EN_12_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2878 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2879 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2880 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR12_15_net, DOUTA2 =>
|
| 2881 |
|
|
QAX_TEMPR12_14_net, DOUTA1 => QAX_TEMPR12_13_net,
|
| 2882 |
|
|
DOUTA0 => QAX_TEMPR12_12_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 2883 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2884 |
|
|
DOUTB3 => QBX_TEMPR12_15_net, DOUTB2 =>
|
| 2885 |
|
|
QBX_TEMPR12_14_net, DOUTB1 => QBX_TEMPR12_13_net,
|
| 2886 |
|
|
DOUTB0 => QBX_TEMPR12_12_net);
|
| 2887 |
|
|
MX2_88 : MX2
|
| 2888 |
|
|
port map(A => MX2_306_Y, B => MX2_312_Y, S => BUFF_8_Y,
|
| 2889 |
|
|
Y => MX2_88_Y);
|
| 2890 |
|
|
MX2_216 : MX2
|
| 2891 |
|
|
port map(A => MX2_163_Y, B => MX2_243_Y, S =>
|
| 2892 |
|
|
ADDRA_FF2_2_net, Y => MX2_216_Y);
|
| 2893 |
|
|
BUFF_14 : BUFF
|
| 2894 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_14_Y);
|
| 2895 |
|
|
NAND2_ENABLE_ADDRA_4_inst : NAND2
|
| 2896 |
|
|
port map(A => NOR2_2_Y, B => AND2A_5_Y, Y =>
|
| 2897 |
|
|
ENABLE_ADDRA_4_net);
|
| 2898 |
|
|
MX2_230 : MX2
|
| 2899 |
|
|
port map(A => QBX_TEMPR0_4_net, B => QBX_TEMPR1_4_net, S =>
|
| 2900 |
|
|
BUFF_12_Y, Y => MX2_230_Y);
|
| 2901 |
|
|
MX2_131 : MX2
|
| 2902 |
|
|
port map(A => MX2_376_Y, B => MX2_173_Y, S =>
|
| 2903 |
|
|
ADDRB_FF2_2_net, Y => MX2_131_Y);
|
| 2904 |
|
|
MX2_286 : MX2
|
| 2905 |
|
|
port map(A => MX2_311_Y, B => MX2_60_Y, S =>
|
| 2906 |
|
|
ADDRB_FF2_2_net, Y => MX2_286_Y);
|
| 2907 |
|
|
ORB_GATE_12_inst : OR2
|
| 2908 |
|
|
port map(A => ENABLE_ADDRB_12_net, B => WEBP, Y =>
|
| 2909 |
|
|
BLKB_EN_12_net);
|
| 2910 |
|
|
dual_port_memory_R2C0 : RAM4K9
|
| 2911 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2912 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2913 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2914 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2915 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2916 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2917 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2918 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2919 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2920 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2921 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2922 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 2923 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 2924 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2925 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2926 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 2927 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2928 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2929 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2930 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_2_net,
|
| 2931 |
|
|
BLKB => BLKB_EN_2_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2932 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2933 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2934 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR2_3_net, DOUTA2 =>
|
| 2935 |
|
|
QAX_TEMPR2_2_net, DOUTA1 => QAX_TEMPR2_1_net, DOUTA0 =>
|
| 2936 |
|
|
QAX_TEMPR2_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2937 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 2938 |
|
|
DOUTB3 => QBX_TEMPR2_3_net, DOUTB2 => QBX_TEMPR2_2_net,
|
| 2939 |
|
|
DOUTB1 => QBX_TEMPR2_1_net, DOUTB0 => QBX_TEMPR2_0_net);
|
| 2940 |
|
|
MX2_302 : MX2
|
| 2941 |
|
|
port map(A => QBX_TEMPR12_15_net, B => QBX_TEMPR13_15_net,
|
| 2942 |
|
|
S => BUFF_16_Y, Y => MX2_302_Y);
|
| 2943 |
|
|
MX2_103 : MX2
|
| 2944 |
|
|
port map(A => QBX_TEMPR8_3_net, B => QBX_TEMPR9_3_net, S =>
|
| 2945 |
|
|
BUFF_5_Y, Y => MX2_103_Y);
|
| 2946 |
|
|
BUFF_24 : BUFF
|
| 2947 |
|
|
port map(A => ADDRB_FF2_0_net, Y => BUFF_24_Y);
|
| 2948 |
|
|
MX2_309 : MX2
|
| 2949 |
|
|
port map(A => QAX_TEMPR12_6_net, B => QAX_TEMPR13_6_net,
|
| 2950 |
|
|
S => BUFF_10_Y, Y => MX2_309_Y);
|
| 2951 |
|
|
MX2_272 : MX2
|
| 2952 |
|
|
port map(A => QBX_TEMPR8_8_net, B => QBX_TEMPR9_8_net, S =>
|
| 2953 |
|
|
BUFF_34_Y, Y => MX2_272_Y);
|
| 2954 |
|
|
MX2_235 : MX2
|
| 2955 |
|
|
port map(A => QAX_TEMPR10_4_net, B => QAX_TEMPR11_4_net,
|
| 2956 |
|
|
S => BUFF_22_Y, Y => MX2_235_Y);
|
| 2957 |
|
|
MX2_331 : MX2
|
| 2958 |
|
|
port map(A => QBX_TEMPR8_11_net, B => QBX_TEMPR9_11_net,
|
| 2959 |
|
|
S => BUFF_39_Y, Y => MX2_331_Y);
|
| 2960 |
|
|
MX2_47 : MX2
|
| 2961 |
|
|
port map(A => MX2_121_Y, B => MX2_23_Y, S => BUFF_36_Y,
|
| 2962 |
|
|
Y => MX2_47_Y);
|
| 2963 |
|
|
MX2_24 : MX2
|
| 2964 |
|
|
port map(A => QAX_TEMPR8_15_net, B => QAX_TEMPR9_15_net,
|
| 2965 |
|
|
S => BUFF_9_Y, Y => MX2_24_Y);
|
| 2966 |
|
|
MX2_DOUTB_7_inst : MX2
|
| 2967 |
|
|
port map(A => MX2_254_Y, B => MX2_340_Y, S =>
|
| 2968 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(7));
|
| 2969 |
|
|
MX2_DOUTA_13_inst : MX2
|
| 2970 |
|
|
port map(A => MX2_105_Y, B => MX2_26_Y, S =>
|
| 2971 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(13));
|
| 2972 |
|
|
dual_port_memory_R14C1 : RAM4K9
|
| 2973 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 2974 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 2975 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 2976 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 2977 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 2978 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 2979 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 2980 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 2981 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 2982 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 2983 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 2984 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 2985 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 2986 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 2987 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 2988 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 2989 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 2990 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 2991 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 2992 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_14_net,
|
| 2993 |
|
|
BLKB => BLKB_EN_14_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 2994 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 2995 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 2996 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR14_7_net, DOUTA2 =>
|
| 2997 |
|
|
QAX_TEMPR14_6_net, DOUTA1 => QAX_TEMPR14_5_net, DOUTA0 =>
|
| 2998 |
|
|
QAX_TEMPR14_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 2999 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3000 |
|
|
DOUTB3 => QBX_TEMPR14_7_net, DOUTB2 => QBX_TEMPR14_6_net,
|
| 3001 |
|
|
DOUTB1 => QBX_TEMPR14_5_net, DOUTB0 => QBX_TEMPR14_4_net);
|
| 3002 |
|
|
MX2_178 : MX2
|
| 3003 |
|
|
port map(A => QAX_TEMPR8_4_net, B => QAX_TEMPR9_4_net, S =>
|
| 3004 |
|
|
BUFF_22_Y, Y => MX2_178_Y);
|
| 3005 |
|
|
MX2_114 : MX2
|
| 3006 |
|
|
port map(A => QBX_TEMPR0_6_net, B => QBX_TEMPR1_6_net, S =>
|
| 3007 |
|
|
BUFF_6_Y, Y => MX2_114_Y);
|
| 3008 |
|
|
MX2_59 : MX2
|
| 3009 |
|
|
port map(A => MX2_120_Y, B => MX2_169_Y, S =>
|
| 3010 |
|
|
ADDRA_FF2_2_net, Y => MX2_59_Y);
|
| 3011 |
|
|
dual_port_memory_R12C1 : RAM4K9
|
| 3012 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3013 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3014 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3015 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3016 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3017 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3018 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3019 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3020 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3021 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3022 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3023 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 3024 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 3025 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3026 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3027 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 3028 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3029 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3030 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3031 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_12_net,
|
| 3032 |
|
|
BLKB => BLKB_EN_12_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3033 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3034 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3035 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR12_7_net, DOUTA2 =>
|
| 3036 |
|
|
QAX_TEMPR12_6_net, DOUTA1 => QAX_TEMPR12_5_net, DOUTA0 =>
|
| 3037 |
|
|
QAX_TEMPR12_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3038 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3039 |
|
|
DOUTB3 => QBX_TEMPR12_7_net, DOUTB2 => QBX_TEMPR12_6_net,
|
| 3040 |
|
|
DOUTB1 => QBX_TEMPR12_5_net, DOUTB0 => QBX_TEMPR12_4_net);
|
| 3041 |
|
|
dual_port_memory_R5C3 : RAM4K9
|
| 3042 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3043 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3044 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3045 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3046 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3047 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3048 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3049 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3050 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3051 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3052 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3053 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 3054 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 3055 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3056 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3057 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 3058 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3059 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3060 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3061 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_5_net,
|
| 3062 |
|
|
BLKB => BLKB_EN_5_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3063 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3064 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3065 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR5_15_net, DOUTA2 =>
|
| 3066 |
|
|
QAX_TEMPR5_14_net, DOUTA1 => QAX_TEMPR5_13_net, DOUTA0 =>
|
| 3067 |
|
|
QAX_TEMPR5_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3068 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3069 |
|
|
DOUTB3 => QBX_TEMPR5_15_net, DOUTB2 => QBX_TEMPR5_14_net,
|
| 3070 |
|
|
DOUTB1 => QBX_TEMPR5_13_net, DOUTB0 => QBX_TEMPR5_12_net);
|
| 3071 |
|
|
MX2_366 : MX2
|
| 3072 |
|
|
port map(A => QBX_TEMPR4_4_net, B => QBX_TEMPR5_4_net, S =>
|
| 3073 |
|
|
BUFF_12_Y, Y => MX2_366_Y);
|
| 3074 |
|
|
MX2_318 : MX2
|
| 3075 |
|
|
port map(A => QBX_TEMPR12_12_net, B => QBX_TEMPR13_12_net,
|
| 3076 |
|
|
S => BUFF_24_Y, Y => MX2_318_Y);
|
| 3077 |
|
|
ORA_GATE_8_inst : OR2
|
| 3078 |
|
|
port map(A => ENABLE_ADDRA_8_net, B => WEAP, Y =>
|
| 3079 |
|
|
BLKA_EN_8_net);
|
| 3080 |
|
|
MX2_127 : MX2
|
| 3081 |
|
|
port map(A => MX2_197_Y, B => MX2_410_Y, S => BUFF_31_Y,
|
| 3082 |
|
|
Y => MX2_127_Y);
|
| 3083 |
|
|
MX2_3 : MX2
|
| 3084 |
|
|
port map(A => QBX_TEMPR0_9_net, B => QBX_TEMPR1_9_net, S =>
|
| 3085 |
|
|
BUFF_34_Y, Y => MX2_3_Y);
|
| 3086 |
|
|
MX2_99 : MX2
|
| 3087 |
|
|
port map(A => MX2_135_Y, B => MX2_303_Y, S => BUFF_17_Y,
|
| 3088 |
|
|
Y => MX2_99_Y);
|
| 3089 |
|
|
MX2_313 : MX2
|
| 3090 |
|
|
port map(A => MX2_144_Y, B => MX2_20_Y, S =>
|
| 3091 |
|
|
ADDRB_FF2_2_net, Y => MX2_313_Y);
|
| 3092 |
|
|
MX2_184 : MX2
|
| 3093 |
|
|
port map(A => MX2_212_Y, B => QBX_TEMPR14_8_net, S =>
|
| 3094 |
|
|
BUFF_1_Y, Y => MX2_184_Y);
|
| 3095 |
|
|
dual_port_memory_R7C0 : RAM4K9
|
| 3096 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3097 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3098 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3099 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3100 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3101 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3102 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3103 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3104 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3105 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3106 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3107 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 3108 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 3109 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3110 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3111 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 3112 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3113 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3114 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3115 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_7_net,
|
| 3116 |
|
|
BLKB => BLKB_EN_7_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3117 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3118 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3119 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR7_3_net, DOUTA2 =>
|
| 3120 |
|
|
QAX_TEMPR7_2_net, DOUTA1 => QAX_TEMPR7_1_net, DOUTA0 =>
|
| 3121 |
|
|
QAX_TEMPR7_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3122 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3123 |
|
|
DOUTB3 => QBX_TEMPR7_3_net, DOUTB2 => QBX_TEMPR7_2_net,
|
| 3124 |
|
|
DOUTB1 => QBX_TEMPR7_1_net, DOUTB0 => QBX_TEMPR7_0_net);
|
| 3125 |
|
|
MX2_354 : MX2
|
| 3126 |
|
|
port map(A => MX2_39_Y, B => MX2_45_Y, S => ADDRA_FF2_2_net,
|
| 3127 |
|
|
Y => MX2_354_Y);
|
| 3128 |
|
|
MX2_412 : MX2
|
| 3129 |
|
|
port map(A => MX2_149_Y, B => MX2_71_Y, S =>
|
| 3130 |
|
|
ADDRA_FF2_2_net, Y => MX2_412_Y);
|
| 3131 |
|
|
MX2_388 : MX2
|
| 3132 |
|
|
port map(A => QAX_TEMPR0_5_net, B => QAX_TEMPR1_5_net, S =>
|
| 3133 |
|
|
BUFF_22_Y, Y => MX2_388_Y);
|
| 3134 |
|
|
MX2_139 : MX2
|
| 3135 |
|
|
port map(A => QAX_TEMPR4_0_net, B => QAX_TEMPR5_0_net, S =>
|
| 3136 |
|
|
BUFF_18_Y, Y => MX2_139_Y);
|
| 3137 |
|
|
MX2_383 : MX2
|
| 3138 |
|
|
port map(A => MX2_40_Y, B => QAX_TEMPR14_4_net, S =>
|
| 3139 |
|
|
BUFF_35_Y, Y => MX2_383_Y);
|
| 3140 |
|
|
ORA_GATE_10_inst : OR2
|
| 3141 |
|
|
port map(A => ENABLE_ADDRA_10_net, B => WEAP, Y =>
|
| 3142 |
|
|
BLKA_EN_10_net);
|
| 3143 |
|
|
MX2_12 : MX2
|
| 3144 |
|
|
port map(A => MX2_255_Y, B => MX2_344_Y, S => BUFF_25_Y,
|
| 3145 |
|
|
Y => MX2_12_Y);
|
| 3146 |
|
|
MX2_249 : MX2
|
| 3147 |
|
|
port map(A => MX2_134_Y, B => MX2_386_Y, S => BUFF_25_Y,
|
| 3148 |
|
|
Y => MX2_249_Y);
|
| 3149 |
|
|
AND2_2 : AND2
|
| 3150 |
|
|
port map(A => ADDRA(11), B => ADDRA(10), Y => AND2_2_Y);
|
| 3151 |
|
|
MX2_362 : MX2
|
| 3152 |
|
|
port map(A => MX2_276_Y, B => MX2_90_Y, S => BUFF_27_Y,
|
| 3153 |
|
|
Y => MX2_362_Y);
|
| 3154 |
|
|
MX2_102 : MX2
|
| 3155 |
|
|
port map(A => MX2_43_Y, B => MX2_89_Y, S => BUFF_7_Y, Y =>
|
| 3156 |
|
|
MX2_102_Y);
|
| 3157 |
|
|
MX2_163 : MX2
|
| 3158 |
|
|
port map(A => MX2_37_Y, B => MX2_86_Y, S => BUFF_27_Y, Y =>
|
| 3159 |
|
|
MX2_163_Y);
|
| 3160 |
|
|
MX2_335 : MX2
|
| 3161 |
|
|
port map(A => MX2_70_Y, B => MX2_345_Y, S =>
|
| 3162 |
|
|
ADDRA_FF2_2_net, Y => MX2_335_Y);
|
| 3163 |
|
|
MX2_210 : MX2
|
| 3164 |
|
|
port map(A => MX2_176_Y, B => MX2_159_Y, S =>
|
| 3165 |
|
|
ADDRB_FF2_2_net, Y => MX2_210_Y);
|
| 3166 |
|
|
NAND2_ENABLE_ADDRB_7_inst : NAND2
|
| 3167 |
|
|
port map(A => AND2_1_Y, B => AND2A_0_Y, Y =>
|
| 3168 |
|
|
ENABLE_ADDRB_7_net);
|
| 3169 |
|
|
dual_port_memory_R0C1 : RAM4K9
|
| 3170 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3171 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3172 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3173 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3174 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3175 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3176 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3177 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3178 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3179 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3180 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3181 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 3182 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 3183 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3184 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3185 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 3186 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3187 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3188 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3189 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_0_net,
|
| 3190 |
|
|
BLKB => BLKB_EN_0_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3191 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3192 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3193 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR0_7_net, DOUTA2 =>
|
| 3194 |
|
|
QAX_TEMPR0_6_net, DOUTA1 => QAX_TEMPR0_5_net, DOUTA0 =>
|
| 3195 |
|
|
QAX_TEMPR0_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3196 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3197 |
|
|
DOUTB3 => QBX_TEMPR0_7_net, DOUTB2 => QBX_TEMPR0_6_net,
|
| 3198 |
|
|
DOUTB1 => QBX_TEMPR0_5_net, DOUTB0 => QBX_TEMPR0_4_net);
|
| 3199 |
|
|
MX2_369 : MX2
|
| 3200 |
|
|
port map(A => QAX_TEMPR0_13_net, B => QAX_TEMPR1_13_net,
|
| 3201 |
|
|
S => BUFF_37_Y, Y => MX2_369_Y);
|
| 3202 |
|
|
MX2_274 : MX2
|
| 3203 |
|
|
port map(A => QBX_TEMPR2_0_net, B => QBX_TEMPR3_0_net, S =>
|
| 3204 |
|
|
BUFF_23_Y, Y => MX2_274_Y);
|
| 3205 |
|
|
MX2_111 : MX2
|
| 3206 |
|
|
port map(A => MX2_77_Y, B => MX2_372_Y, S => BUFF_1_Y, Y =>
|
| 3207 |
|
|
MX2_111_Y);
|
| 3208 |
|
|
BUFF_15 : BUFF
|
| 3209 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_15_Y);
|
| 3210 |
|
|
BUFF_10 : BUFF
|
| 3211 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_10_Y);
|
| 3212 |
|
|
MX2_404 : MX2
|
| 3213 |
|
|
port map(A => MX2_359_Y, B => MX2_245_Y, S => BUFF_4_Y,
|
| 3214 |
|
|
Y => MX2_404_Y);
|
| 3215 |
|
|
dual_port_memory_R5C0 : RAM4K9
|
| 3216 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3217 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3218 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3219 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3220 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3221 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3222 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3223 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3224 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3225 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3226 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3227 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 3228 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 3229 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3230 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3231 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 3232 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3233 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3234 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3235 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_5_net,
|
| 3236 |
|
|
BLKB => BLKB_EN_5_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3237 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3238 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3239 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR5_3_net, DOUTA2 =>
|
| 3240 |
|
|
QAX_TEMPR5_2_net, DOUTA1 => QAX_TEMPR5_1_net, DOUTA0 =>
|
| 3241 |
|
|
QAX_TEMPR5_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3242 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3243 |
|
|
DOUTB3 => QBX_TEMPR5_3_net, DOUTB2 => QBX_TEMPR5_2_net,
|
| 3244 |
|
|
DOUTB1 => QBX_TEMPR5_1_net, DOUTB0 => QBX_TEMPR5_0_net);
|
| 3245 |
|
|
MX2_280 : MX2
|
| 3246 |
|
|
port map(A => QAX_TEMPR2_15_net, B => QAX_TEMPR3_15_net,
|
| 3247 |
|
|
S => BUFF_9_Y, Y => MX2_280_Y);
|
| 3248 |
|
|
MX2_181 : MX2
|
| 3249 |
|
|
port map(A => MX2_124_Y, B => MX2_231_Y, S => BUFF_35_Y,
|
| 3250 |
|
|
Y => MX2_181_Y);
|
| 3251 |
|
|
MX2_197 : MX2
|
| 3252 |
|
|
port map(A => QAX_TEMPR8_8_net, B => QAX_TEMPR9_8_net, S =>
|
| 3253 |
|
|
BUFF_11_Y, Y => MX2_197_Y);
|
| 3254 |
|
|
MX2_347 : MX2
|
| 3255 |
|
|
port map(A => MX2_204_Y, B => MX2_393_Y, S =>
|
| 3256 |
|
|
ADDRB_FF2_2_net, Y => MX2_347_Y);
|
| 3257 |
|
|
MX2_215 : MX2
|
| 3258 |
|
|
port map(A => QBX_TEMPR0_8_net, B => QBX_TEMPR1_8_net, S =>
|
| 3259 |
|
|
BUFF_34_Y, Y => MX2_215_Y);
|
| 3260 |
|
|
MX2_311 : MX2
|
| 3261 |
|
|
port map(A => MX2_68_Y, B => MX2_6_Y, S => BUFF_13_Y, Y =>
|
| 3262 |
|
|
MX2_311_Y);
|
| 3263 |
|
|
MX2_DOUTA_8_inst : MX2
|
| 3264 |
|
|
port map(A => MX2_288_Y, B => MX2_106_Y, S =>
|
| 3265 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(8));
|
| 3266 |
|
|
MX2_243 : MX2
|
| 3267 |
|
|
port map(A => MX2_309_Y, B => QAX_TEMPR14_6_net, S =>
|
| 3268 |
|
|
BUFF_27_Y, Y => MX2_243_Y);
|
| 3269 |
|
|
MX2_DOUTB_5_inst : MX2
|
| 3270 |
|
|
port map(A => MX2_373_Y, B => MX2_313_Y, S =>
|
| 3271 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(5));
|
| 3272 |
|
|
NAND2_ENABLE_ADDRB_8_inst : NAND2
|
| 3273 |
|
|
port map(A => NOR2_1_Y, B => AND2A_6_Y, Y =>
|
| 3274 |
|
|
ENABLE_ADDRB_8_net);
|
| 3275 |
|
|
dual_port_memory_R11C1 : RAM4K9
|
| 3276 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3277 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3278 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3279 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3280 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3281 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3282 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3283 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3284 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3285 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3286 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3287 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(7),
|
| 3288 |
|
|
DINA2 => DINA(6), DINA1 => DINA(5), DINA0 => DINA(4),
|
| 3289 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3290 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3291 |
|
|
DINB3 => DINB(7), DINB2 => DINB(6), DINB1 => DINB(5),
|
| 3292 |
|
|
DINB0 => DINB(4), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3293 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3294 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3295 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_11_net,
|
| 3296 |
|
|
BLKB => BLKB_EN_11_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3297 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3298 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3299 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR11_7_net, DOUTA2 =>
|
| 3300 |
|
|
QAX_TEMPR11_6_net, DOUTA1 => QAX_TEMPR11_5_net, DOUTA0 =>
|
| 3301 |
|
|
QAX_TEMPR11_4_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3302 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3303 |
|
|
DOUTB3 => QBX_TEMPR11_7_net, DOUTB2 => QBX_TEMPR11_6_net,
|
| 3304 |
|
|
DOUTB1 => QBX_TEMPR11_5_net, DOUTB0 => QBX_TEMPR11_4_net);
|
| 3305 |
|
|
BUFF_25 : BUFF
|
| 3306 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_25_Y);
|
| 3307 |
|
|
BUFF_20 : BUFF
|
| 3308 |
|
|
port map(A => ADDRA_FF2_0_net, Y => BUFF_20_Y);
|
| 3309 |
|
|
MX2_34 : MX2
|
| 3310 |
|
|
port map(A => QBX_TEMPR10_12_net, B => QBX_TEMPR11_12_net,
|
| 3311 |
|
|
S => BUFF_24_Y, Y => MX2_34_Y);
|
| 3312 |
|
|
MX2_285 : MX2
|
| 3313 |
|
|
port map(A => QAX_TEMPR4_3_net, B => QAX_TEMPR5_3_net, S =>
|
| 3314 |
|
|
BUFF_0_Y, Y => MX2_285_Y);
|
| 3315 |
|
|
MX2_381 : MX2
|
| 3316 |
|
|
port map(A => MX2_256_Y, B => MX2_94_Y, S => BUFF_13_Y,
|
| 3317 |
|
|
Y => MX2_381_Y);
|
| 3318 |
|
|
MX2_409 : MX2
|
| 3319 |
|
|
port map(A => MX2_46_Y, B => MX2_350_Y, S =>
|
| 3320 |
|
|
ADDRA_FF2_2_net, Y => MX2_409_Y);
|
| 3321 |
|
|
MX2_232 : MX2
|
| 3322 |
|
|
port map(A => MX2_336_Y, B => MX2_200_Y, S =>
|
| 3323 |
|
|
ADDRB_FF2_2_net, Y => MX2_232_Y);
|
| 3324 |
|
|
MX2_19 : MX2
|
| 3325 |
|
|
port map(A => MX2_56_Y, B => QBX_TEMPR14_10_net, S =>
|
| 3326 |
|
|
BUFF_19_Y, Y => MX2_19_Y);
|
| 3327 |
|
|
MX2_43 : MX2
|
| 3328 |
|
|
port map(A => QBX_TEMPR8_2_net, B => QBX_TEMPR9_2_net, S =>
|
| 3329 |
|
|
BUFF_33_Y, Y => MX2_43_Y);
|
| 3330 |
|
|
MX2_138 : MX2
|
| 3331 |
|
|
port map(A => MX2_333_Y, B => MX2_337_Y, S => BUFF_31_Y,
|
| 3332 |
|
|
Y => MX2_138_Y);
|
| 3333 |
|
|
AFF1_1_inst : DFN1
|
| 3334 |
|
|
port map(D => ADDRA(11), CLK => CLKA, Q => ADDRA_FF2_1_net);
|
| 3335 |
|
|
MX2_162 : MX2
|
| 3336 |
|
|
port map(A => QAX_TEMPR0_10_net, B => QAX_TEMPR1_10_net,
|
| 3337 |
|
|
S => BUFF_20_Y, Y => MX2_162_Y);
|
| 3338 |
|
|
MX2_DOUTA_7_inst : MX2
|
| 3339 |
|
|
port map(A => MX2_351_Y, B => MX2_327_Y, S =>
|
| 3340 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(7));
|
| 3341 |
|
|
MX2_119 : MX2
|
| 3342 |
|
|
port map(A => QBX_TEMPR2_4_net, B => QBX_TEMPR3_4_net, S =>
|
| 3343 |
|
|
BUFF_12_Y, Y => MX2_119_Y);
|
| 3344 |
|
|
MX2_150 : MX2
|
| 3345 |
|
|
port map(A => MX2_9_Y, B => MX2_387_Y, S => ADDRA_FF2_2_net,
|
| 3346 |
|
|
Y => MX2_150_Y);
|
| 3347 |
|
|
MX2_248 : MX2
|
| 3348 |
|
|
port map(A => QAX_TEMPR6_8_net, B => QAX_TEMPR7_8_net, S =>
|
| 3349 |
|
|
BUFF_11_Y, Y => MX2_248_Y);
|
| 3350 |
|
|
MX2_376 : MX2
|
| 3351 |
|
|
port map(A => MX2_202_Y, B => MX2_180_Y, S => BUFF_36_Y,
|
| 3352 |
|
|
Y => MX2_376_Y);
|
| 3353 |
|
|
MX2_189 : MX2
|
| 3354 |
|
|
port map(A => QAX_TEMPR12_14_net, B => QAX_TEMPR13_14_net,
|
| 3355 |
|
|
S => BUFF_9_Y, Y => MX2_189_Y);
|
| 3356 |
|
|
MX2_20 : MX2
|
| 3357 |
|
|
port map(A => MX2_300_Y, B => QBX_TEMPR14_5_net, S =>
|
| 3358 |
|
|
BUFF_29_Y, Y => MX2_20_Y);
|
| 3359 |
|
|
MX2_146 : MX2
|
| 3360 |
|
|
port map(A => QAX_TEMPR0_6_net, B => QAX_TEMPR1_6_net, S =>
|
| 3361 |
|
|
BUFF_26_Y, Y => MX2_146_Y);
|
| 3362 |
|
|
MX2_315 : MX2
|
| 3363 |
|
|
port map(A => QBX_TEMPR4_5_net, B => QBX_TEMPR5_5_net, S =>
|
| 3364 |
|
|
BUFF_12_Y, Y => MX2_315_Y);
|
| 3365 |
|
|
MX2_145 : MX2
|
| 3366 |
|
|
port map(A => QBX_TEMPR2_3_net, B => QBX_TEMPR3_3_net, S =>
|
| 3367 |
|
|
BUFF_5_Y, Y => MX2_145_Y);
|
| 3368 |
|
|
dual_port_memory_R2C2 : RAM4K9
|
| 3369 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3370 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3371 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3372 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3373 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3374 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3375 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3376 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3377 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3378 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3379 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3380 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 3381 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 3382 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3383 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3384 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 3385 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3386 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3387 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3388 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_2_net,
|
| 3389 |
|
|
BLKB => BLKB_EN_2_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3390 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3391 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3392 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR2_11_net, DOUTA2 =>
|
| 3393 |
|
|
QAX_TEMPR2_10_net, DOUTA1 => QAX_TEMPR2_9_net, DOUTA0 =>
|
| 3394 |
|
|
QAX_TEMPR2_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3395 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3396 |
|
|
DOUTB3 => QBX_TEMPR2_11_net, DOUTB2 => QBX_TEMPR2_10_net,
|
| 3397 |
|
|
DOUTB1 => QBX_TEMPR2_9_net, DOUTB0 => QBX_TEMPR2_8_net);
|
| 3398 |
|
|
MX2_340 : MX2
|
| 3399 |
|
|
port map(A => MX2_201_Y, B => MX2_52_Y, S =>
|
| 3400 |
|
|
ADDRB_FF2_2_net, Y => MX2_340_Y);
|
| 3401 |
|
|
MX2_385 : MX2
|
| 3402 |
|
|
port map(A => MX2_133_Y, B => MX2_12_Y, S =>
|
| 3403 |
|
|
ADDRB_FF2_2_net, Y => MX2_385_Y);
|
| 3404 |
|
|
MX2_72 : MX2
|
| 3405 |
|
|
port map(A => MX2_318_Y, B => QBX_TEMPR14_12_net, S =>
|
| 3406 |
|
|
BUFF_4_Y, Y => MX2_72_Y);
|
| 3407 |
|
|
MX2_234 : MX2
|
| 3408 |
|
|
port map(A => QBX_TEMPR4_10_net, B => QBX_TEMPR5_10_net,
|
| 3409 |
|
|
S => BUFF_28_Y, Y => MX2_234_Y);
|
| 3410 |
|
|
MX2_372 : MX2
|
| 3411 |
|
|
port map(A => QBX_TEMPR10_9_net, B => QBX_TEMPR11_9_net,
|
| 3412 |
|
|
S => BUFF_28_Y, Y => MX2_372_Y);
|
| 3413 |
|
|
MX2_173 : MX2
|
| 3414 |
|
|
port map(A => MX2_61_Y, B => MX2_265_Y, S => BUFF_36_Y,
|
| 3415 |
|
|
Y => MX2_173_Y);
|
| 3416 |
|
|
BUFF_32 : BUFF
|
| 3417 |
|
|
port map(A => ADDRA_FF2_1_net, Y => BUFF_32_Y);
|
| 3418 |
|
|
dual_port_memory_R4C3 : RAM4K9
|
| 3419 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3420 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3421 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3422 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3423 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3424 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3425 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3426 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3427 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3428 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3429 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3430 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 3431 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 3432 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3433 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3434 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 3435 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3436 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3437 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3438 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_4_net,
|
| 3439 |
|
|
BLKB => BLKB_EN_4_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3440 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3441 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3442 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR4_15_net, DOUTA2 =>
|
| 3443 |
|
|
QAX_TEMPR4_14_net, DOUTA1 => QAX_TEMPR4_13_net, DOUTA0 =>
|
| 3444 |
|
|
QAX_TEMPR4_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3445 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3446 |
|
|
DOUTB3 => QBX_TEMPR4_15_net, DOUTB2 => QBX_TEMPR4_14_net,
|
| 3447 |
|
|
DOUTB1 => QBX_TEMPR4_13_net, DOUTB0 => QBX_TEMPR4_12_net);
|
| 3448 |
|
|
MX2_379 : MX2
|
| 3449 |
|
|
port map(A => MX2_290_Y, B => MX2_122_Y, S => BUFF_32_Y,
|
| 3450 |
|
|
Y => MX2_379_Y);
|
| 3451 |
|
|
MX2_62 : MX2
|
| 3452 |
|
|
port map(A => MX2_160_Y, B => MX2_214_Y, S => BUFF_13_Y,
|
| 3453 |
|
|
Y => MX2_62_Y);
|
| 3454 |
|
|
MX2_209 : MX2
|
| 3455 |
|
|
port map(A => MX2_294_Y, B => QAX_TEMPR14_15_net, S =>
|
| 3456 |
|
|
BUFF_30_Y, Y => MX2_209_Y);
|
| 3457 |
|
|
dual_port_memory_R5C2 : RAM4K9
|
| 3458 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3459 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3460 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3461 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3462 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3463 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3464 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3465 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3466 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3467 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3468 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3469 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 3470 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 3471 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3472 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3473 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 3474 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3475 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3476 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3477 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_5_net,
|
| 3478 |
|
|
BLKB => BLKB_EN_5_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3479 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3480 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3481 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR5_11_net, DOUTA2 =>
|
| 3482 |
|
|
QAX_TEMPR5_10_net, DOUTA1 => QAX_TEMPR5_9_net, DOUTA0 =>
|
| 3483 |
|
|
QAX_TEMPR5_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3484 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3485 |
|
|
DOUTB3 => QBX_TEMPR5_11_net, DOUTB2 => QBX_TEMPR5_10_net,
|
| 3486 |
|
|
DOUTB1 => QBX_TEMPR5_9_net, DOUTB0 => QBX_TEMPR5_8_net);
|
| 3487 |
|
|
MX2_221 : MX2
|
| 3488 |
|
|
port map(A => MX2_308_Y, B => QAX_TEMPR14_12_net, S =>
|
| 3489 |
|
|
BUFF_8_Y, Y => MX2_221_Y);
|
| 3490 |
|
|
ORB_GATE_9_inst : OR2
|
| 3491 |
|
|
port map(A => ENABLE_ADDRB_9_net, B => WEBP, Y =>
|
| 3492 |
|
|
BLKB_EN_9_net);
|
| 3493 |
|
|
MX2_212 : MX2
|
| 3494 |
|
|
port map(A => QBX_TEMPR12_8_net, B => QBX_TEMPR13_8_net,
|
| 3495 |
|
|
S => BUFF_34_Y, Y => MX2_212_Y);
|
| 3496 |
|
|
MX2_227 : MX2
|
| 3497 |
|
|
port map(A => MX2_100_Y, B => MX2_360_Y, S => BUFF_19_Y,
|
| 3498 |
|
|
Y => MX2_227_Y);
|
| 3499 |
|
|
MX2_41 : MX2
|
| 3500 |
|
|
port map(A => QBX_TEMPR8_0_net, B => QBX_TEMPR9_0_net, S =>
|
| 3501 |
|
|
BUFF_23_Y, Y => MX2_41_Y);
|
| 3502 |
|
|
MX2_118 : MX2
|
| 3503 |
|
|
port map(A => MX2_36_Y, B => MX2_218_Y, S => BUFF_27_Y,
|
| 3504 |
|
|
Y => MX2_118_Y);
|
| 3505 |
|
|
MX2_DOUTA_10_inst : MX2
|
| 3506 |
|
|
port map(A => MX2_186_Y, B => MX2_380_Y, S =>
|
| 3507 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(10));
|
| 3508 |
|
|
MX2_26 : MX2
|
| 3509 |
|
|
port map(A => MX2_11_Y, B => MX2_108_Y, S =>
|
| 3510 |
|
|
ADDRA_FF2_2_net, Y => MX2_26_Y);
|
| 3511 |
|
|
MX2_282 : MX2
|
| 3512 |
|
|
port map(A => QAX_TEMPR12_8_net, B => QAX_TEMPR13_8_net,
|
| 3513 |
|
|
S => BUFF_11_Y, Y => MX2_282_Y);
|
| 3514 |
|
|
MX2_48 : MX2
|
| 3515 |
|
|
port map(A => QAX_TEMPR6_9_net, B => QAX_TEMPR7_9_net, S =>
|
| 3516 |
|
|
BUFF_20_Y, Y => MX2_48_Y);
|
| 3517 |
|
|
MX2_55 : MX2
|
| 3518 |
|
|
port map(A => MX2_282_Y, B => QAX_TEMPR14_8_net, S =>
|
| 3519 |
|
|
BUFF_31_Y, Y => MX2_55_Y);
|
| 3520 |
|
|
MX2_188 : MX2
|
| 3521 |
|
|
port map(A => MX2_111_Y, B => MX2_116_Y, S =>
|
| 3522 |
|
|
ADDRB_FF2_2_net, Y => MX2_188_Y);
|
| 3523 |
|
|
AND2A_3 : AND2A
|
| 3524 |
|
|
port map(A => ADDRA(12), B => ADDRA(13), Y => AND2A_3_Y);
|
| 3525 |
|
|
MX2_307 : MX2
|
| 3526 |
|
|
port map(A => MX2_206_Y, B => MX2_72_Y, S =>
|
| 3527 |
|
|
ADDRB_FF2_2_net, Y => MX2_307_Y);
|
| 3528 |
|
|
MX2_95 : MX2
|
| 3529 |
|
|
port map(A => MX2_80_Y, B => MX2_229_Y, S => BUFF_19_Y,
|
| 3530 |
|
|
Y => MX2_95_Y);
|
| 3531 |
|
|
MX2_203 : MX2
|
| 3532 |
|
|
port map(A => QBX_TEMPR10_1_net, B => QBX_TEMPR11_1_net,
|
| 3533 |
|
|
S => BUFF_33_Y, Y => MX2_203_Y);
|
| 3534 |
|
|
ORA_GATE_3_inst : OR2
|
| 3535 |
|
|
port map(A => ENABLE_ADDRA_3_net, B => WEAP, Y =>
|
| 3536 |
|
|
BLKA_EN_3_net);
|
| 3537 |
|
|
MX2_79 : MX2
|
| 3538 |
|
|
port map(A => MX2_166_Y, B => MX2_378_Y, S => BUFF_8_Y,
|
| 3539 |
|
|
Y => MX2_79_Y);
|
| 3540 |
|
|
dual_port_memory_R4C2 : RAM4K9
|
| 3541 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3542 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3543 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3544 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3545 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3546 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3547 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3548 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3549 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3550 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3551 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3552 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 3553 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 3554 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3555 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3556 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 3557 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3558 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3559 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3560 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_4_net,
|
| 3561 |
|
|
BLKB => BLKB_EN_4_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3562 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3563 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3564 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR4_11_net, DOUTA2 =>
|
| 3565 |
|
|
QAX_TEMPR4_10_net, DOUTA1 => QAX_TEMPR4_9_net, DOUTA0 =>
|
| 3566 |
|
|
QAX_TEMPR4_8_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3567 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3568 |
|
|
DOUTB3 => QBX_TEMPR4_11_net, DOUTB2 => QBX_TEMPR4_10_net,
|
| 3569 |
|
|
DOUTB1 => QBX_TEMPR4_9_net, DOUTB0 => QBX_TEMPR4_8_net);
|
| 3570 |
|
|
MX2_30 : MX2
|
| 3571 |
|
|
port map(A => MX2_269_Y, B => QBX_TEMPR14_13_net, S =>
|
| 3572 |
|
|
BUFF_4_Y, Y => MX2_30_Y);
|
| 3573 |
|
|
MX2_172 : MX2
|
| 3574 |
|
|
port map(A => QBX_TEMPR0_13_net, B => QBX_TEMPR1_13_net,
|
| 3575 |
|
|
S => BUFF_24_Y, Y => MX2_172_Y);
|
| 3576 |
|
|
MX2_344 : MX2
|
| 3577 |
|
|
port map(A => QBX_TEMPR6_6_net, B => QBX_TEMPR7_6_net, S =>
|
| 3578 |
|
|
BUFF_6_Y, Y => MX2_344_Y);
|
| 3579 |
|
|
MX2_69 : MX2
|
| 3580 |
|
|
port map(A => MX2_330_Y, B => MX2_19_Y, S =>
|
| 3581 |
|
|
ADDRB_FF2_2_net, Y => MX2_69_Y);
|
| 3582 |
|
|
MX2_336 : MX2
|
| 3583 |
|
|
port map(A => MX2_103_Y, B => MX2_224_Y, S => BUFF_7_Y,
|
| 3584 |
|
|
Y => MX2_336_Y);
|
| 3585 |
|
|
NAND2_ENABLE_ADDRB_3_inst : NAND2
|
| 3586 |
|
|
port map(A => AND2_1_Y, B => NOR2_0_Y, Y =>
|
| 3587 |
|
|
ENABLE_ADDRB_3_net);
|
| 3588 |
|
|
MX2_269 : MX2
|
| 3589 |
|
|
port map(A => QBX_TEMPR12_13_net, B => QBX_TEMPR13_13_net,
|
| 3590 |
|
|
S => BUFF_2_Y, Y => MX2_269_Y);
|
| 3591 |
|
|
MX2_291 : MX2
|
| 3592 |
|
|
port map(A => QAX_TEMPR2_7_net, B => QAX_TEMPR3_7_net, S =>
|
| 3593 |
|
|
BUFF_10_Y, Y => MX2_291_Y);
|
| 3594 |
|
|
MX2_297 : MX2
|
| 3595 |
|
|
port map(A => QBX_TEMPR10_14_net, B => QBX_TEMPR11_14_net,
|
| 3596 |
|
|
S => BUFF_16_Y, Y => MX2_297_Y);
|
| 3597 |
|
|
MX2_214 : MX2
|
| 3598 |
|
|
port map(A => QBX_TEMPR6_15_net, B => QBX_TEMPR7_15_net,
|
| 3599 |
|
|
S => BUFF_16_Y, Y => MX2_214_Y);
|
| 3600 |
|
|
NOR2_0 : NOR2
|
| 3601 |
|
|
port map(A => ADDRB(13), B => ADDRB(12), Y => NOR2_0_Y);
|
| 3602 |
|
|
NAND2_ENABLE_ADDRB_9_inst : NAND2
|
| 3603 |
|
|
port map(A => AND2A_1_Y, B => AND2A_6_Y, Y =>
|
| 3604 |
|
|
ENABLE_ADDRB_9_net);
|
| 3605 |
|
|
MX2_208 : MX2
|
| 3606 |
|
|
port map(A => MX2_289_Y, B => MX2_165_Y, S =>
|
| 3607 |
|
|
ADDRB_FF2_2_net, Y => MX2_208_Y);
|
| 3608 |
|
|
dual_port_memory_R9C3 : RAM4K9
|
| 3609 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3610 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3611 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3612 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3613 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3614 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3615 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3616 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3617 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3618 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3619 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3620 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 3621 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 3622 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3623 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3624 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 3625 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3626 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3627 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3628 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_9_net,
|
| 3629 |
|
|
BLKB => BLKB_EN_9_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3630 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3631 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3632 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR9_15_net, DOUTA2 =>
|
| 3633 |
|
|
QAX_TEMPR9_14_net, DOUTA1 => QAX_TEMPR9_13_net, DOUTA0 =>
|
| 3634 |
|
|
QAX_TEMPR9_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3635 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3636 |
|
|
DOUTB3 => QBX_TEMPR9_15_net, DOUTB2 => QBX_TEMPR9_14_net,
|
| 3637 |
|
|
DOUTB1 => QBX_TEMPR9_13_net, DOUTB0 => QBX_TEMPR9_12_net);
|
| 3638 |
|
|
MX2_284 : MX2
|
| 3639 |
|
|
port map(A => MX2_130_Y, B => MX2_195_Y, S =>
|
| 3640 |
|
|
ADDRA_FF2_2_net, Y => MX2_284_Y);
|
| 3641 |
|
|
dual_port_memory_R10C3 : RAM4K9
|
| 3642 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3643 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3644 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3645 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3646 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3647 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3648 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3649 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3650 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3651 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3652 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3653 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 3654 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 3655 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3656 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3657 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 3658 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3659 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3660 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3661 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_10_net,
|
| 3662 |
|
|
BLKB => BLKB_EN_10_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3663 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3664 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3665 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR10_15_net, DOUTA2 =>
|
| 3666 |
|
|
QAX_TEMPR10_14_net, DOUTA1 => QAX_TEMPR10_13_net,
|
| 3667 |
|
|
DOUTA0 => QAX_TEMPR10_12_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 3668 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3669 |
|
|
DOUTB3 => QBX_TEMPR10_15_net, DOUTB2 =>
|
| 3670 |
|
|
QBX_TEMPR10_14_net, DOUTB1 => QBX_TEMPR10_13_net,
|
| 3671 |
|
|
DOUTB0 => QBX_TEMPR10_12_net);
|
| 3672 |
|
|
MX2_106 : MX2
|
| 3673 |
|
|
port map(A => MX2_127_Y, B => MX2_55_Y, S =>
|
| 3674 |
|
|
ADDRA_FF2_2_net, Y => MX2_106_Y);
|
| 3675 |
|
|
dual_port_memory_R14C2 : RAM4K9
|
| 3676 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3677 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3678 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3679 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3680 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3681 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3682 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3683 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3684 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3685 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3686 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3687 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(11),
|
| 3688 |
|
|
DINA2 => DINA(10), DINA1 => DINA(9), DINA0 => DINA(8),
|
| 3689 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3690 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3691 |
|
|
DINB3 => DINB(11), DINB2 => DINB(10), DINB1 => DINB(9),
|
| 3692 |
|
|
DINB0 => DINB(8), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3693 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3694 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3695 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_14_net,
|
| 3696 |
|
|
BLKB => BLKB_EN_14_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3697 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3698 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3699 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR14_11_net, DOUTA2 =>
|
| 3700 |
|
|
QAX_TEMPR14_10_net, DOUTA1 => QAX_TEMPR14_9_net,
|
| 3701 |
|
|
DOUTA0 => QAX_TEMPR14_8_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 3702 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3703 |
|
|
DOUTB3 => QBX_TEMPR14_11_net, DOUTB2 =>
|
| 3704 |
|
|
QBX_TEMPR14_10_net, DOUTB1 => QBX_TEMPR14_9_net,
|
| 3705 |
|
|
DOUTB0 => QBX_TEMPR14_8_net);
|
| 3706 |
|
|
MX2_332 : MX2
|
| 3707 |
|
|
port map(A => QAX_TEMPR2_0_net, B => QAX_TEMPR3_0_net, S =>
|
| 3708 |
|
|
BUFF_18_Y, Y => MX2_332_Y);
|
| 3709 |
|
|
MX2_DOUTB_13_inst : MX2
|
| 3710 |
|
|
port map(A => MX2_83_Y, B => MX2_259_Y, S =>
|
| 3711 |
|
|
ADDRB_FF2_3_net, Y => DOUTB(13));
|
| 3712 |
|
|
MX2_133 : MX2
|
| 3713 |
|
|
port map(A => MX2_114_Y, B => MX2_250_Y, S => BUFF_25_Y,
|
| 3714 |
|
|
Y => MX2_133_Y);
|
| 3715 |
|
|
MX2_157 : MX2
|
| 3716 |
|
|
port map(A => QBX_TEMPR12_3_net, B => QBX_TEMPR13_3_net,
|
| 3717 |
|
|
S => BUFF_5_Y, Y => MX2_157_Y);
|
| 3718 |
|
|
MX2_105 : MX2
|
| 3719 |
|
|
port map(A => MX2_399_Y, B => MX2_348_Y, S =>
|
| 3720 |
|
|
ADDRA_FF2_2_net, Y => MX2_105_Y);
|
| 3721 |
|
|
BUFF_36 : BUFF
|
| 3722 |
|
|
port map(A => ADDRB_FF2_1_net, Y => BUFF_36_Y);
|
| 3723 |
|
|
MX2_339 : MX2
|
| 3724 |
|
|
port map(A => MX2_192_Y, B => QBX_TEMPR14_14_net, S =>
|
| 3725 |
|
|
BUFF_13_Y, Y => MX2_339_Y);
|
| 3726 |
|
|
MX2_367 : MX2
|
| 3727 |
|
|
port map(A => MX2_125_Y, B => MX2_287_Y, S => BUFF_30_Y,
|
| 3728 |
|
|
Y => MX2_367_Y);
|
| 3729 |
|
|
MX2_263 : MX2
|
| 3730 |
|
|
port map(A => QAX_TEMPR12_11_net, B => QAX_TEMPR13_11_net,
|
| 3731 |
|
|
S => BUFF_14_Y, Y => MX2_263_Y);
|
| 3732 |
|
|
MX2_300 : MX2
|
| 3733 |
|
|
port map(A => QBX_TEMPR12_5_net, B => QBX_TEMPR13_5_net,
|
| 3734 |
|
|
S => BUFF_6_Y, Y => MX2_300_Y);
|
| 3735 |
|
|
ORB_GATE_1_inst : OR2
|
| 3736 |
|
|
port map(A => ENABLE_ADDRB_1_net, B => WEBP, Y =>
|
| 3737 |
|
|
BLKB_EN_1_net);
|
| 3738 |
|
|
MX2_36 : MX2
|
| 3739 |
|
|
port map(A => QAX_TEMPR8_7_net, B => QAX_TEMPR9_7_net, S =>
|
| 3740 |
|
|
BUFF_10_Y, Y => MX2_36_Y);
|
| 3741 |
|
|
MX2_15 : MX2
|
| 3742 |
|
|
port map(A => MX2_375_Y, B => QAX_TEMPR14_2_net, S =>
|
| 3743 |
|
|
BUFF_17_Y, Y => MX2_15_Y);
|
| 3744 |
|
|
dual_port_memory_R8C3 : RAM4K9
|
| 3745 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3746 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3747 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3748 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3749 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3750 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3751 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3752 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3753 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3754 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3755 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3756 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 3757 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 3758 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3759 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3760 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 3761 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3762 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3763 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3764 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_8_net,
|
| 3765 |
|
|
BLKB => BLKB_EN_8_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3766 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3767 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3768 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR8_15_net, DOUTA2 =>
|
| 3769 |
|
|
QAX_TEMPR8_14_net, DOUTA1 => QAX_TEMPR8_13_net, DOUTA0 =>
|
| 3770 |
|
|
QAX_TEMPR8_12_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3771 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3772 |
|
|
DOUTB3 => QBX_TEMPR8_15_net, DOUTB2 => QBX_TEMPR8_14_net,
|
| 3773 |
|
|
DOUTB1 => QBX_TEMPR8_13_net, DOUTB0 => QBX_TEMPR8_12_net);
|
| 3774 |
|
|
ORB_GATE_0_inst : OR2
|
| 3775 |
|
|
port map(A => ENABLE_ADDRB_0_net, B => WEBP, Y =>
|
| 3776 |
|
|
BLKB_EN_0_net);
|
| 3777 |
|
|
MX2_27 : MX2
|
| 3778 |
|
|
port map(A => QBX_TEMPR0_5_net, B => QBX_TEMPR1_5_net, S =>
|
| 3779 |
|
|
BUFF_12_Y, Y => MX2_27_Y);
|
| 3780 |
|
|
MX2_268 : MX2
|
| 3781 |
|
|
port map(A => MX2_334_Y, B => QAX_TEMPR14_5_net, S =>
|
| 3782 |
|
|
BUFF_35_Y, Y => MX2_268_Y);
|
| 3783 |
|
|
MX2_316 : MX2
|
| 3784 |
|
|
port map(A => QAX_TEMPR2_1_net, B => QAX_TEMPR3_1_net, S =>
|
| 3785 |
|
|
BUFF_18_Y, Y => MX2_316_Y);
|
| 3786 |
|
|
dual_port_memory_R3C0 : RAM4K9
|
| 3787 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3788 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3789 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3790 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3791 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3792 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3793 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3794 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3795 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3796 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3797 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3798 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(3),
|
| 3799 |
|
|
DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0),
|
| 3800 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3801 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3802 |
|
|
DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1),
|
| 3803 |
|
|
DINB0 => DINB(0), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3804 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3805 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3806 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_3_net,
|
| 3807 |
|
|
BLKB => BLKB_EN_3_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3808 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3809 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3810 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR3_3_net, DOUTA2 =>
|
| 3811 |
|
|
QAX_TEMPR3_2_net, DOUTA1 => QAX_TEMPR3_1_net, DOUTA0 =>
|
| 3812 |
|
|
QAX_TEMPR3_0_net, DOUTB8 => OPEN , DOUTB7 => OPEN ,
|
| 3813 |
|
|
DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3814 |
|
|
DOUTB3 => QBX_TEMPR3_3_net, DOUTB2 => QBX_TEMPR3_2_net,
|
| 3815 |
|
|
DOUTB1 => QBX_TEMPR3_1_net, DOUTB0 => QBX_TEMPR3_0_net);
|
| 3816 |
|
|
WEBUBBLEA : INV
|
| 3817 |
|
|
port map(A => BLKA, Y => WEAP);
|
| 3818 |
|
|
ORA_GATE_11_inst : OR2
|
| 3819 |
|
|
port map(A => ENABLE_ADDRA_11_net, B => WEAP, Y =>
|
| 3820 |
|
|
BLKA_EN_11_net);
|
| 3821 |
|
|
MX2_140 : MX2
|
| 3822 |
|
|
port map(A => QAX_TEMPR0_11_net, B => QAX_TEMPR1_11_net,
|
| 3823 |
|
|
S => BUFF_14_Y, Y => MX2_140_Y);
|
| 3824 |
|
|
MX2_166 : MX2
|
| 3825 |
|
|
port map(A => QAX_TEMPR8_12_net, B => QAX_TEMPR9_12_net,
|
| 3826 |
|
|
S => BUFF_37_Y, Y => MX2_166_Y);
|
| 3827 |
|
|
MX2_386 : MX2
|
| 3828 |
|
|
port map(A => QBX_TEMPR2_7_net, B => QBX_TEMPR3_7_net, S =>
|
| 3829 |
|
|
BUFF_3_Y, Y => MX2_386_Y);
|
| 3830 |
|
|
MX2_5 : MX2
|
| 3831 |
|
|
port map(A => MX2_398_Y, B => MX2_316_Y, S => BUFF_38_Y,
|
| 3832 |
|
|
Y => MX2_5_Y);
|
| 3833 |
|
|
MX2_132 : MX2
|
| 3834 |
|
|
port map(A => QAX_TEMPR10_5_net, B => QAX_TEMPR11_5_net,
|
| 3835 |
|
|
S => BUFF_26_Y, Y => MX2_132_Y);
|
| 3836 |
|
|
AND2A_5 : AND2A
|
| 3837 |
|
|
port map(A => ADDRA(13), B => ADDRA(12), Y => AND2A_5_Y);
|
| 3838 |
|
|
MX2_165 : MX2
|
| 3839 |
|
|
port map(A => MX2_115_Y, B => QBX_TEMPR14_1_net, S =>
|
| 3840 |
|
|
BUFF_36_Y, Y => MX2_165_Y);
|
| 3841 |
|
|
BFF1_2_inst : DFN1
|
| 3842 |
|
|
port map(D => ADDRB(12), CLK => CLKB, Q => ADDRB_FF2_2_net);
|
| 3843 |
|
|
MX2_DOUTA_15_inst : MX2
|
| 3844 |
|
|
port map(A => MX2_335_Y, B => MX2_126_Y, S =>
|
| 3845 |
|
|
ADDRA_FF2_3_net, Y => DOUTA(15));
|
| 3846 |
|
|
MX2_9 : MX2
|
| 3847 |
|
|
port map(A => MX2_402_Y, B => MX2_319_Y, S => BUFF_31_Y,
|
| 3848 |
|
|
Y => MX2_9_Y);
|
| 3849 |
|
|
MX2_82 : MX2
|
| 3850 |
|
|
port map(A => MX2_117_Y, B => MX2_291_Y, S => BUFF_27_Y,
|
| 3851 |
|
|
Y => MX2_82_Y);
|
| 3852 |
|
|
MX2_360 : MX2
|
| 3853 |
|
|
port map(A => QBX_TEMPR2_11_net, B => QBX_TEMPR3_11_net,
|
| 3854 |
|
|
S => BUFF_39_Y, Y => MX2_360_Y);
|
| 3855 |
|
|
dual_port_memory_R14C3 : RAM4K9
|
| 3856 |
|
|
port map(ADDRA11 => GND_1_net, ADDRA10 => GND_1_net,
|
| 3857 |
|
|
ADDRA9 => ADDRA(9), ADDRA8 => ADDRA(8), ADDRA7 =>
|
| 3858 |
|
|
ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5),
|
| 3859 |
|
|
ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 =>
|
| 3860 |
|
|
ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0),
|
| 3861 |
|
|
ADDRB11 => GND_1_net, ADDRB10 => GND_1_net, ADDRB9 =>
|
| 3862 |
|
|
ADDRB(9), ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7),
|
| 3863 |
|
|
ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 =>
|
| 3864 |
|
|
ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2),
|
| 3865 |
|
|
ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), DINA8 =>
|
| 3866 |
|
|
GND_1_net, DINA7 => GND_1_net, DINA6 => GND_1_net,
|
| 3867 |
|
|
DINA5 => GND_1_net, DINA4 => GND_1_net, DINA3 => DINA(15),
|
| 3868 |
|
|
DINA2 => DINA(14), DINA1 => DINA(13), DINA0 => DINA(12),
|
| 3869 |
|
|
DINB8 => GND_1_net, DINB7 => GND_1_net, DINB6 =>
|
| 3870 |
|
|
GND_1_net, DINB5 => GND_1_net, DINB4 => GND_1_net,
|
| 3871 |
|
|
DINB3 => DINB(15), DINB2 => DINB(14), DINB1 => DINB(13),
|
| 3872 |
|
|
DINB0 => DINB(12), WIDTHA0 => GND_1_net, WIDTHA1 =>
|
| 3873 |
|
|
VCC_1_net, WIDTHB0 => GND_1_net, WIDTHB1 => VCC_1_net,
|
| 3874 |
|
|
PIPEA => GND_1_net, PIPEB => GND_1_net, WMODEA =>
|
| 3875 |
|
|
VCC_1_net, WMODEB => VCC_1_net, BLKA => BLKA_EN_14_net,
|
| 3876 |
|
|
BLKB => BLKB_EN_14_net, WENA => RWA, WENB => RWB, CLKA =>
|
| 3877 |
|
|
CLKA, CLKB => CLKB, RESET => RESETP, DOUTA8 => OPEN ,
|
| 3878 |
|
|
DOUTA7 => OPEN , DOUTA6 => OPEN , DOUTA5 => OPEN ,
|
| 3879 |
|
|
DOUTA4 => OPEN , DOUTA3 => QAX_TEMPR14_15_net, DOUTA2 =>
|
| 3880 |
|
|
QAX_TEMPR14_14_net, DOUTA1 => QAX_TEMPR14_13_net,
|
| 3881 |
|
|
DOUTA0 => QAX_TEMPR14_12_net, DOUTB8 => OPEN , DOUTB7 =>
|
| 3882 |
|
|
OPEN , DOUTB6 => OPEN , DOUTB5 => OPEN , DOUTB4 => OPEN ,
|
| 3883 |
|
|
DOUTB3 => QBX_TEMPR14_15_net, DOUTB2 =>
|
| 3884 |
|
|
QBX_TEMPR14_14_net, DOUTB1 => QBX_TEMPR14_13_net,
|
| 3885 |
|
|
DOUTB0 => QBX_TEMPR14_12_net);
|
| 3886 |
|
|
MX2_312 : MX2
|
| 3887 |
|
|
port map(A => QAX_TEMPR2_12_net, B => QAX_TEMPR3_12_net,
|
| 3888 |
|
|
S => BUFF_37_Y, Y => MX2_312_Y);
|
| 3889 |
|
|
end DEF_ARCH;
|
