Subversion Repositories motion_estimation_processor

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--     solely for design, simulation, implementation and creation of          --

--     design files limited to Xilinx devices or technologies. Use            --

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--     (c) Copyright 1995-2004 Xilinx, Inc.                                   --

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-- You must compile the wrapper file current_macroblock_memory64.vhd when simulating

-- the core, current_macroblock_memory64. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;

ENTITY current_macroblock_memory64 IS

        port (

        addr: IN std_logic_VECTOR(4 downto 0);

        clk: IN std_logic;

        din: IN std_logic_VECTOR(63 downto 0);

        dout: OUT std_logic_VECTOR(63 downto 0);

        we: IN std_logic);

END current_macroblock_memory64;

ARCHITECTURE current_macroblock_memory64_a OF current_macroblock_memory64 IS

component wrapped_current_macroblock_memory64

        port (

        addr: IN std_logic_VECTOR(4 downto 0);

        clk: IN std_logic;

        din: IN std_logic_VECTOR(63 downto 0);

        dout: OUT std_logic_VECTOR(63 downto 0);

        we: IN std_logic);

end component;

-- Configuration specification 

        for all : wrapped_current_macroblock_memory64 use entity XilinxCoreLib.blkmemsp_v6_1(behavioral)

                generic map(

                        c_sinit_value => "0",

                        c_reg_inputs => 0,

                        c_yclk_is_rising => 1,

                        c_has_en => 0,

                        c_ysinit_is_high => 1,

                        c_ywe_is_high => 1,

                        c_ytop_addr => "1024",

                        c_yprimitive_type => "32kx1",

                        c_yhierarchy => "hierarchy1",

                        c_has_rdy => 0,

                        c_has_limit_data_pitch => 0,

                        c_write_mode => 0,

                        c_width => 64,

                        c_yuse_single_primitive => 0,

                        c_has_nd => 0,

                        c_enable_rlocs => 0,

                        c_has_we => 1,

                        c_has_rfd => 0,

                        c_has_din => 1,

                        c_ybottom_addr => "0",

                        c_pipe_stages => 0,

                        c_yen_is_high => 1,

                        c_depth => 32,

                        c_has_default_data => 0,

                        c_limit_data_pitch => 18,

                        c_has_sinit => 0,

                        c_mem_init_file => "current_macroblock_memory64.mif",

                        c_yydisable_warnings => 1,

                        c_default_data => "0",

                        c_ymake_bmm => 0,

                        c_addr_width => 5);

BEGIN

U0 : wrapped_current_macroblock_memory64

                port map (

                        addr => addr,

                        clk => clk,

                        din => din,

                        dout => dout,

                        we => we);

END current_macroblock_memory64_a;

-- synopsys translate_on