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eejlny |
----------------------------------------------------------------------------
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-- This file is a part of the LM VHDL IP LIBRARY
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-- Copyright (C) 2009 Jose Nunez-Yanez
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-- The license allows free and unlimited use of the library and tools for research and education purposes.
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-- The full LM core supports many more advanced motion estimation features and it is available under a
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-- low-cost commercial license. See the readme file to learn more or contact us at
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-- eejlny@byacom.co.uk or www.byacom.co.uk
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-----------------------------------------------------------------------------
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-- Entity: register_file
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-- File: register_file.vhd
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-- Author: Jose Luis Nunez
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-- Description: register file that holds the command and the first mv
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.Numeric_STD.all;
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use IEEE.std_logic_unsigned."-";
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use IEEE.std_logic_unsigned."+";
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use IEEE.std_logic_arith."abs";
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use work.config.all;
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entity distance_engine64 is
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generic( qp_mode : std_logic := '0');
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port(
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clk : in std_logic;
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clear : in std_logic;
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reset : in std_logic;
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enable : in std_logic;
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update : in std_logic;
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load_mv : in std_logic;
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mv_cost_on : in std_logic;
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mode_in : in mode_type;
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mv_cost_in : in std_logic_vector(15 downto 0);
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candidate_mvx : in std_logic_vector(7 downto 0);
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candidate_mvy : in std_logic_vector(7 downto 0);
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reference_data_in : in std_logic_vector(63 downto 0);
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residue_out : out std_logic_vector(63 downto 0);
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enable_fifo : out std_logic;
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reset_fifo : out std_logic;
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winner1 : out std_logic;
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calculate_sad_done : out std_logic;
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distance_engine_active : out std_logic;
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current_data_in : in std_logic_vector(63 downto 0);
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best_sad : out std_logic_vector(15 downto 0);
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best_mv : out std_logic_vector(15 downto 0));
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end;
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architecture behav of distance_engine64 is
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type state_type is (idle,calculate_sad,select_mv,wait_for_sad); -- dist engine control unit states
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type state_register_type is record
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enable_fifo : std_logic; -- enable the residue fifo
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winner1 : std_logic; -- winner flag controls residue store in block1 or 2
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state : state_type;
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current_sad : std_logic_vector(15 downto 0); -- stored partial and current sad
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-- current_mv : std_logic_vector(15 downto 0); -- stored the future motion vector to be evaluated
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current_mv2 : std_logic_vector(15 downto 0); -- stored the current motion vector being evaluated
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pipeline_cm : std_logic_vector(63 downto 0); -- pipeline for cm register directly from memory
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pipeline_rm : std_logic_vector(63 downto 0); -- pipeline for rm register directly from memory
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pipeline : std_logic_vector(63 downto 0); -- pipeline register
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end record;
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signal r, r_in: state_register_type; -- state register
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--signal sad_value_out, sad_value_in : std_logic_vector(15 downto 0);
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begin
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residue_out <= r.pipeline; -- write the residue to FIFOs
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r_in.enable_fifo <= '1' when r.state = calculate_sad else '0';
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r_in.pipeline_cm <= current_data_in;
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r_in.pipeline_rm <= reference_data_in;
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enable_fifo <= r.enable_fifo;
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--reset_fifo <= '1' when r.state = memory_read else '0'; -- empty the fifo before start writing to it
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tree_process : process(r)
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variable vpipeline : std_logic_vector(63 downto 0);
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variable vsad_value : std_logic_vector(15 downto 0);
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begin
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vpipeline := r.pipeline;
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vsad_value := r.current_sad;
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if (r.state = calculate_sad or r.state = wait_for_sad) then
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--if (r.state /= idle) then
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for i in 8 downto 1 loop
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vsad_value := vsad_value + (x"00" & vpipeline((8*i-1) downto (8*i-8)));
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end loop;
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elsif (qp_mode = '0') then
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vsad_value := (others => '0');
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elsif (r.state = idle) then
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vsad_value := (others => '0');
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end if;
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r_in.current_sad <= vsad_value;
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end process tree_process;
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sad_process : process(r)
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variable vpipeline : std_logic_vector(71 downto 0); -- 8 extra bits to accomodate signs
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--variable vpipeline2 : std_logic_vector(63 downto 0);
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begin
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if (r.state = idle) then
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vpipeline := (others => '0');
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elsif (r.state = select_mv and qp_mode = '1') then
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vpipeline := (others => '0');
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else
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for i in 8 downto 1 loop
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--vpipeline1((8*i-1) downto (8*i-8)) := signed(reference_data_in((8*i-1) downto (8*i-8)) - current_data_in((8*i-1) downto (8*i-8)));
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vpipeline((9*i-1) downto (9*i-9)) := std_logic_vector(ABS(signed(("0" & r.pipeline_rm((8*i-1) downto (8*i-8))) - ("0" & r.pipeline_cm((8*i-1) downto (8*i-8))))));
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--vpipeline((9*i-1) downto (9*i-9)) := std_logic_vector(ABS(signed(("0" & reference_data_in((8*i-1) downto (8*i-8))) - ("0" & current_data_in((8*i-1) downto (8*i-8))))));
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end loop;
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end if;
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for i in 8 downto 1 loop
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r_in.pipeline((8*i-1) downto (8*i-8)) <= vpipeline((9*i-2) downto (9*i-9));
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end loop;
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end process sad_process;
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sad_control : process(r,enable,load_mv,update,candidate_mvx,candidate_mvy,mode_in)
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variable vcalculate_sad_done,vdistance_engine_active : std_logic;
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variable v : state_register_type;
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begin
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vdistance_engine_active := '0';
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v.state := r.state;
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v.winner1 := r.winner1;
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vcalculate_sad_done := '0';
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-- v.current_mv := r.current_mv;
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v.current_mv2 := r.current_mv2;
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case v.state is
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when idle => -- first state, waiting for enable signal
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if (enable = '1') then
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v.state := calculate_sad;
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end if;
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when calculate_sad => -- read and evaluate sad
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vdistance_engine_active := '1';
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if (enable = '0') then -- wait for sad
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v.state := wait_for_sad;
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end if;
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when wait_for_sad =>
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vdistance_engine_active := '1';
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v.state := select_mv;
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when select_mv => -- select best mv
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vdistance_engine_active := '1';
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--v.current_mv := (others => '0'); -- clear in preparation for new calculation
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if (qp_mode = '0') then
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vcalculate_sad_done := '1';
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end if;
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if (enable = '0') then
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if (qp_mode = '1') then
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vcalculate_sad_done := '1';
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end if;
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v.state := idle;
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else
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--vcalculate_sad_done := '1';
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v.state := calculate_sad;
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end if;
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when others => null;
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end case;
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-- if (enable = '1') then
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-- v.current_mv2 := v.current_mv;
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-- end if;
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if (load_mv = '1') then
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-- v.current_mv2 := v.current_mv;
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v.current_mv2 := candidate_mvx & candidate_mvy;
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end if;
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r_in.state <= v.state;
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--r_in.current_mv <= v.current_mv;
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r_in.current_mv2 <= v.current_mv2;
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r_in.winner1 <= v.winner1;
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calculate_sad_done <= vcalculate_sad_done;
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distance_engine_active <= vdistance_engine_active;
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end process sad_control;
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best_sad <= (r.current_sad + mv_cost_in) when mv_cost_on = '1' else r.current_sad;
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best_mv <= r.current_mv2;
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winner1 <= r.winner1;
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regs : process(clk,clear)
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begin
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if (clear = '1') then
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r.enable_fifo <= '0';
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r.winner1 <= '0';
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r.state <= idle;
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r.current_sad <= (others => '0');
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r.pipeline <= (others => '0');
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r.pipeline_cm <= (others => '0');
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r.pipeline_rm <= (others => '0');
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--r.current_mv <= (others => '0');
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r.current_mv2 <= (others => '0');
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elsif rising_edge(clk) then
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if (reset = '1') then -- general enable
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r.enable_fifo <= '0';
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r.winner1 <= '0';
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r.state <= idle;
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r.current_sad <= (others => '0');
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r.pipeline <= (others => '0');
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r.pipeline_cm <= (others => '0');
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r.pipeline_rm <= (others => '0');
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--r.current_mv <= (others => '0');
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r.current_mv2 <= (others => '0');
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else
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r <= r_in;
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end if;
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end if;
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end process regs;
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end behav;
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