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eejlny |
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----------------------------------------------------------------------------
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-- This file is a part of the me testbench VHDL model
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-- Copyright (C) 2006 Jose Luis Nunez
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--
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-----------------------------------------------------------------------------
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-- Entity:
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-- File: macroblock_data.vhd
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-- Author: Jose Luis Nunez
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-- Description: macroblock data 5x5 macroblocks
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.Numeric_STD.all;
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entity macroblock_data1 is
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port(
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clk : in std_logic;
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reset : in std_logic;
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clear : in std_logic;
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addr : in std_logic_vector (4 downto 0);
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data : out std_logic_vector (63 downto 0)
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);
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end;
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architecture rtl of macroblock_data1 is
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signal data_int: std_logic_vector(63 downto 0);
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subtype word is integer range 0 to 255;
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type mem is array (0 to 255) of word;
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signal memory : mem := (
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16#3E#,16#48#,16#44#,16#48#,16#46#,16#41#,16#40#,16#40#,16#45#,16#4A#,16#4A#,16#46#,16#45#,16#3F#,16#47#,16#4D#,
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16#46#,16#45#,16#42#,16#3C#,16#42#,16#43#,16#43#,16#44#,16#41#,16#43#,16#41#,16#42#,16#45#,16#46#,16#4D#,16#47#,
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16#47#,16#3E#,16#45#,16#42#,16#42#,16#45#,16#40#,16#3C#,16#3C#,16#41#,16#41#,16#45#,16#42#,16#44#,16#47#,16#41#,
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16#46#,16#44#,16#43#,16#46#,16#42#,16#40#,16#3D#,16#39#,16#3D#,16#3C#,16#3B#,16#40#,16#41#,16#44#,16#42#,16#44#,
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16#43#,16#41#,16#3D#,16#3E#,16#3D#,16#3E#,16#41#,16#42#,16#44#,16#3F#,16#3D#,16#3D#,16#41#,16#44#,16#42#,16#42#,
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16#40#,16#3E#,16#40#,16#39#,16#39#,16#44#,16#4B#,16#4D#,16#4C#,16#4E#,16#4D#,16#44#,16#3F#,16#3D#,16#40#,16#41#,
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16#41#,16#45#,16#3F#,16#37#,16#3E#,16#4A#,16#3D#,16#2C#,16#2D#,16#35#,16#43#,16#4B#,16#44#,16#3B#,16#40#,16#45#,
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16#40#,16#3E#,16#39#,16#3E#,16#4A#,16#45#,16#2E#,16#25#,16#2C#,16#2E#,16#39#,16#4B#,16#4C#,16#40#,16#3C#,16#40#,
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16#43#,16#3D#,16#38#,16#41#,16#4C#,16#2B#,16#55#,16#AD#,16#A9#,16#81#,16#4A#,16#39#,16#4B#,16#48#,16#3B#,16#3B#,
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16#48#,16#48#,16#3F#,16#44#,16#40#,16#4A#,16#BD#,16#FF#,16#ED#,16#E0#,16#9A#,16#43#,16#41#,16#4B#,16#3C#,16#3F#,
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16#40#,16#40#,16#3B#,16#49#,16#36#,16#5E#,16#F7#,16#ED#,16#BB#,16#EB#,16#C8#,16#4D#,16#3B#,16#4E#,16#3A#,16#32#,
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16#38#,16#39#,16#39#,16#44#,16#3F#,16#37#,16#A5#,16#EF#,16#D9#,16#D3#,16#93#,16#3F#,16#42#,16#4E#,16#3C#,16#1A#,
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16#3C#,16#41#,16#45#,16#41#,16#47#,16#33#,16#28#,16#81#,16#AC#,16#7D#,16#4F#,16#46#,16#4E#,16#40#,16#45#,16#64#,
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16#47#,16#48#,16#49#,16#3F#,16#3E#,16#40#,16#1F#,16#22#,16#37#,16#30#,16#39#,16#49#,16#4C#,16#36#,16#49#,16#C0#,
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16#4D#,16#3C#,16#28#,16#34#,16#3A#,16#40#,16#44#,16#2B#,16#20#,16#32#,16#44#,16#44#,16#3F#,16#3D#,16#40#,16#64#,
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16#8#,16#2C#,16#7E#,16#61#,16#39#,16#43#,16#3C#,16#3D#,16#44#,16#3F#,16#39#,16#40#,16#3D#,16#42#,16#42#,16#13#
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);
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--attribute syn_romstyle : string;
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--attribute syn_romstyle of memory : signal is "logic";
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begin
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p : process(addr)
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variable vaddr1 : integer range 0 to 255;
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variable vaddr2 : integer range 0 to 255;
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variable vaddr3 : integer range 0 to 255;
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variable vaddr4 : integer range 0 to 255;
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variable vaddr5 : integer range 0 to 255;
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variable vaddr6 : integer range 0 to 255;
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variable vaddr7 : integer range 0 to 255;
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variable vaddr8 : integer range 0 to 255;
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begin
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vaddr1 := To_integer(unsigned(addr&"000"));
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vaddr2 := To_integer(unsigned(addr&"001"));
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vaddr3 := To_integer(unsigned(addr&"010"));
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vaddr4 := To_integer(unsigned(addr&"011"));
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vaddr5 := To_integer(unsigned(addr&"100"));
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vaddr6 := To_integer(unsigned(addr&"101"));
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vaddr7 := To_integer(unsigned(addr&"110"));
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vaddr8 := To_integer(unsigned(addr&"111"));
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data_int <= (std_logic_vector(to_unsigned(memory(vaddr1),8)) & std_logic_vector(to_unsigned(memory(vaddr2),8)) & std_logic_vector(to_unsigned(memory(vaddr3),8)) & std_logic_vector(to_unsigned(memory(vaddr4),8)) & std_logic_vector(to_unsigned(memory(vaddr5),8)) & std_logic_vector(to_unsigned(memory(vaddr6),8)) & std_logic_vector(to_unsigned(memory(vaddr7),8)) & std_logic_vector(to_unsigned(memory(vaddr8),8)));
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-- data_int(23 downto 16) <= std_logic_vector(to_unsigned(memory(vaddr2),8));
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-- data_int(15 downto 8) <= std_logic_vector(to_unsigned(memory(vaddr3),8));
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-- data_int(7 downto 0) <= std_logic_vector(to_unsigned(memory(vaddr4),8));
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end process;
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ff: process(clear,clk)
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begin
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if (clear = '1') then
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data <= (others => '0');
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elsif rising_edge(clk) then
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if (reset = '1') then
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data <= (others => '0');
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else
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data <= data_int;
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end if;
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end if;
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end process;
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end rtl;
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