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eejlny |
----------------------------------------------------------------------------
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-- This file is a part of the LM VHDL IP LIBRARY
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-- Copyright (C) 2009 Jose Nunez-Yanez
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-- The license allows free and unlimited use of the library and tools for research and education purposes.
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-- The full LM core supports many more advanced motion estimation features and it is available under a
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-- low-cost commercial license. See the readme file to learn more or contact us at
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-- eejlny@byacom.co.uk or www.byacom.co.uk
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-----------------------------------------------------------------------------
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-- Entity:
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-- File: macroblock_data.vhd
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-- Author: Jose Luis Nunez
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-- Description: macroblock data 5x5 macroblocks
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.Numeric_STD.all;
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entity macroblock_data2 is
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port(
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clk : in std_logic;
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reset : in std_logic;
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clear : in std_logic;
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addr : in std_logic_vector (4 downto 0);
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data : out std_logic_vector (63 downto 0)
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);
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end;
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architecture rtl of macroblock_data2 is
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signal data_int: std_logic_vector(63 downto 0);
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subtype word is integer range 0 to 255;
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type mem is array (0 to 255) of word;
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signal memory : mem := (
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16#48#,16#47#,16#4A#,16#49#,16#48#,16#46#,16#43#,16#49#,16#4E#,16#47#,16#44#,16#4A#,16#4F#,16#4C#,16#49#,16#4A#,
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16#40#,16#45#,16#49#,16#4A#,16#46#,16#46#,16#48#,16#49#,16#4A#,16#4A#,16#47#,16#4B#,16#4E#,16#4C#,16#43#,16#46#,
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16#47#,16#4D#,16#47#,16#43#,16#44#,16#47#,16#49#,16#4C#,16#4D#,16#4D#,16#45#,16#43#,16#4A#,16#4E#,16#47#,16#44#,
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16#4C#,16#46#,16#41#,16#42#,16#49#,16#4D#,16#4B#,16#49#,16#44#,16#43#,16#42#,16#42#,16#49#,16#4E#,16#4A#,16#41#,
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16#41#,16#41#,16#47#,16#4B#,16#49#,16#46#,16#44#,16#42#,16#40#,16#41#,16#46#,16#45#,16#46#,16#4B#,16#4B#,16#43#,
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16#43#,16#49#,16#48#,16#46#,16#43#,16#41#,16#40#,16#45#,16#4A#,16#4A#,16#4C#,16#47#,16#43#,16#49#,16#4D#,16#46#,
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16#45#,16#44#,16#3F#,16#3F#,16#42#,16#44#,16#46#,16#46#,16#46#,16#47#,16#4A#,16#47#,16#42#,16#46#,16#4B#,16#46#,
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16#40#,16#41#,16#41#,16#42#,16#41#,16#42#,16#43#,16#43#,16#42#,16#40#,16#41#,16#40#,16#3D#,16#44#,16#4B#,16#48#,
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16#3E#,16#42#,16#44#,16#44#,16#43#,16#43#,16#44#,16#43#,16#43#,16#41#,16#42#,16#44#,16#40#,16#44#,16#4A#,16#49#,
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16#36#,16#27#,16#28#,16#2A#,16#31#,16#3A#,16#3F#,16#45#,16#4C#,16#4D#,16#4D#,16#4F#,16#49#,16#45#,16#48#,16#4A#,
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16#57#,16#5E#,16#3E#,16#35#,16#31#,16#26#,16#1D#,16#1A#,16#18#,16#19#,16#19#,16#1A#,16#28#,16#44#,16#4D#,16#49#,
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16#42#,16#A1#,16#C1#,16#BB#,16#9E#,16#74#,16#5D#,16#50#,16#47#,16#46#,16#46#,16#43#,16#3E#,16#44#,16#4D#,16#4A#,
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16#44#,16#6B#,16#C8#,16#D8#,16#ED#,16#FF#,16#FE#,16#E9#,16#DB#,16#D8#,16#D7#,16#D5#,16#98#,16#44#,16#43#,16#4F#,
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16#B6#,16#53#,16#45#,16#49#,16#90#,16#EE#,16#FF#,16#FF#,16#F0#,16#EC#,16#EB#,16#F0#,16#AB#,16#41#,16#41#,16#4F#,
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16#C4#,16#D5#,16#99#,16#5B#,16#2B#,16#35#,16#62#,16#B6#,16#DE#,16#D8#,16#C4#,16#BF#,16#85#,16#3B#,16#46#,16#4D#,
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16#41#,16#8D#,16#BE#,16#F2#,16#B8#,16#62#,16#28#,16#37#,16#5E#,16#92#,16#D7#,16#E2#,16#77#,16#31#,16#4B#,16#4D#
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);
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--attribute syn_romstyle : string;
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--attribute syn_romstyle of memory : signal is "logic";
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begin
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p : process(addr)
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variable vaddr1 : integer range 0 to 255;
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variable vaddr2 : integer range 0 to 255;
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variable vaddr3 : integer range 0 to 255;
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variable vaddr4 : integer range 0 to 255;
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variable vaddr5 : integer range 0 to 255;
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variable vaddr6 : integer range 0 to 255;
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variable vaddr7 : integer range 0 to 255;
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variable vaddr8 : integer range 0 to 255;
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begin
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vaddr1 := To_integer(unsigned(addr&"000"));
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vaddr2 := To_integer(unsigned(addr&"001"));
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vaddr3 := To_integer(unsigned(addr&"010"));
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vaddr4 := To_integer(unsigned(addr&"011"));
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vaddr5 := To_integer(unsigned(addr&"100"));
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vaddr6 := To_integer(unsigned(addr&"101"));
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vaddr7 := To_integer(unsigned(addr&"110"));
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vaddr8 := To_integer(unsigned(addr&"111"));
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data_int <= (std_logic_vector(to_unsigned(memory(vaddr1),8)) & std_logic_vector(to_unsigned(memory(vaddr2),8)) & std_logic_vector(to_unsigned(memory(vaddr3),8)) & std_logic_vector(to_unsigned(memory(vaddr4),8)) & std_logic_vector(to_unsigned(memory(vaddr5),8)) & std_logic_vector(to_unsigned(memory(vaddr6),8)) & std_logic_vector(to_unsigned(memory(vaddr7),8)) & std_logic_vector(to_unsigned(memory(vaddr8),8)));
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-- data_int(23 downto 16) <= std_logic_vector(to_unsigned(memory(vaddr2),8));
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-- data_int(15 downto 8) <= std_logic_vector(to_unsigned(memory(vaddr3),8));
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-- data_int(7 downto 0) <= std_logic_vector(to_unsigned(memory(vaddr4),8));
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end process;
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ff: process(clear,clk)
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begin
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if (clear = '1') then
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data <= (others => '0');
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elsif rising_edge(clk) then
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if (reset = '1') then
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data <= (others => '0');
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else
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data <= data_int;
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end if;
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end if;
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end process;
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end rtl;
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