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eejlny |
----------------------------------------------------------------------------
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-- This file is a part of the LM VHDL IP LIBRARY
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-- Copyright (C) 2009 Jose Nunez-Yanez
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-- The license allows free and unlimited use of the library and tools for research and education purposes.
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-- The full LM core supports many more advanced motion estimation features and it is available under a
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-- low-cost commercial license. See the readme file to learn more or contact us at
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-- eejlny@byacom.co.uk or www.byacom.co.uk
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--------------------------------------
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-- entity = sad_selector --
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-- version = 1.0 --
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-- last update = 30/12/07 --
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-- author = Jose Nunez --
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--------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned."<";
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use IEEE.std_logic_unsigned."+";
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use IEEE.Numeric_STD.all;
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use work.config.all;
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entity sad_selector is
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generic (integer_pipeline_count : integer);
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port (
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clk : in std_logic;
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reset : in std_logic;
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clear : in std_logic;
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calculate_sad_done : in std_logic;
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active_pipelines : in std_logic_vector(CFG_PIPELINE_COUNT-1 downto 0);
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update : in std_logic; --end of program
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update_fp : in std_logic; -- end of iteraction
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best_eu : out std_logic_vector(3 downto 0);
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best_sad : in std_logic_vector(15 downto 0);
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best_mv : in std_logic_vector(15 downto 0);
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rest_best_sad : in rest_type_displacement;
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rest_best_mv : in rest_type_displacement;
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best_sad_out : out std_logic_vector(15 downto 0);
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best_mv_out : out std_logic_vector(15 downto 0));
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end sad_selector;
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architecture behavioral of sad_selector is
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type eu_id_type is array(CFG_PIPELINE_COUNT-1 downto 0) of std_logic_vector(3 downto 0); -- max number of integer eu is 15
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-- zero identifies when there is no winner
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type active_pipelines_type is array(5 downto 0) of std_logic_vector(CFG_PIPELINE_COUNT-1 downto 0);
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type state_register_type is record
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best_sad_candidate : std_logic_vector(15 downto 0); -- found sad for the best mv
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best_sad : std_logic_vector(15 downto 0); -- stored sad for the best mv
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best_mv : std_logic_vector(15 downto 0); -- mv associated to best sad
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best_eu : std_logic_vector(3 downto 0);
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eu_id : eu_id_type; -- keep track of the winning eu
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active_pipelines_r : active_pipelines_type; -- reproduce pipeline effects
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calculate_sad_done_int : std_logic; -- pipeline for performance
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end record;
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signal r, r_in: state_register_type; -- state register
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begin
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selection : process(best_sad,best_mv,rest_best_sad,rest_best_mv,update,calculate_sad_done,update_fp)
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variable vbest_sad_fp,vbest_mv_fp : std_logic_vector(15 downto 0);
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variable v : state_register_type; -- state register
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variable veu_id : std_logic_vector(3 downto 0); -- execution unit identifier
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begin
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vbest_sad_fp := best_sad;
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vbest_mv_fp := best_mv;
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veu_id := r.eu_id(0);
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v := r;
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for i in 1 to (integer_pipeline_count-1) loop
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if (v.active_pipelines_r(5)(i) = '1') then
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if rest_best_sad(i) < vbest_sad_fp then
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vbest_sad_fp := rest_best_sad(i);
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vbest_mv_fp := rest_best_mv(i);
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veu_id := r.eu_id(i);
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end if;
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end if;
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end loop;
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v.best_sad_candidate := vbest_sad_fp;
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v.active_pipelines_r(5) := v.active_pipelines_r(4);
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v.active_pipelines_r(4) := v.active_pipelines_r(3);
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v.active_pipelines_r(3) := v.active_pipelines_r(2);
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v.active_pipelines_r(2) := v.active_pipelines_r(1);
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v.active_pipelines_r(1) := v.active_pipelines_r(0);
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v.active_pipelines_r(0) := active_pipelines; -- pipeline effect
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if (r.best_sad_candidate < r.best_sad and v.calculate_sad_done_int = '1') then
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v.best_sad := r.best_sad_candidate;
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v.best_mv := vbest_mv_fp;
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v.best_eu := veu_id;
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best_sad_out <= r.best_sad_candidate;
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best_mv_out <= vbest_mv_fp;
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best_eu <= veu_id;
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else
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best_sad_out <= r.best_sad;
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best_mv_out <= r.best_mv;
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best_eu <= r.best_eu;
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end if;
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if (update = '1') then
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v.best_sad := x"FFFF"; --new program new max value
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elsif (update_fp = '1') then --iteraction completes
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for i in 0 to (CFG_PIPELINE_COUNT-1) loop
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v.eu_id(i) := std_logic_vector(to_unsigned((i+1),4));
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end loop;
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v.best_eu := (others => '0');
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elsif (v.calculate_sad_done_int = '1') then
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for i in 0 to (CFG_PIPELINE_COUNT-1) loop
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v.eu_id(i) := v.eu_id(i)+CFG_PIPELINE_COUNT;
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end loop;
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end if;
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v.calculate_sad_done_int := calculate_sad_done;
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r_in <= v;
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end process;
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regs : process(clk,clear)
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begin
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if (clear = '1') then
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r.best_sad <= x"FFFF"; -- start with the highest value
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r.best_sad_candidate <= (others => '0');
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r.best_mv <= (others => '0');
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r.best_eu <= (others => '0');
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for i in 0 to 5 loop
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r.active_pipelines_r(i) <= (others => '0');
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end loop;
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for i in 0 to (CFG_PIPELINE_COUNT-1) loop
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r.eu_id(i) <= std_logic_vector(to_unsigned((i+1),4));
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end loop;
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r.calculate_sad_done_int <= '0';
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elsif rising_edge(clk) then
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if (reset = '1') then -- general enable
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r.best_sad <= x"FFFF"; -- start with the highest value
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r.best_sad_candidate <= (others => '0');
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r.best_mv <= (others => '0');
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r.best_eu <= (others => '0');
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for i in 0 to 5 loop
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r.active_pipelines_r(i) <= (others => '0');
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end loop;
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for i in 0 to (CFG_PIPELINE_COUNT-1) loop
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r.eu_id(i) <= std_logic_vector(to_unsigned((i+1),4));
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end loop;
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r.calculate_sad_done_int <= '0';
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else
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r <= r_in;
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end if;
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end if;
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end process regs;
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end behavioral;
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