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Subversion Repositories motion_estimation_processor

[/] [motion_estimation_processor/] [trunk/] [syn/] [me_top.prj] - Blame information for rev 2

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1 2 eejlny
#-- Synplicity, Inc.
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#-- Version Synplify Pro 8.1
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#-- Project file D:\projects\me_interpolation_16m\open_source_core\syn\me_top.prj
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#-- Written on Wed Aug 26 12:22:58 2009
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#add_file options
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add_file -vhdl -lib work "../src_me/config.vhd"
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add_file -vhdl -lib work "../src_me/forward_engine.vhd"
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add_file -vhdl -lib work "../src_me/concatenate64.vhd"
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add_file -vhdl -lib work "../src_me/current_macroblock_memory64.vhd"
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add_file -vhdl -lib work "../src_me/distance_engine64.vhd"
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add_file -vhdl -lib work "../src_me/dual_port_component.vhd"
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add_file -vhdl -lib work "../src_me/range_checker.vhd"
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add_file -vhdl -lib work "../src_me/me_control_unit.vhd"
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add_file -vhdl -lib work "../src_me/me_engine.vhd"
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add_file -vhdl -lib work "../src_me/phy_address.vhd"
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add_file -vhdl -lib work "../src_me/point_memory.vhd"
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add_file -vhdl -lib work "../src_me/program_memory.vhd"
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add_file -vhdl -lib work "../src_me/sad_selector.vhd"
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add_file -vhdl -lib work "../src_me/reg_memory_dp.vhd"
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add_file -vhdl -lib work "../src_me/register_file.vhd"
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add_file -vhdl -lib work "../src_me/reference_memory64_remap.vhd"
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add_file -vhdl -lib work "../src_me/reference_macroblock_memory64.vhd"
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add_file -vhdl -lib work "../src_me/reference_memory64_dp_large.vhd"
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add_file -vhdl -lib work "../src_me/me_top.vhd"
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#implementation: "rev_1"
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impl -add rev_1
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#device options
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set_option -technology SPARTAN3
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set_option -part XC3S1500
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set_option -package FG320
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set_option -speed_grade -4
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#compilation/mapping options
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set_option -default_enum_encoding default
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set_option -symbolic_fsm_compiler 1
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set_option -resource_sharing 1
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set_option -use_fsm_explorer 0
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#map options
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set_option -frequency 200.000
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set_option -run_prop_extract 0
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set_option -fanout_limit 10000
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set_option -disable_io_insertion 1
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set_option -pipe 1
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set_option -fixgatedclocks 0
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set_option -retiming 0
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set_option -modular 0
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set_option -update_models_cp 0
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set_option -verification_mode 0
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set_option -no_sequential_opt 0
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#simulation options
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set_option -write_verilog 0
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set_option -write_vhdl 0
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#VIF options
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set_option -write_vif 1
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#set result format/file last
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project -result_file "rev_1/me_top.edf"
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#
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#implementation attributes
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set_option -vlog_std v2001
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set_option -project_relative_includes 1
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#par_1 attributes
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set_option -job par_1 -add par
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set_option -job par_1 -option run_backannotation 0
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impl -active "rev_1"

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