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https://opencores.org/ocsvn/mpdma/mpdma/trunk
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quickwayne |
HDL language for the peripheral (top level) design unit fifo_link is vhdl ...
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INFO:MDT - Create temparary xst project file: D:\mpdma\pcores\fifo_link.prj
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Compiling vhdl file
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"D:/thesis/mb-diesel/pcores/fifo_link_v1_00_a/hdl/vhdl/fifo_link.vhd" in Library
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fifo_link_v1_00_a.
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Entity compiled.
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Entity (Architecture ) compiled.
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Analyzing HDL attributes ...
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INFO:MDT - IPTYPE set to value : PERIPHERAL
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INFO:MDT - IMP_NETLIST set to value : TRUE
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INFO:MDT - HDL set to value : VHDL
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INFO:MDT - NO SIGIS=RST specified for probable Reset signal FSL_Rst
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INFO:MDT - NO SIGIS=RST specified for probable Reset signal FSL_Rst
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INFO:MDT - Infer bus clock [FSL_Clk] for bus interface MFSL ...
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INFO:MDT - Infer bus reset [FSL_Rst] for bus interface MFSL ...
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INFO:MDT - Infer bus clock [FSL_Clk] for bus interface SFSL ...
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INFO:MDT - Infer bus reset [FSL_Rst] for bus interface SFSL ...
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Copying file fifo_link.vhd to D:\mpdma\pcores\fifo_link_v1_00_a\hdl\vhdl\ ...
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Summary:
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Logical library : fifo_link_v1_00_a
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Version : 1.00.a
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Bus interface(s) : SFSL MFSL
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The following sub-directories will be created in the pcores repository in your
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project:
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- fifo_link_v1_00_a\data
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- fifo_link_v1_00_a\hdl
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- fifo_link_v1_00_a\hdl\vhdl
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The following HDL source files will be copied into the
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fifo_link_v1_00_a\hdl\vhdl directory:
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- fifo_link.vhd
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The following files will be created under the fifo_link_v1_00_a\data directory:
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- fifo_link_v2_1_0.mpd
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- fifo_link_v2_1_0.pao
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Thank you for using this Import Peripheral Wizard!
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