URL https://opencores.org/ocsvn/mpdma/mpdma/trunk

Subversion Repositories mpdma

[/] [mpdma/] [trunk/] [system.mhs] - Blame information for rev 28

Details | Compare with Previous | View Log


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
# Thu Oct 19 14:57:41 2006
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:        virtex2p
# Device:        xc2vp30
# Package:       ff896
# Speed Grade:   -7
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :  64 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
# ##############################################################################
 
 
 PARAMETER VERSION = 2.1.0
 
 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
 PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
 PORT sys_rst_pin = sys_rst_s, DIR = INPUT
 
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DLMB = dlmb0
 BUS_INTERFACE ILMB = ilmb0
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE MFSL0 = fsl0m
 BUS_INTERFACE SFSL0 = fsl0s
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_1
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DLMB = dlmb1
 BUS_INTERFACE ILMB = ilmb1
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE SFSL0 = fsl1s
 BUS_INTERFACE MFSL0 = fsl1m
END
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_2
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DLMB = dlmb2
 BUS_INTERFACE ILMB = ilmb2
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE SFSL0 = fsl2s
 BUS_INTERFACE MFSL0 = fsl2m
 PORT CLK = sys_clk_s
END
 
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_3
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 BUS_INTERFACE DLMB = dlmb3
 BUS_INTERFACE ILMB = ilmb3
 BUS_INTERFACE SFSL0 = fsl3s
 BUS_INTERFACE MFSL0 = fsl3m
END
 
BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END
 
BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl0m
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl0s
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1m
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl1s
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl2m
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl2s
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl3m
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN fsl_v20
 PARAMETER INSTANCE = fsl3s
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = dlmb0
 BUS_INTERFACE BRAM_PORT = dlmb_port0
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = ilmb0
 BUS_INTERFACE BRAM_PORT = ilmb_port0
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port0
 BUS_INTERFACE PORTB = dlmb_port0
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb1
 BUS_INTERFACE BRAM_PORT = dmb_port1
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb1
 BUS_INTERFACE BRAM_PORT = ilmb_port1
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram1
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port1
 BUS_INTERFACE PORTB = dmb_port1
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr2
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb2
 BUS_INTERFACE BRAM_PORT = dlmb_port2
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr2
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb2
 BUS_INTERFACE BRAM_PORT = ilmb_port2
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram2
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port2
 BUS_INTERFACE PORTB = dlmb_port2
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr3
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE BRAM_PORT = dlmb_port3
 BUS_INTERFACE SLMB = dlmb3
END
 
BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr3
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE BRAM_PORT = ilmb_port3
 BUS_INTERFACE SLMB = ilmb3
END
 
BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram3
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port3
 BUS_INTERFACE PORTB = dlmb_port3
END
 
BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END
 
BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END
 
BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CLK_PAIRS = 4
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 64
 PARAMETER C_MEM0_BASEADDR = 0x30000000
 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
 PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END
 
BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END
 
BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_PHASE_SHIFT = 60
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END
 
BEGIN fifo_link
 PARAMETER INSTANCE = fifo01
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl0m
 BUS_INTERFACE MFSL = fsl1s
END
 
BEGIN fifo_link
 PARAMETER INSTANCE = fifo12
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl1m
 BUS_INTERFACE MFSL = fsl2s
END
 
BEGIN fifo_link
 PARAMETER INSTANCE = fifo23
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl2m
 BUS_INTERFACE MFSL = fsl3s
END
 
BEGIN fifo_link
 PARAMETER INSTANCE = fifo30
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl3m
 BUS_INTERFACE MFSL = fsl0s
END
 

Line No.	Rev	Author	Line
1	6	quickwayne	`# ##############################################################################`
2			`# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1`
3			`# Thu Oct 19 14:57:41 2006`
4			`# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C`
5			`# Family: virtex2p`
6			`# Device: xc2vp30`
7			`# Package: ff896`
8			`# Speed Grade: -7`
9			`# Processor: Microblaze`
10			`# System clock frequency: 100.000000 MHz`
11			`# Debug interface: On-Chip HW Debug Module`
12			`# On Chip Memory : 64 KB`
13			`# Total Off Chip Memory : 256 MB`
14	11	quickwayne	`# - DDR_SDRAM_32Mx64 Single Rank = 256 MB`
15	6	quickwayne	`# ##############################################################################`
16
17
18			`PARAMETER VERSION = 2.1.0`
19
20
21			`PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = INPUT`
22			`PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = OUTPUT`
23			`PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = INPUT`
24	11	quickwayne	`PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, VEC = [6:0], DIR = OUTPUT`
25			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, VEC = [15:0], DIR = INOUT`
26	6	quickwayne	`PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = OUTPUT`
27			`PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = OUTPUT`
28			`PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = OUTPUT`
29			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = INPUT`
30	11	quickwayne	`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, VEC = [0:2], DIR = OUTPUT`
31			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, VEC = [0:2], DIR = OUTPUT`
32			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, VEC = [0:12], DIR = OUTPUT`
33			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT`
34	6	quickwayne	`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = OUTPUT`
35			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = OUTPUT`
36			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = OUTPUT`
37	11	quickwayne	`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, VEC = [0:7], DIR = OUTPUT`
38			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, VEC = [0:7], DIR = INOUT`
39			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, VEC = [0:63], DIR = INOUT`
40	6	quickwayne	`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = OUTPUT`
41			`PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = OUTPUT`
42			`PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT`
43			`PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT`
44			`PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK`
45			`PORT sys_rst_pin = sys_rst_s, DIR = INPUT`
46
47
48			`BEGIN microblaze`
49			`PARAMETER INSTANCE = microblaze_0`
50			`PARAMETER HW_VER = 4.00.a`
51			`PARAMETER C_DEBUG_ENABLED = 1`
52			`PARAMETER C_NUMBER_OF_PC_BRK = 2`
53			`PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1`
54			`PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1`
55	11	quickwayne	`PARAMETER C_FSL_LINKS = 1`
56			`BUS_INTERFACE DLMB = dlmb0`
57			`BUS_INTERFACE ILMB = ilmb0`
58	6	quickwayne	`BUS_INTERFACE DOPB = mb_opb`
59			`BUS_INTERFACE IOPB = mb_opb`
60	11	quickwayne	`BUS_INTERFACE MFSL0 = fsl0m`
61			`BUS_INTERFACE SFSL0 = fsl0s`
62	6	quickwayne	`PORT CLK = sys_clk_s`
63			`PORT DBG_CAPTURE = DBG_CAPTURE_s`
64			`PORT DBG_CLK = DBG_CLK_s`
65			`PORT DBG_REG_EN = DBG_REG_EN_s`
66			`PORT DBG_TDI = DBG_TDI_s`
67			`PORT DBG_TDO = DBG_TDO_s`
68			`PORT DBG_UPDATE = DBG_UPDATE_s`
69			`END`
70
71	11	quickwayne	`BEGIN microblaze`
72	22	quickwayne	`PARAMETER INSTANCE = microblaze_1`
73			`PARAMETER HW_VER = 4.00.a`
74			`PARAMETER C_DEBUG_ENABLED = 1`
75			`PARAMETER C_NUMBER_OF_PC_BRK = 2`
76			`PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1`
77			`PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1`
78			`PARAMETER C_FSL_LINKS = 1`
79			`BUS_INTERFACE DLMB = dlmb1`
80			`BUS_INTERFACE ILMB = ilmb1`
81			`BUS_INTERFACE DOPB = mb_opb`
82			`BUS_INTERFACE IOPB = mb_opb`
83			`BUS_INTERFACE SFSL0 = fsl1s`
84			`BUS_INTERFACE MFSL0 = fsl1m`
85			`END`
86
87			`BEGIN microblaze`
88	11	quickwayne	`PARAMETER INSTANCE = microblaze_2`
89			`PARAMETER HW_VER = 4.00.a`
90			`PARAMETER C_DEBUG_ENABLED = 1`
91			`PARAMETER C_NUMBER_OF_PC_BRK = 2`
92			`PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1`
93			`PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1`
94			`PARAMETER C_FSL_LINKS = 1`
95			`BUS_INTERFACE DLMB = dlmb2`
96			`BUS_INTERFACE ILMB = ilmb2`
97			`BUS_INTERFACE DOPB = mb_opb`
98			`BUS_INTERFACE IOPB = mb_opb`
99			`BUS_INTERFACE SFSL0 = fsl2s`
100			`BUS_INTERFACE MFSL0 = fsl2m`
101			`PORT CLK = sys_clk_s`
102			`END`
103
104	16	quickwayne	`BEGIN microblaze`
105			`PARAMETER INSTANCE = microblaze_3`
106			`PARAMETER HW_VER = 4.00.a`
107			`PARAMETER C_FSL_LINKS = 1`
108			`BUS_INTERFACE DOPB = mb_opb`
109			`BUS_INTERFACE IOPB = mb_opb`
110			`BUS_INTERFACE DLMB = dlmb3`
111			`BUS_INTERFACE ILMB = ilmb3`
112			`BUS_INTERFACE SFSL0 = fsl3s`
113			`BUS_INTERFACE MFSL0 = fsl3m`
114			`END`
115
116	6	quickwayne	`BEGIN opb_v20`
117			`PARAMETER INSTANCE = mb_opb`
118			`PARAMETER HW_VER = 1.10.c`
119			`PARAMETER C_EXT_RESET_HIGH = 0`
120			`PORT SYS_Rst = sys_rst_s`
121			`PORT OPB_Clk = sys_clk_s`
122			`END`
123
124			`BEGIN opb_mdm`
125			`PARAMETER INSTANCE = debug_module`
126			`PARAMETER HW_VER = 2.00.a`
127			`PARAMETER C_MB_DBG_PORTS = 1`
128			`PARAMETER C_USE_UART = 1`
129			`PARAMETER C_UART_WIDTH = 8`
130			`PARAMETER C_BASEADDR = 0x41400000`
131			`PARAMETER C_HIGHADDR = 0x4140ffff`
132			`BUS_INTERFACE SOPB = mb_opb`
133			`PORT OPB_Clk = sys_clk_s`
134			`PORT DBG_CAPTURE_0 = DBG_CAPTURE_s`
135			`PORT DBG_CLK_0 = DBG_CLK_s`
136			`PORT DBG_REG_EN_0 = DBG_REG_EN_s`
137			`PORT DBG_TDI_0 = DBG_TDI_s`
138			`PORT DBG_TDO_0 = DBG_TDO_s`
139			`PORT DBG_UPDATE_0 = DBG_UPDATE_s`
140			`END`
141
142			`BEGIN lmb_v10`
143	11	quickwayne	`PARAMETER INSTANCE = ilmb0`
144	6	quickwayne	`PARAMETER HW_VER = 1.00.a`
145			`PARAMETER C_EXT_RESET_HIGH = 0`
146			`PORT SYS_Rst = sys_rst_s`
147			`PORT LMB_Clk = sys_clk_s`
148			`END`
149
150			`BEGIN lmb_v10`
151	11	quickwayne	`PARAMETER INSTANCE = dlmb0`
152	6	quickwayne	`PARAMETER HW_VER = 1.00.a`
153			`PARAMETER C_EXT_RESET_HIGH = 0`
154			`PORT SYS_Rst = sys_rst_s`
155			`PORT LMB_Clk = sys_clk_s`
156			`END`
157
158	11	quickwayne	`BEGIN lmb_v10`
159	22	quickwayne	`PARAMETER INSTANCE = ilmb1`
160			`PARAMETER HW_VER = 1.00.a`
161			`PARAMETER C_EXT_RESET_HIGH = 0`
162			`PORT SYS_Rst = sys_rst_s`
163			`PORT LMB_Clk = sys_clk_s`
164			`END`
165
166			`BEGIN lmb_v10`
167			`PARAMETER INSTANCE = dlmb1`
168			`PARAMETER HW_VER = 1.00.a`
169			`PARAMETER C_EXT_RESET_HIGH = 0`
170			`PORT SYS_Rst = sys_rst_s`
171			`PORT LMB_Clk = sys_clk_s`
172			`END`
173
174			`BEGIN lmb_v10`
175	11	quickwayne	`PARAMETER INSTANCE = ilmb2`
176			`PARAMETER HW_VER = 1.00.a`
177			`PARAMETER C_EXT_RESET_HIGH = 0`
178			`PORT SYS_Rst = sys_rst_s`
179			`PORT LMB_Clk = sys_clk_s`
180			`END`
181
182			`BEGIN lmb_v10`
183			`PARAMETER INSTANCE = dlmb2`
184			`PARAMETER HW_VER = 1.00.a`
185			`PARAMETER C_EXT_RESET_HIGH = 0`
186			`PORT SYS_Rst = sys_rst_s`
187			`PORT LMB_Clk = sys_clk_s`
188			`END`
189
190	16	quickwayne	`BEGIN lmb_v10`
191			`PARAMETER INSTANCE = ilmb3`
192			`PARAMETER HW_VER = 1.00.a`
193			`PARAMETER C_EXT_RESET_HIGH = 0`
194			`PORT SYS_Rst = sys_rst_s`
195			`PORT LMB_Clk = sys_clk_s`
196			`END`
197
198			`BEGIN lmb_v10`
199			`PARAMETER INSTANCE = dlmb3`
200			`PARAMETER HW_VER = 1.00.a`
201			`PARAMETER C_EXT_RESET_HIGH = 0`
202			`PORT SYS_Rst = sys_rst_s`
203			`PORT LMB_Clk = sys_clk_s`
204			`END`
205
206	11	quickwayne	`BEGIN fsl_v20`
207			`PARAMETER INSTANCE = fsl0m`
208			`PARAMETER HW_VER = 2.00.a`
209			`PARAMETER C_EXT_RESET_HIGH = 0`
210			`PARAMETER C_FSL_DEPTH = 128`
211			`PORT FSL_Clk = sys_clk_s`
212			`PORT SYS_Rst = sys_rst_s`
213			`END`
214
215			`BEGIN fsl_v20`
216			`PARAMETER INSTANCE = fsl0s`
217			`PARAMETER HW_VER = 2.00.a`
218			`PARAMETER C_EXT_RESET_HIGH = 0`
219			`PARAMETER C_FSL_DEPTH = 128`
220			`PORT FSL_Clk = sys_clk_s`
221			`PORT SYS_Rst = sys_rst_s`
222			`END`
223
224			`BEGIN fsl_v20`
225	22	quickwayne	`PARAMETER INSTANCE = fsl1m`
226			`PARAMETER HW_VER = 2.00.a`
227			`PARAMETER C_EXT_RESET_HIGH = 0`
228			`PARAMETER C_FSL_DEPTH = 128`
229			`PORT FSL_Clk = sys_clk_s`
230			`PORT SYS_Rst = sys_rst_s`
231			`END`
232
233			`BEGIN fsl_v20`
234			`PARAMETER INSTANCE = fsl1s`
235			`PARAMETER HW_VER = 2.00.a`
236			`PARAMETER C_EXT_RESET_HIGH = 0`
237			`PARAMETER C_FSL_DEPTH = 128`
238			`PORT FSL_Clk = sys_clk_s`
239			`PORT SYS_Rst = sys_rst_s`
240			`END`
241
242			`BEGIN fsl_v20`
243	11	quickwayne	`PARAMETER INSTANCE = fsl2m`
244			`PARAMETER HW_VER = 2.00.a`
245			`PARAMETER C_EXT_RESET_HIGH = 0`
246			`PARAMETER C_FSL_DEPTH = 128`
247			`PORT FSL_Clk = sys_clk_s`
248			`PORT SYS_Rst = sys_rst_s`
249			`END`
250
251			`BEGIN fsl_v20`
252			`PARAMETER INSTANCE = fsl2s`
253			`PARAMETER HW_VER = 2.00.a`
254			`PARAMETER C_EXT_RESET_HIGH = 0`
255			`PARAMETER C_FSL_DEPTH = 128`
256			`PORT FSL_Clk = sys_clk_s`
257			`PORT SYS_Rst = sys_rst_s`
258			`END`
259
260	16	quickwayne	`BEGIN fsl_v20`
261			`PARAMETER INSTANCE = fsl3m`
262			`PARAMETER HW_VER = 2.00.a`
263			`PARAMETER C_EXT_RESET_HIGH = 0`
264			`PARAMETER C_FSL_DEPTH = 128`
265			`PORT FSL_Clk = sys_clk_s`
266			`PORT SYS_Rst = sys_rst_s`
267			`END`
268
269			`BEGIN fsl_v20`
270			`PARAMETER INSTANCE = fsl3s`
271			`PARAMETER HW_VER = 2.00.a`
272			`PARAMETER C_EXT_RESET_HIGH = 0`
273			`PARAMETER C_FSL_DEPTH = 128`
274			`PORT FSL_Clk = sys_clk_s`
275			`PORT SYS_Rst = sys_rst_s`
276			`END`
277
278	6	quickwayne	`BEGIN lmb_bram_if_cntlr`
279	11	quickwayne	`PARAMETER INSTANCE = dlmb_cntlr0`
280	6	quickwayne	`PARAMETER HW_VER = 1.00.b`
281			`PARAMETER C_BASEADDR = 0x00000000`
282			`PARAMETER C_HIGHADDR = 0x0000ffff`
283	11	quickwayne	`BUS_INTERFACE SLMB = dlmb0`
284			`BUS_INTERFACE BRAM_PORT = dlmb_port0`
285	6	quickwayne	`END`
286
287			`BEGIN lmb_bram_if_cntlr`
288	11	quickwayne	`PARAMETER INSTANCE = ilmb_cntlr0`
289	6	quickwayne	`PARAMETER HW_VER = 1.00.b`
290			`PARAMETER C_BASEADDR = 0x00000000`
291			`PARAMETER C_HIGHADDR = 0x0000ffff`
292	11	quickwayne	`BUS_INTERFACE SLMB = ilmb0`
293			`BUS_INTERFACE BRAM_PORT = ilmb_port0`
294	6	quickwayne	`END`
295
296			`BEGIN bram_block`
297	11	quickwayne	`PARAMETER INSTANCE = lmb_bram0`
298	6	quickwayne	`PARAMETER HW_VER = 1.00.a`
299	11	quickwayne	`BUS_INTERFACE PORTA = ilmb_port0`
300			`BUS_INTERFACE PORTB = dlmb_port0`
301	6	quickwayne	`END`
302
303	11	quickwayne	`BEGIN lmb_bram_if_cntlr`
304	22	quickwayne	`PARAMETER INSTANCE = dlmb_cntlr1`
305			`PARAMETER HW_VER = 1.00.b`
306			`PARAMETER C_BASEADDR = 0x00000000`
307			`PARAMETER C_HIGHADDR = 0x00001fff`
308			`BUS_INTERFACE SLMB = dlmb1`
309			`BUS_INTERFACE BRAM_PORT = dmb_port1`
310			`END`
311
312			`BEGIN lmb_bram_if_cntlr`
313			`PARAMETER INSTANCE = ilmb_cntlr1`
314			`PARAMETER HW_VER = 1.00.b`
315			`PARAMETER C_BASEADDR = 0x00000000`
316			`PARAMETER C_HIGHADDR = 0x00001fff`
317			`BUS_INTERFACE SLMB = ilmb1`
318			`BUS_INTERFACE BRAM_PORT = ilmb_port1`
319			`END`
320
321			`BEGIN bram_block`
322			`PARAMETER INSTANCE = lmb_bram1`
323			`PARAMETER HW_VER = 1.00.a`
324			`BUS_INTERFACE PORTA = ilmb_port1`
325			`BUS_INTERFACE PORTB = dmb_port1`
326			`END`
327
328			`BEGIN lmb_bram_if_cntlr`
329	11	quickwayne	`PARAMETER INSTANCE = dlmb_cntlr2`
330			`PARAMETER HW_VER = 1.00.b`
331			`PARAMETER C_BASEADDR = 0x00000000`
332			`PARAMETER C_HIGHADDR = 0x00001fff`
333			`BUS_INTERFACE SLMB = dlmb2`
334			`BUS_INTERFACE BRAM_PORT = dlmb_port2`
335			`END`
336
337			`BEGIN lmb_bram_if_cntlr`
338			`PARAMETER INSTANCE = ilmb_cntlr2`
339			`PARAMETER HW_VER = 1.00.b`
340			`PARAMETER C_BASEADDR = 0x00000000`
341			`PARAMETER C_HIGHADDR = 0x00001fff`
342			`BUS_INTERFACE SLMB = ilmb2`
343			`BUS_INTERFACE BRAM_PORT = ilmb_port2`
344			`END`
345
346			`BEGIN bram_block`
347			`PARAMETER INSTANCE = lmb_bram2`
348			`PARAMETER HW_VER = 1.00.a`
349			`BUS_INTERFACE PORTA = ilmb_port2`
350			`BUS_INTERFACE PORTB = dlmb_port2`
351			`END`
352
353	16	quickwayne	`BEGIN lmb_bram_if_cntlr`
354			`PARAMETER INSTANCE = dlmb_cntlr3`
355			`PARAMETER HW_VER = 1.00.b`
356			`PARAMETER C_BASEADDR = 0x00000000`
357			`PARAMETER C_HIGHADDR = 0x00001fff`
358			`BUS_INTERFACE BRAM_PORT = dlmb_port3`
359			`BUS_INTERFACE SLMB = dlmb3`
360			`END`
361
362			`BEGIN lmb_bram_if_cntlr`
363			`PARAMETER INSTANCE = ilmb_cntlr3`
364			`PARAMETER HW_VER = 1.00.b`
365			`PARAMETER C_BASEADDR = 0x00000000`
366			`PARAMETER C_HIGHADDR = 0x00001fff`
367			`BUS_INTERFACE BRAM_PORT = ilmb_port3`
368			`BUS_INTERFACE SLMB = ilmb3`
369			`END`
370
371			`BEGIN bram_block`
372			`PARAMETER INSTANCE = lmb_bram3`
373			`PARAMETER HW_VER = 1.00.a`
374			`BUS_INTERFACE PORTA = ilmb_port3`
375			`BUS_INTERFACE PORTB = dlmb_port3`
376			`END`
377
378	6	quickwayne	`BEGIN opb_uartlite`
379			`PARAMETER INSTANCE = RS232_Uart_1`
380			`PARAMETER HW_VER = 1.00.b`
381			`PARAMETER C_BAUDRATE = 9600`
382			`PARAMETER C_DATA_BITS = 8`
383			`PARAMETER C_ODD_PARITY = 0`
384			`PARAMETER C_USE_PARITY = 0`
385			`PARAMETER C_CLK_FREQ = 100000000`
386			`PARAMETER C_BASEADDR = 0x40600000`
387			`PARAMETER C_HIGHADDR = 0x4060ffff`
388			`BUS_INTERFACE SOPB = mb_opb`
389			`PORT OPB_Clk = sys_clk_s`
390			`PORT RX = fpga_0_RS232_Uart_1_RX`
391			`PORT TX = fpga_0_RS232_Uart_1_TX`
392			`END`
393
394			`BEGIN opb_sysace`
395			`PARAMETER INSTANCE = SysACE_CompactFlash`
396			`PARAMETER HW_VER = 1.00.c`
397			`PARAMETER C_MEM_WIDTH = 16`
398			`PARAMETER C_BASEADDR = 0x41800000`
399			`PARAMETER C_HIGHADDR = 0x4180ffff`
400			`BUS_INTERFACE SOPB = mb_opb`
401			`PORT OPB_Clk = sys_clk_s`
402			`PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK`
403			`PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA`
404			`PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD`
405			`PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN`
406			`PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN`
407			`PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN`
408			`PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ`
409			`END`
410
411			`BEGIN opb_ddr`
412			`PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5`
413			`PARAMETER HW_VER = 2.00.b`
414			`PARAMETER C_OPB_CLK_PERIOD_PS = 10000`
415			`PARAMETER C_NUM_BANKS_MEM = 1`
416			`PARAMETER C_NUM_CLK_PAIRS = 4`
417			`PARAMETER C_REG_DIMM = 0`
418			`PARAMETER C_DDR_TMRD = 20000`
419			`PARAMETER C_DDR_TWR = 20000`
420			`PARAMETER C_DDR_TRAS = 60000`
421			`PARAMETER C_DDR_TRC = 90000`
422			`PARAMETER C_DDR_TRFC = 100000`
423			`PARAMETER C_DDR_TRCD = 30000`
424			`PARAMETER C_DDR_TRRD = 20000`
425			`PARAMETER C_DDR_TRP = 30000`
426			`PARAMETER C_DDR_TREFC = 70300000`
427			`PARAMETER C_DDR_AWIDTH = 13`
428			`PARAMETER C_DDR_COL_AWIDTH = 10`
429			`PARAMETER C_DDR_BANK_AWIDTH = 2`
430			`PARAMETER C_DDR_DWIDTH = 64`
431			`PARAMETER C_MEM0_BASEADDR = 0x30000000`
432			`PARAMETER C_MEM0_HIGHADDR = 0x3fffffff`
433			`BUS_INTERFACE SOPB = mb_opb`
434			`PORT OPB_Clk = sys_clk_s`
435			`PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr`
436			`PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr`
437			`PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn`
438			`PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE`
439			`PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn`
440			`PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn`
441			`PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn`
442			`PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM`
443			`PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS`
444			`PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ`
445			`PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s`
446			`PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0`
447			`PORT Device_Clk90_in = clk_90_s`
448			`PORT Device_Clk90_in_n = clk_90_n_s`
449			`PORT Device_Clk = sys_clk_s`
450			`PORT Device_Clk_n = sys_clk_n_s`
451			`PORT DDR_Clk90_in = ddr_clk_90_s`
452			`PORT DDR_Clk90_in_n = ddr_clk_90_n_s`
453			`END`
454
455			`BEGIN util_vector_logic`
456			`PARAMETER INSTANCE = sysclk_inv`
457			`PARAMETER HW_VER = 1.00.a`
458			`PARAMETER C_SIZE = 1`
459			`PARAMETER C_OPERATION = not`
460			`PORT Op1 = sys_clk_s`
461			`PORT Res = sys_clk_n_s`
462			`END`
463
464			`BEGIN util_vector_logic`
465			`PARAMETER INSTANCE = clk90_inv`
466			`PARAMETER HW_VER = 1.00.a`
467			`PARAMETER C_SIZE = 1`
468			`PARAMETER C_OPERATION = not`
469			`PORT Op1 = clk_90_s`
470			`PORT Res = clk_90_n_s`
471			`END`
472
473			`BEGIN util_vector_logic`
474			`PARAMETER INSTANCE = ddr_clk90_inv`
475			`PARAMETER HW_VER = 1.00.a`
476			`PARAMETER C_SIZE = 1`
477			`PARAMETER C_OPERATION = not`
478			`PORT Op1 = ddr_clk_90_s`
479			`PORT Res = ddr_clk_90_n_s`
480			`END`
481
482			`BEGIN dcm_module`
483			`PARAMETER INSTANCE = dcm_0`
484			`PARAMETER HW_VER = 1.00.a`
485			`PARAMETER C_CLK0_BUF = TRUE`
486			`PARAMETER C_CLK90_BUF = TRUE`
487			`PARAMETER C_CLKIN_PERIOD = 10.000000`
488			`PARAMETER C_CLK_FEEDBACK = 1X`
489			`PARAMETER C_EXT_RESET_HIGH = 1`
490			`PORT CLKIN = dcm_clk_s`
491			`PORT CLK0 = sys_clk_s`
492			`PORT CLK90 = clk_90_s`
493			`PORT CLKFB = sys_clk_s`
494			`PORT RST = net_gnd`
495			`PORT LOCKED = dcm_0_lock`
496			`END`
497
498			`BEGIN dcm_module`
499			`PARAMETER INSTANCE = dcm_1`
500			`PARAMETER HW_VER = 1.00.a`

Browse

Tools

Subversion Repositories mpdma

[/] [mpdma/] [trunk/] [system.mhs] - Blame information for rev 28