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kdv |
/*
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* framestore_response.v
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*
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* Copyright (c) 2007 Koen De Vleeschauwer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Frame Store Response. Read response from memory controller.
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*
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* Receives data read from the memory controller;
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* passes data read on to motion compensation or display.
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*/
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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`undef CHECK
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//`define CHECK 1
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`ifdef __IVERILOG__
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`define CHECK 1
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`endif
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//`define SIMULATION_ONLY
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`ifdef __IVERILOG__
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`define SIMULATION_ONLY 1
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`endif
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module framestore_response(rst, clk,
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fwd_wr_dta_full, fwd_wr_dta_en, fwd_wr_dta_ack, fwd_wr_dta, fwd_wr_dta_almost_full,
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bwd_wr_dta_full, bwd_wr_dta_en, bwd_wr_dta_ack, bwd_wr_dta, bwd_wr_dta_almost_full,
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disp_wr_dta_full, disp_wr_dta_en, disp_wr_dta_ack, disp_wr_dta, disp_wr_dta_almost_full,
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vbr_wr_full, vbr_wr_en, vbr_wr_ack, vbr_wr_dta, vbr_wr_almost_full,
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mem_res_rd_dta, mem_res_rd_en, mem_res_rd_empty, mem_res_rd_valid,
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tag_rd_dta, tag_rd_empty, tag_rd_en, tag_rd_valid
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);
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input rst;
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input clk;
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/* motion compensation: reading forward reference frame */
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input fwd_wr_dta_full;
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input fwd_wr_dta_almost_full;
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output reg fwd_wr_dta_en;
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input fwd_wr_dta_ack;
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output reg [63:0]fwd_wr_dta;
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/* motion compensation: reading backward reference frame */
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input bwd_wr_dta_full;
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input bwd_wr_dta_almost_full;
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output reg bwd_wr_dta_en;
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input bwd_wr_dta_ack;
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output reg [63:0]bwd_wr_dta;
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/* display: reading reconstructed frame */
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input disp_wr_dta_full;
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input disp_wr_dta_almost_full;
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output reg disp_wr_dta_en;
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input disp_wr_dta_ack;
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output reg [63:0]disp_wr_dta;
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/* video buffer: reading from circular buffer */
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input vbr_wr_full;
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input vbr_wr_almost_full;
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output reg vbr_wr_en;
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input vbr_wr_ack;
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output reg [63:0]vbr_wr_dta;
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/* memory response fifo */
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input [63:0]mem_res_rd_dta;
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output reg mem_res_rd_en;
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input mem_res_rd_empty;
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input mem_res_rd_valid;
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/* tag fifo */
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input [2:0]tag_rd_dta;
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input tag_rd_empty;
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output reg tag_rd_en;
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input tag_rd_valid;
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`include "mem_codes.v"
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parameter [2:0]
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STATE_INIT = 4'h0,
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STATE_FLUSH = 4'h1,
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STATE_WAIT = 4'h2,
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STATE_READ = 4'h3,
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STATE_WRITE = 4'h4;
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reg [2:0]state;
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reg [2:0]next;
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reg [15:0]flush_counter;
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always @(posedge clk)
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if (~rst) flush_counter <= 0;
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else if (state == STATE_FLUSH) flush_counter <= flush_counter + 16'd1;
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else flush_counter <= flush_counter;
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wire fifos_not_ready = fwd_wr_dta_full || bwd_wr_dta_full || disp_wr_dta_full || vbr_wr_full || tag_rd_empty || mem_res_rd_empty;
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wire fifos_ready = ~fifos_not_ready;
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/* next state logic */
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always @*
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case (state)
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`ifdef SIMULATION_ONLY
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STATE_INIT: next = STATE_WAIT;
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`else
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STATE_INIT: next = STATE_FLUSH;
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`endif
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STATE_FLUSH: if (flush_counter == 16'hffff) next = STATE_WAIT; // Flush any data in the memory response fifo's.
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else next = STATE_FLUSH;
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STATE_WAIT: if (fifos_not_ready) next = STATE_WAIT; // wait until all fifos available
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else next = STATE_READ;
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STATE_READ: next = STATE_WRITE;
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STATE_WRITE: next = STATE_WAIT;
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default next = STATE_WAIT;
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endcase
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/* state */
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always @(posedge clk)
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if(~rst) state <= STATE_INIT;
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else state <= next;
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/*
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* read from memory response and tag fifos
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*/
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always @(posedge clk)
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if (~rst) mem_res_rd_en <= 1'b0;
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else if (state == STATE_FLUSH) mem_res_rd_en <= 1'b1;
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else if (state == STATE_READ) mem_res_rd_en <= fifos_ready;
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else mem_res_rd_en <= 1'b0;
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always @(posedge clk)
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if (~rst) tag_rd_en <= 1'b0;
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else if (state == STATE_READ) tag_rd_en <= fifos_ready;
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else tag_rd_en <= 1'b0;
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/*
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* second stage: if successful read from memory response fifo, write memory response data to fifo corresponding to tag (fwd, bwd, disp or vbr).
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*/
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always @(posedge clk)
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if (~rst) fwd_wr_dta_en <= 1'b0;
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else fwd_wr_dta_en <= (tag_rd_dta == TAG_FWD) && tag_rd_valid;
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always @(posedge clk)
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if (~rst) fwd_wr_dta <= 64'b0;
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else if (mem_res_rd_valid) fwd_wr_dta <= mem_res_rd_dta;
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else fwd_wr_dta <= fwd_wr_dta;
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always @(posedge clk)
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if (~rst) bwd_wr_dta_en <= 1'b0;
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else bwd_wr_dta_en <= (tag_rd_dta == TAG_BWD) && tag_rd_valid;
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always @(posedge clk)
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if (~rst) bwd_wr_dta <= 64'b0;
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else if (mem_res_rd_valid) bwd_wr_dta <= mem_res_rd_dta;
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else bwd_wr_dta <= bwd_wr_dta;
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always @(posedge clk)
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if (~rst) disp_wr_dta_en <= 1'b0;
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else disp_wr_dta_en <= (tag_rd_dta == TAG_DISP) && tag_rd_valid;
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always @(posedge clk)
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if (~rst) disp_wr_dta <= 64'b0;
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else if (mem_res_rd_valid) disp_wr_dta <= mem_res_rd_dta;
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else disp_wr_dta <= disp_wr_dta;
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always @(posedge clk)
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if (~rst) vbr_wr_en <= 1'b0;
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else vbr_wr_en <= (tag_rd_dta == TAG_VBUF) && tag_rd_valid;
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always @(posedge clk)
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if (~rst) vbr_wr_dta <= 64'b0;
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else if (mem_res_rd_valid) vbr_wr_dta <= mem_res_rd_dta;
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else vbr_wr_dta <= vbr_wr_dta;
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`ifdef DEBUG
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always @(posedge clk)
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case (state)
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STATE_INIT: #0 $display("%m STATE_INIT");
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STATE_WAIT: #0 $display("%m STATE_WAIT");
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STATE_FLUSH: #0 $display("%m STATE_FLUSH");
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STATE_READ: #0 $display("%m STATE_READ");
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STATE_WRITE: #0 $display("%m STATE_WRITE");
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default #0 $display("%m *** Error: unknown state %d", state);
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endcase
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always @(posedge clk)
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$strobe("%m\tmem_res_rd_dta: %h mem_res_rd_valid: %h tag_rd_dta: %h tag_rd_valid: %h fifos_not_ready: %h mem_res_rd_en: %h", mem_res_rd_dta, mem_res_rd_valid, tag_rd_dta, tag_rd_valid, fifos_not_ready, mem_res_rd_en);
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always @(posedge clk)
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begin
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$strobe("%m\tfwd_wr_dta: %h fwd_wr_dta_en: %h", fwd_wr_dta, fwd_wr_dta_en);
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$strobe("%m\tbwd_wr_dta: %h bwd_wr_dta_en: %h", bwd_wr_dta, bwd_wr_dta_en);
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$strobe("%m\tdisp_wr_dta: %h disp_wr_dta_en: %h", disp_wr_dta, disp_wr_dta_en);
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$strobe("%m\tvbr_wr_dta: %h vbr_wr_en: %h", vbr_wr_dta, vbr_wr_en);
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end
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always @(posedge clk)
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if (tag_rd_valid)
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case (tag_rd_dta)
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TAG_FWD: #0 $display ("%m\ttag_rd_dta: fwd");
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TAG_BWD: #0 $display ("%m\ttag_rd_dta: bwd");
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TAG_DISP: #0 $display ("%m\ttag_rd_dta: disp");
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TAG_VBUF: #0 $display ("%m\ttag_rd_dta: vbuf");
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default: #0 $display ("%m\t*** error: unknown tag %d ***", tag_rd_dta);
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endcase
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`endif
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`ifdef CHECK
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always @(posedge clk)
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if (fwd_wr_dta_full) #0 $display ("%m\t*** warning: memory stall possible: fwd_wr_dta_full ***");
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always @(posedge clk)
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if (bwd_wr_dta_full) #0 $display ("%m\t*** warning: memory stall possible: bwd_wr_dta_full ***");
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always @(posedge clk)
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if (disp_wr_dta_full) #0 $display ("%m\t*** warning: memory stall possible: disp_wr_dta_full ***");
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always @(posedge clk)
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if (vbr_wr_full) #0 $display ("%m\t*** warning: memory stall possible: vbr_wr_full ***");
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/*
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* Should never happen, but doesn't hurt to check.
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*/
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always @(posedge clk)
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if ((state == STATE_READ) && ((tag_rd_valid && ~mem_res_rd_valid) || (mem_res_rd_valid && ~tag_rd_valid)))
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begin
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#0 $display("%m\t*** error: tag and mem_res fifo unsynchronized tag_rd_valid: %d mem_res_rd_valid: %d ***", tag_rd_valid, mem_res_rd_valid);
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$stop;
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end
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always @(posedge clk)
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if (tag_rd_valid && (tag_rd_dta != TAG_FWD) && (tag_rd_dta != TAG_BWD) && (tag_rd_dta != TAG_DISP) && (tag_rd_dta != TAG_VBUF))
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begin
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#0 $display("%m\t*** error: unknown tag %d ***", tag_rd_dta);
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$stop;
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end
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`endif
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endmodule
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/* not truncated */
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