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kdv |
/*
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* iquant.v
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*
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* Copyright (c) 2007 Koen De Vleeschauwer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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`include "timescale.v"
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`undef DEBUG
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//`define DEBUG 1
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module intra_quant_matrix(clk, rst, rd_addr, rd_clk_en, dta_out, wr_addr, dta_in, wr_clk_en, wr_en, rst_values, alternate_scan);
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input clk;
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input rst;
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input [5:0]rd_addr;
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input rd_clk_en;
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output reg [7:0]dta_out;
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input [5:0]wr_addr;
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input [7:0]dta_in;
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input wr_en;
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input wr_clk_en;
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input rst_values;
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input alternate_scan;
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reg default_values;
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wire [7:0]do;
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reg [7:0]default_do;
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reg [5:0]iquant_wr_addr;
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reg iquant_wr_en;
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reg [7:0]iquant_wr_dta;
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parameter [2:0]
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STATE_INIT = 3'b001,
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STATE_CLEAR = 3'b010,
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STATE_RUN = 3'b100;
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reg [2:0]next;
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reg [2:0]state;
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/*
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* state machine to initialize intra_quantiser_matrix at reset
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*/
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always @*
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case (state)
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STATE_INIT: next = STATE_CLEAR;
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STATE_CLEAR: if (iquant_wr_addr == 6'h3f) next = STATE_RUN;
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else next = STATE_CLEAR;
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STATE_RUN: next = STATE_RUN;
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default: next = STATE_INIT;
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endcase
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always @(posedge clk)
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if (~rst) state <= STATE_INIT;
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else state <= next;
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always @(posedge clk)
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if (~rst) iquant_wr_en <= 1'b0;
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else
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case (state)
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STATE_INIT: iquant_wr_en <= 1'b0;
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STATE_CLEAR: iquant_wr_en <= 1'b1;
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STATE_RUN: iquant_wr_en <= wr_clk_en && wr_en;
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default iquant_wr_en <= 1'b0;
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endcase
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always @(posedge clk)
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if (~rst) iquant_wr_addr <= 6'b0;
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else
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case (state)
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STATE_INIT: iquant_wr_addr <= 6'b0;
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STATE_CLEAR: iquant_wr_addr <= iquant_wr_addr + 6'b1;
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STATE_RUN: iquant_wr_addr <= scan_reverse(alternate_scan, wr_addr);
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default iquant_wr_addr <= 6'b0;
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endcase
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always @(posedge clk)
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if (~rst) iquant_wr_dta <= 8'b0;
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else
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case (state)
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STATE_INIT: iquant_wr_dta <= 8'b0;
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STATE_CLEAR: iquant_wr_dta <= 8'b0;
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STATE_RUN: iquant_wr_dta <= dta_in;
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default iquant_wr_dta <= 8'b0;
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endcase
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/* reading */
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always @(posedge clk)
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if (~rst) default_do <= 8'b0;
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else if (rd_clk_en) default_do <= default_intra_quant(rd_addr);
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else default_do <= default_do;
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always @(posedge clk)
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if (~rst) dta_out <= 8'b0;
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else if (rd_clk_en && default_values) dta_out <= default_do;
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else if (rd_clk_en) dta_out <= do;
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else dta_out <= dta_out;
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always @(posedge clk)
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if (~rst) default_values <= 1;
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else if (wr_clk_en && rst_values) default_values <= 1;
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else if (wr_clk_en && wr_en && (wr_addr == 6'h3f)) default_values <= 0; // set after last of intra_quant values has been uploaded
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else default_values <= default_values;
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`include "zigzag_table.v"
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/*
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intra block quantisation matrix.
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par. 6.3.11: when sequence_header_code is decoded all matrices shall be reset to their default values.
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par. 7.3.1: inverse scan for quantization matrix download:
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the quantisation matrix is sent in zigzag (scan 0) order, so here we un-zigzag it using scan0_reverse.
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*/
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dpram_sc
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#(.addr_width(6), // number of bits in address bus
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.dta_width(8)) // number of bits in data bus
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intra_quantiser_matrix (
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.rst(rst), // reset, active low
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.clk(clk), // clock, rising edge trigger
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.wr_en(iquant_wr_en), // write enable, active high
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.wr_addr(iquant_wr_addr), // write address
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.din(iquant_wr_dta), // data input
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.rd_en(1'b1), // read enable, active high
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.rd_addr(rd_addr), // read address
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.dout(do) // data output
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);
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/*
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Default intra block quantisation matrix values. par. 6.3.11.
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*/
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function [7:0]default_intra_quant;
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input [5:0]u_v;
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begin
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casex(u_v)
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6'd00: default_intra_quant = 8;
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6'd01: default_intra_quant = 16;
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6'd02: default_intra_quant = 19;
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6'd03: default_intra_quant = 22;
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6'd04: default_intra_quant = 26;
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6'd05: default_intra_quant = 27;
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6'd06: default_intra_quant = 29;
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6'd07: default_intra_quant = 34;
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6'd08: default_intra_quant = 16;
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6'd09: default_intra_quant = 16;
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6'd10: default_intra_quant = 22;
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6'd11: default_intra_quant = 24;
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6'd12: default_intra_quant = 27;
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6'd13: default_intra_quant = 29;
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6'd14: default_intra_quant = 34;
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6'd15: default_intra_quant = 37;
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6'd16: default_intra_quant = 19;
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6'd17: default_intra_quant = 22;
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6'd18: default_intra_quant = 26;
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6'd19: default_intra_quant = 27;
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6'd20: default_intra_quant = 29;
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6'd21: default_intra_quant = 34;
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6'd22: default_intra_quant = 34;
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6'd23: default_intra_quant = 38;
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6'd24: default_intra_quant = 22;
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6'd25: default_intra_quant = 22;
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6'd26: default_intra_quant = 26;
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6'd27: default_intra_quant = 27;
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6'd28: default_intra_quant = 29;
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6'd29: default_intra_quant = 34;
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6'd30: default_intra_quant = 37;
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6'd31: default_intra_quant = 40;
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6'd32: default_intra_quant = 22;
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6'd33: default_intra_quant = 26;
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6'd34: default_intra_quant = 27;
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6'd35: default_intra_quant = 29;
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6'd36: default_intra_quant = 32;
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6'd37: default_intra_quant = 35;
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6'd38: default_intra_quant = 40;
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6'd39: default_intra_quant = 48;
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6'd40: default_intra_quant = 26;
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6'd41: default_intra_quant = 27;
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6'd42: default_intra_quant = 29;
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6'd43: default_intra_quant = 32;
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6'd44: default_intra_quant = 35;
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6'd45: default_intra_quant = 40;
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6'd46: default_intra_quant = 48;
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6'd47: default_intra_quant = 58;
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6'd48: default_intra_quant = 26;
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6'd49: default_intra_quant = 27;
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6'd50: default_intra_quant = 29;
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6'd51: default_intra_quant = 34;
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6'd52: default_intra_quant = 38;
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6'd53: default_intra_quant = 46;
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6'd54: default_intra_quant = 56;
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6'd55: default_intra_quant = 69;
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6'd56: default_intra_quant = 27;
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6'd57: default_intra_quant = 29;
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6'd58: default_intra_quant = 35;
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6'd59: default_intra_quant = 38;
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6'd60: default_intra_quant = 46;
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6'd61: default_intra_quant = 56;
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6'd62: default_intra_quant = 69;
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6'd63: default_intra_quant = 83;
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endcase
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end
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endfunction
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`ifdef DEBUG
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always @(posedge clk)
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if (rd_clk_en && default_values) #0 $display("%m\tread %h from %h (default value)", default_intra_quant(rd_addr), rd_addr);
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else if (rd_clk_en) #0 $display("%m\tread %h from %h", do, rd_addr);
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always @(posedge clk)
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if (~rst) $display("%m\tset to default values");
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else if (wr_clk_en && rst_values) $display("%m\tset to default values");
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else if (wr_clk_en && wr_en) $display("%m\tset to uploaded table");
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always @(posedge clk)
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if (wr_clk_en && wr_en) #0 $display("%m\twrite %h to %h (was %h)", dta_in, scan_reverse(alternate_scan, wr_addr), wr_addr);
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`endif
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endmodule
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module non_intra_quant_matrix(clk, rst, rd_addr, rd_clk_en, dta_out, wr_addr, dta_in, wr_clk_en, wr_en, rst_values, alternate_scan);
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input clk;
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input rst;
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input [5:0]rd_addr;
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input rd_clk_en;
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output reg [7:0]dta_out;
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input [5:0]wr_addr;
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input [7:0]dta_in;
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input wr_clk_en;
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input wr_en;
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input rst_values;
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input alternate_scan;
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reg default_values;
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wire [7:0]do;
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reg [5:0]non_iquant_wr_addr;
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reg non_iquant_wr_en;
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reg [7:0]non_iquant_wr_dta;
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parameter [2:0]
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STATE_INIT = 3'b001,
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STATE_CLEAR = 3'b010,
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STATE_RUN = 3'b100;
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reg [2:0]next;
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reg [2:0]state;
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/*
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* state machine to initialize intra_quantiser_matrix at reset
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*/
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always @*
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case (state)
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STATE_INIT: next = STATE_CLEAR;
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STATE_CLEAR: if (non_iquant_wr_addr == 6'h3f) next = STATE_RUN;
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else next = STATE_CLEAR;
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STATE_RUN: next = STATE_RUN;
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default: next = STATE_INIT;
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endcase
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always @(posedge clk)
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if (~rst) state <= STATE_INIT;
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else state <= next;
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always @(posedge clk)
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if (~rst) non_iquant_wr_en <= 1'b0;
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else
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case (state)
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STATE_INIT: non_iquant_wr_en <= 1'b0;
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STATE_CLEAR: non_iquant_wr_en <= 1'b1;
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STATE_RUN: non_iquant_wr_en <= wr_clk_en && wr_en;
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default non_iquant_wr_en <= 1'b0;
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endcase
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always @(posedge clk)
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if (~rst) non_iquant_wr_addr <= 6'b0;
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else
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case (state)
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STATE_INIT: non_iquant_wr_addr <= 6'b0;
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STATE_CLEAR: non_iquant_wr_addr <= non_iquant_wr_addr + 6'b1;
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STATE_RUN: non_iquant_wr_addr <= scan_reverse(alternate_scan, wr_addr);
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default non_iquant_wr_addr <= 6'b0;
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endcase
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always @(posedge clk)
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if (~rst) non_iquant_wr_dta <= 8'b0;
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else
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case (state)
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STATE_INIT: non_iquant_wr_dta <= 8'b0;
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STATE_CLEAR: non_iquant_wr_dta <= 8'b0;
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STATE_RUN: non_iquant_wr_dta <= dta_in;
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default non_iquant_wr_dta <= 8'b0;
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endcase
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/* reading */
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always @(posedge clk)
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if (rd_clk_en && default_values) dta_out <= 8'd16 ; // Default non intra block quantisation matrix value is 8'd16. par. 6.3.11.
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else if (rd_clk_en) dta_out <= do;
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else dta_out <= dta_out;
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always @(posedge clk)
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if (~rst) default_values <= 1;
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else if (wr_clk_en && rst_values) default_values <= 1;
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else if (wr_clk_en && wr_en && (wr_addr == 6'h3f)) default_values <= 0; // set after last of non_intra_quant values has been uploaded
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else default_values <= default_values;
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`include "zigzag_table.v"
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/*
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non intra block quantisation matrix.
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par. 6.3.11: when sequence_header_code is decoded all matrices shall be reset to their default values.
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325 |
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par. 7.3.1: inverse scan for quantization matrix download:
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326 |
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the quantisation matrix is sent in zigzag (scan 0) order, so here we un-zigzag it using scan0_reverse.
|
327 |
|
|
*/
|
328 |
|
|
|
329 |
|
|
dpram_sc
|
330 |
|
|
#(.addr_width(6), // number of bits in address bus
|
331 |
|
|
.dta_width(8)) // number of bits in data bus
|
332 |
|
|
non_intra_quantiser_matrix (
|
333 |
|
|
.rst(rst), // reset, active low
|
334 |
|
|
.clk(clk), // clock, rising edge trigger
|
335 |
|
|
.wr_en(non_iquant_wr_en), // write enable, active high
|
336 |
|
|
.wr_addr(non_iquant_wr_addr), // write address
|
337 |
|
|
.din(non_iquant_wr_dta), // data input
|
338 |
|
|
.rd_en(1'b1), // read enable, active high
|
339 |
|
|
.rd_addr(rd_addr), // read address
|
340 |
|
|
.dout(do) // data output
|
341 |
|
|
);
|
342 |
|
|
|
343 |
|
|
`ifdef DEBUG
|
344 |
|
|
always @(posedge clk)
|
345 |
|
|
if (rd_clk_en && default_values) #0 $display("%m\tread %h from %h (default value)", 8'd16, rd_addr);
|
346 |
|
|
else if (rd_clk_en) #0 $display("%m\tread %h from %h", do, rd_addr);
|
347 |
|
|
|
348 |
|
|
always @(posedge clk)
|
349 |
|
|
if (~rst) $display("%m\tset to default values");
|
350 |
|
|
else if (wr_clk_en && rst_values) $display("%m\tset to default values");
|
351 |
|
|
else if (wr_clk_en && wr_en && (wr_addr == 6'h3f)) $display("%m\tset to uploaded table");
|
352 |
|
|
|
353 |
|
|
always @(posedge clk)
|
354 |
|
|
if (wr_clk_en && wr_en) #0 $display("%m\twrite %h to %h (was %h)", dta_in, scan_reverse(alternate_scan, wr_addr), wr_addr);
|
355 |
|
|
|
356 |
|
|
`endif
|
357 |
|
|
|
358 |
|
|
endmodule
|
359 |
|
|
/* not truncated */
|