1 |
2 |
kdv |
/*
|
2 |
|
|
* fifo_sc.v
|
3 |
|
|
*
|
4 |
|
|
* Copyright (c) 2007 Koen De Vleeschauwer.
|
5 |
|
|
*
|
6 |
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
7 |
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
8 |
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
9 |
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
10 |
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
11 |
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
12 |
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
13 |
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
14 |
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
15 |
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
16 |
|
|
* SUCH DAMAGE.
|
17 |
|
|
*/
|
18 |
|
|
|
19 |
|
|
/*
|
20 |
|
|
* fifo with common clock for read and write port.
|
21 |
|
|
*/
|
22 |
|
|
|
23 |
|
|
`include "timescale.v"
|
24 |
|
|
|
25 |
|
|
module xfifo_sc (
|
26 |
|
|
clk,
|
27 |
|
|
rst,
|
28 |
|
|
din,
|
29 |
|
|
wr_en,
|
30 |
|
|
full,
|
31 |
|
|
wr_ack,
|
32 |
|
|
overflow,
|
33 |
|
|
prog_full,
|
34 |
|
|
dout,
|
35 |
|
|
rd_en,
|
36 |
|
|
empty,
|
37 |
|
|
valid,
|
38 |
|
|
underflow,
|
39 |
|
|
prog_empty
|
40 |
|
|
);
|
41 |
|
|
|
42 |
|
|
parameter [8:0]dta_width=9'd8; /* Data bus width */
|
43 |
|
|
parameter [8:0]addr_width=9'd8; /* Address bus width, determines fifo size by evaluating 2^addr_width */
|
44 |
|
|
parameter [8:0]prog_thresh=9'd1; /* Programmable threshold constant for prog_empty and prog_full */
|
45 |
|
|
|
46 |
|
|
input clk;
|
47 |
|
|
input rst; /* low active sync master reset */
|
48 |
|
|
/* read port */
|
49 |
|
|
output reg [dta_width-1:0]dout; /* data output */
|
50 |
|
|
input rd_en; /* read enable */
|
51 |
|
|
output reg empty; /* asserted if fifo is empty; no additional reads can be performed */
|
52 |
|
|
output reg valid; /* valid (read acknowledge): indicates rd_en was asserted during previous clock cycle and data was succesfully read from fifo and placed on dout */
|
53 |
|
|
output reg underflow; /* underflow (read error): indicates rd_en was asserted during previous clock cycle but no data was read from fifo because fifo was empty */
|
54 |
|
|
output reg prog_empty; /* indicates the fifo has prog_thresh entries, or less. threshold for asserting prog_empty is prog_thresh */
|
55 |
|
|
/* write port */
|
56 |
|
|
input [dta_width-1:0]din; /* data input */
|
57 |
|
|
input wr_en; /* write enable */
|
58 |
|
|
output reg full; /* asserted if fifo is full; no additional writes can be performed */
|
59 |
|
|
output reg overflow; /* overflow (write error): indicates wr_en was asserted during previous clock cycle but no data was written to fifo because fifo was full */
|
60 |
|
|
output reg wr_ack; /* write acknowledge: indicates wr_en was asserted during previous clock cycle and data was succesfully written to fifo */
|
61 |
|
|
output reg prog_full; /* indicates the fifo has prog_thresh free entries, or less, left. threshold for asserting prog_full is 2^addr_width - prog_thresh */
|
62 |
|
|
|
63 |
|
|
/* Writing when the fifo is full, or reading while the fifo is empty, does not destroy the contents of the fifo. */
|
64 |
|
|
|
65 |
|
|
/*
|
66 |
|
|
* read and write addresses
|
67 |
|
|
*/
|
68 |
|
|
|
69 |
|
|
reg [addr_width:0]wr_addr;
|
70 |
|
|
reg [addr_width:0]rd_addr;
|
71 |
|
|
reg [addr_width:0]next_wr_addr;
|
72 |
|
|
reg [addr_width:0]next_rd_addr;
|
73 |
|
|
|
74 |
|
|
always @*
|
75 |
|
|
if (wr_en && ~full) next_wr_addr = wr_addr + 1'b1;
|
76 |
|
|
else next_wr_addr = wr_addr;
|
77 |
|
|
|
78 |
|
|
always @*
|
79 |
|
|
if (rd_en && ~empty) next_rd_addr = rd_addr + 1'b1;
|
80 |
|
|
else next_rd_addr = rd_addr;
|
81 |
|
|
|
82 |
|
|
always @(posedge clk)
|
83 |
|
|
if (~rst) wr_addr <= 1'b0;
|
84 |
|
|
else wr_addr <= next_wr_addr;
|
85 |
|
|
|
86 |
|
|
always @(posedge clk)
|
87 |
|
|
if (~rst) rd_addr <= 1'b0;
|
88 |
|
|
else rd_addr <= next_rd_addr;
|
89 |
|
|
|
90 |
|
|
/*
|
91 |
|
|
* empty and full
|
92 |
|
|
*/
|
93 |
|
|
|
94 |
|
|
always @(posedge clk)
|
95 |
|
|
if (~rst) empty <= 1'b1;
|
96 |
|
|
else empty <= (next_wr_addr == next_rd_addr);
|
97 |
|
|
|
98 |
|
|
always @(posedge clk)
|
99 |
|
|
if (~rst) full <= 1'b0;
|
100 |
|
|
else full <= (next_wr_addr[addr_width-1:0] == next_rd_addr[addr_width-1:0]) && (next_wr_addr[addr_width] != next_rd_addr[addr_width]);
|
101 |
|
|
|
102 |
|
|
/*
|
103 |
|
|
* valid and wr_ack
|
104 |
|
|
*/
|
105 |
|
|
|
106 |
|
|
always @(posedge clk)
|
107 |
|
|
if (~rst) valid <= 1'b0;
|
108 |
|
|
else valid <= rd_en && ~empty;
|
109 |
|
|
|
110 |
|
|
always @(posedge clk)
|
111 |
|
|
if (~rst) wr_ack <= 1'b0;
|
112 |
|
|
else wr_ack <= wr_en && ~full;
|
113 |
|
|
|
114 |
|
|
/*
|
115 |
|
|
* underflow and overflow
|
116 |
|
|
*/
|
117 |
|
|
|
118 |
|
|
always @(posedge clk)
|
119 |
|
|
if (~rst) underflow <= 1'b0;
|
120 |
|
|
else underflow <= rd_en && empty;
|
121 |
|
|
|
122 |
|
|
always @(posedge clk)
|
123 |
|
|
if (~rst) overflow <= 1'b0;
|
124 |
|
|
else overflow <= wr_en && full;
|
125 |
|
|
|
126 |
|
|
/*
|
127 |
|
|
* prog_empty and prog_full
|
128 |
|
|
*/
|
129 |
|
|
|
130 |
|
|
wire [addr_width:0]next_count = next_wr_addr - next_rd_addr;
|
131 |
|
|
wire [addr_width:0]lower_threshold = prog_thresh + 1'b1;
|
132 |
|
|
wire [addr_width:0]max_count = 1'b1 << addr_width;
|
133 |
|
|
wire [addr_width:0]upper_threshold = max_count - lower_threshold;
|
134 |
|
|
|
135 |
|
|
always @(posedge clk)
|
136 |
|
|
if (~rst) prog_empty <= 1'b1;
|
137 |
|
|
else prog_empty <= (next_count < lower_threshold);
|
138 |
|
|
|
139 |
|
|
always @(posedge clk)
|
140 |
|
|
if (~rst) prog_full <= 1'b0;
|
141 |
|
|
else prog_full <= (next_count > upper_threshold);
|
142 |
|
|
|
143 |
|
|
/*
|
144 |
|
|
* dual-port ram w/registered output
|
145 |
|
|
*/
|
146 |
|
|
|
147 |
|
|
reg [dta_width-1:0]ram[(1 << addr_width)-1:0];
|
148 |
|
|
|
149 |
|
|
always @(posedge clk)
|
150 |
|
|
if (~rst) dout <= 0;
|
151 |
|
|
else if (~empty) dout <= ram[rd_addr[addr_width-1:0]];
|
152 |
|
|
else dout <= dout;
|
153 |
|
|
|
154 |
|
|
always @(posedge clk)
|
155 |
|
|
if (wr_en && ~full) ram[wr_addr[addr_width-1:0]] <= din;
|
156 |
|
|
|
157 |
|
|
endmodule
|
158 |
|
|
/* not truncated */
|