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/*
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* xilinx_fifo.v
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*
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* Copyright (c) 2007 Koen De Vleeschauwer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* fifos, implemented using Xilinx Virtex5 primitives.
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* See "Virtex-5 Libraries Guide for HDL Designs", Xilinx v5ldl.
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* and "Virtex-5 User Guide", Xilinx ug190.
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*
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* Note when resetting Xilinx FIFO18/FIFO36 primitives:
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* "The reset signal must be high for at least three read clock and three write clock cycles." Caveat emptor.
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*/
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`include "timescale.v"
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module xilinx_fifo (
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ALMOSTEMPTY,
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ALMOSTFULL,
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DO,
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EMPTY,
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FULL,
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RDERR,
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VALID,
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WRERR,
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WR_ACK,
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DI,
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RDCLK,
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RDEN,
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RST,
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WRCLK,
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WREN
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);
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parameter [9:0]ALMOST_FULL_OFFSET=9'h080;
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parameter [9:0]ALMOST_EMPTY_OFFSET=9'h080;
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parameter [9:0]DATA_WIDTH=9'd217;
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parameter [9:0]ADDR_WIDTH=9'd14;
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parameter DO_REG=1;
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parameter EN_SYN="FALSE";
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output ALMOSTEMPTY;
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output ALMOSTFULL;
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output [DATA_WIDTH-1:0]DO;
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output EMPTY;
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output FULL;
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output RDERR;
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output reg VALID;
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output WRERR;
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output reg WR_ACK;
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input [DATA_WIDTH-1:0]DI;
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input RDCLK;
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input RDEN;
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input RST;
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input WRCLK;
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input WREN;
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/* VALID and WR_ACK flags */
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always @(posedge WRCLK)
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if (RST) WR_ACK <= 1'b0;
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else WR_ACK <= WREN && ~FULL;
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always @(posedge RDCLK)
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if (RST) VALID <= 1'b0;
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else VALID <= RDEN && ~EMPTY;
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/* instantiate FIFO */
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generate
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if ((DATA_WIDTH <= 9'd4) && (ADDR_WIDTH <= 9'd12))
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begin
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wire [15:0]din;
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wire [1:0]dinp;
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wire [15:0]dout;
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wire [1:0]doutp;
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assign DO = dout[3:0];
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assign din = DI;
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assign dinp = 2'b0;
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// FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO18 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DATA_WIDTH(9'd4), // Sets data width to 4, 9 or 18
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.DO_REG(DO_REG), // Enable output register (0 or 1) output register usage
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// Must be 1 if EN_SYN = "FALSE
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.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
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// or Synchronous ("TRUE")
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
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) FIFO18_width_4 (
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.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
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.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
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.DO(dout), // 16-bit data output
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.DOP(doutp), // 2-bit parity data output
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.EMPTY(EMPTY), // 1-bit empty output flag
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.FULL(FULL), // 1-bit full output flag
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.RDERR(RDERR), // 1-bit read error output
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.WRCOUNT(), // 12-bit write count output
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.WRERR(WRERR), // 1-bit write error
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.DI(din), // 16-bit data input
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.DIP(dinp), // 2-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(RDEN), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(WREN) // 1-bit write enable input
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);
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end
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else if ((DATA_WIDTH <= 9'd4) && (ADDR_WIDTH <= 9'd13))
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begin
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wire [31:0]din;
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wire [3:0]dinp;
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wire [31:0]dout;
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wire [3:0]doutp;
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assign DO = dout[3:0];
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assign din = DI;
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assign dinp = 4'b0;
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// FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO36 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DATA_WIDTH(4), // Sets data width to 4, 9, 18 or 36
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.DO_REG(DO_REG), // Enable output register (0 or 1)register usage
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// Must be 1 if EN_SYN = "FALSE
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.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
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) FIFO36_width_4 (
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.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
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.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
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.DO(dout), // 32-bit data output
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.DOP(doutp), // 4-bit parity data output
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.EMPTY(EMPTY), // 1-bit empty output flag
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.FULL(FULL), // 1-bit full output flag
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.RDCOUNT(), // 13-bit read count output
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.RDERR(RDERR), // 1-bit read error output
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.WRCOUNT(), // 13-bit write count output
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.WRERR(WRERR), // 1-bit write error
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.DI(din), // FIFO data input, width determined by DATA_WIDTH
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.DIP(dinp), // 4-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(RDEN), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(WREN) // 1-bit write enable input
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);
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end
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else if ((DATA_WIDTH <= 9'd9) && (ADDR_WIDTH <= 9'd11))
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begin
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wire [15:0]din;
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wire [1:0]dinp;
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wire [15:0]dout;
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wire [1:0]doutp;
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wire [8:0]DIN = DI; // extend DI to 9 bit, if needed
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assign DO = {doutp[0], dout[7:0]};
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assign din = DIN[7:0];
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assign dinp = DIN[8];
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// FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO18 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DATA_WIDTH(9), // Sets data width to 4, 9 or 18
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.DO_REG(DO_REG), // Enable output register (0 or 1) output register usage
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// Must be 1 if EN_SYN = "FALSE
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.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
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// or Synchronous ("TRUE")
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
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) FIFO18_width_9 (
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.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
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.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
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.DO(dout), // 16-bit data output
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.DOP(doutp), // 2-bit parity data output
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.EMPTY(EMPTY), // 1-bit empty output flag
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.FULL(FULL), // 1-bit full output flag
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.RDERR(RDERR), // 1-bit read error output
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.WRCOUNT(), // 12-bit write count output
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.WRERR(WRERR), // 1-bit write error
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.DI(din), // 16-bit data input
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.DIP(dinp), // 2-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(RDEN), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(WREN) // 1-bit write enable input
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);
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end
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else if ((DATA_WIDTH <= 9'd9) && (ADDR_WIDTH <= 9'd12))
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begin
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wire [31:0]din;
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wire [3:0]dinp;
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wire [31:0]dout;
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wire [3:0]doutp;
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wire [8:0]DIN = DI; // extend DI to 9 bit, if needed
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assign DO = {doutp[0], dout[7:0]};
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assign din = DIN[7:0];
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assign dinp = DIN[8];
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// FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO36 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DATA_WIDTH(9), // Sets data width to 4, 9, 18 or 36
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.DO_REG(DO_REG), // Enable output register (0 or 1)register usage
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// Must be 1 if EN_SYN = "FALSE
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.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
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) FIFO36_width_9 (
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.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
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.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
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.DO(dout), // 32-bit data output
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.DOP(doutp), // 4-bit parity data output
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.EMPTY(EMPTY), // 1-bit empty output flag
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.FULL(FULL), // 1-bit full output flag
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.RDCOUNT(), // 13-bit read count output
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.RDERR(RDERR), // 1-bit read error output
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.WRCOUNT(), // 13-bit write count output
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.WRERR(WRERR), // 1-bit write error
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.DI(din), // FIFO data input, width determined by DATA_WIDTH
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.DIP(dinp), // 4-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(RDEN), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(WREN) // 1-bit write enable input
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);
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end
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else if ((DATA_WIDTH <= 9'd18) && (ADDR_WIDTH <= 9'd10))
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begin
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wire [15:0]din;
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wire [1:0]dinp;
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wire [15:0]dout;
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wire [1:0]doutp;
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wire [17:0]DIN = DI; // extend DI to 18 bit, if needed
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assign DO = {doutp, dout};
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assign {dinp, din} = DIN;
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// FIFO18: 16k+2k Parity Synchronous/Asynchronous BlockRAM FIFO
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO18 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DATA_WIDTH(18), // Sets data width to 4, 9 or 18
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.DO_REG(DO_REG), // Enable output register (0 or 1) output register usage
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// Must be 1 if EN_SYN = "FALSE
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.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
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// or Synchronous ("TRUE")
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
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) FIFO18_width_18 (
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.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
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.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
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.DO(dout), // 16-bit data output
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.DOP(doutp), // 2-bit parity data output
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.EMPTY(EMPTY), // 1-bit empty output flag
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.FULL(FULL), // 1-bit full output flag
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.RDERR(RDERR), // 1-bit read error output
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.WRCOUNT(), // 12-bit write count output
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.WRERR(WRERR), // 1-bit write error
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.DI(din), // 16-bit data input
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.DIP(dinp), // 2-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(RDEN), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(WREN) // 1-bit write enable input
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);
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end
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else if ((DATA_WIDTH <= 9'd18) && (ADDR_WIDTH <= 9'd11))
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begin
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wire [31:0]din;
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wire [3:0]dinp;
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wire [31:0]dout;
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wire [3:0]doutp;
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wire [17:0]DIN = DI; // extend DI to 18 bit, if needed
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assign DO = {doutp[1:0], dout[15:0]};
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assign din = DIN[15:0];
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assign dinp = DIN[17:16];
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// FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
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311 |
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// Virtex-5
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312 |
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// Xilinx HDL Libraries Guide, version 8.2.2
|
313 |
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FIFO36 #(
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314 |
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|
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
|
315 |
|
|
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
|
316 |
|
|
.DATA_WIDTH(18), // Sets data width to 4, 9, 18 or 36
|
317 |
|
|
.DO_REG(DO_REG), // Enable output register (0 or 1)register usage
|
318 |
|
|
// Must be 1 if EN_SYN = "FALSE
|
319 |
|
|
.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
|
320 |
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
|
321 |
|
|
) FIFO36_width_18 (
|
322 |
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
323 |
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
324 |
|
|
.DO(dout), // 32-bit data output
|
325 |
|
|
.DOP(doutp), // 4-bit parity data output
|
326 |
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
327 |
|
|
.FULL(FULL), // 1-bit full output flag
|
328 |
|
|
.RDCOUNT(), // 13-bit read count output
|
329 |
|
|
.RDERR(RDERR), // 1-bit read error output
|
330 |
|
|
.WRCOUNT(), // 13-bit write count output
|
331 |
|
|
.WRERR(WRERR), // 1-bit write error
|
332 |
|
|
.DI(din), // FIFO data input, width determined by DATA_WIDTH
|
333 |
|
|
.DIP(dinp), // 4-bit parity input
|
334 |
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
335 |
|
|
.RDEN(RDEN), // 1-bit read enable input
|
336 |
|
|
.RST(RST), // 1-bit reset input
|
337 |
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
338 |
|
|
.WREN(WREN) // 1-bit write enable input
|
339 |
|
|
);
|
340 |
|
|
end
|
341 |
|
|
else if ((DATA_WIDTH <= 9'd36) && (ADDR_WIDTH <= 9'd9))
|
342 |
|
|
begin
|
343 |
|
|
wire [31:0]din;
|
344 |
|
|
wire [31:0]dout;
|
345 |
|
|
wire [3:0]dinp;
|
346 |
|
|
wire [3:0]doutp;
|
347 |
|
|
|
348 |
|
|
assign DO = {doutp, dout};
|
349 |
|
|
assign {dinp, din} = DI;
|
350 |
|
|
|
351 |
|
|
// FIFO18_36: 36x18k Synchronous/Asynchronous BlockRAM FIFO
|
352 |
|
|
// Virtex-5
|
353 |
|
|
// Xilinx HDL Libraries Guide, version 8.2.2
|
354 |
|
|
FIFO18_36 #(
|
355 |
|
|
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
|
356 |
|
|
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
|
357 |
|
|
.DO_REG(DO_REG), // Enable output register (0 or 1)
|
358 |
|
|
// Must be 1 if EN_SYN = "FALSE
|
359 |
|
|
.EN_SYN(EN_SYN), // Specifies FIFO as Asynchronous ("FALSE")
|
360 |
|
|
// or Synchronous ("TRUE")
|
361 |
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
|
362 |
|
|
) FIFO18_36_width_36 (
|
363 |
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
364 |
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
365 |
|
|
.DO(dout), // 32-bit data output
|
366 |
|
|
.DOP(doutp), // 4-bit parity data output
|
367 |
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
368 |
|
|
.FULL(FULL), // 1-bit full output flag
|
369 |
|
|
.RDCOUNT(), // 9-bit read count output
|
370 |
|
|
.RDERR(RDERR), // 1-bit read error output
|
371 |
|
|
.WRCOUNT(), // 9-bit write count output
|
372 |
|
|
.WRERR(WRERR), // 1-bit write error
|
373 |
|
|
.DI(din), // 32-bit data input
|
374 |
|
|
.DIP(dinp), // 4-bit parity input
|
375 |
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
376 |
|
|
.RDEN(RDEN), // 1-bit read enable input
|
377 |
|
|
.RST(RST), // 1-bit reset input
|
378 |
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
379 |
|
|
.WREN(WREN) // 1-bit write enable input
|
380 |
|
|
);
|
381 |
|
|
end
|
382 |
|
|
else if ((DATA_WIDTH <= 9'd36) && (ADDR_WIDTH <= 9'd10))
|
383 |
|
|
begin
|
384 |
|
|
wire [31:0]din;
|
385 |
|
|
wire [3:0]dinp;
|
386 |
|
|
wire [31:0]dout;
|
387 |
|
|
wire [3:0]doutp;
|
388 |
|
|
|
389 |
|
|
assign DO = {doutp, dout};
|
390 |
|
|
assign {dinp, din} = DI;
|
391 |
|
|
|
392 |
|
|
// FIFO36: 32k+4k Parity Synchronous/Asynchronous BlockRAM FIFO
|
393 |
|
|
// Virtex-5
|
394 |
|
|
// Xilinx HDL Libraries Guide, version 8.2.2
|
395 |
|
|
FIFO36 #(
|
396 |
|
|
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
|
397 |
|
|
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
|
398 |
|
|
.DATA_WIDTH(36), // Sets data width to 4, 9, 18 or 36
|
399 |
|
|
.DO_REG(DO_REG), // Enable output register (0 or 1)register usage
|
400 |
|
|
// Must be 1 if EN_SYN = "FALSE
|
401 |
|
|
.EN_SYN(EN_SYN), // FALSE when using independent read/write clocks; TRUE when using the same clock
|
402 |
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
|
403 |
|
|
) FIFO36_width_36 (
|
404 |
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
405 |
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
406 |
|
|
.DO(dout), // 32-bit data output
|
407 |
|
|
.DOP(doutp), // 4-bit parity data output
|
408 |
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
409 |
|
|
.FULL(FULL), // 1-bit full output flag
|
410 |
|
|
.RDCOUNT(), // 13-bit read count output
|
411 |
|
|
.RDERR(RDERR), // 1-bit read error output
|
412 |
|
|
.WRCOUNT(), // 13-bit write count output
|
413 |
|
|
.WRERR(WRERR), // 1-bit write error
|
414 |
|
|
.DI(din), // FIFO data input, width determined by DATA_WIDTH
|
415 |
|
|
.DIP(dinp), // 4-bit parity input
|
416 |
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
417 |
|
|
.RDEN(RDEN), // 1-bit read enable input
|
418 |
|
|
.RST(RST), // 1-bit reset input
|
419 |
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
420 |
|
|
.WREN(WREN) // 1-bit write enable input
|
421 |
|
|
);
|
422 |
|
|
end
|
423 |
|
|
else if ((DATA_WIDTH <= 9'd72) && (ADDR_WIDTH <= 9'd9))
|
424 |
|
|
begin
|
425 |
|
|
wire [63:0]din;
|
426 |
|
|
wire [63:0]dout;
|
427 |
|
|
wire [7:0]dinp;
|
428 |
|
|
wire [7:0]doutp;
|
429 |
|
|
|
430 |
|
|
assign DO = {doutp, dout};
|
431 |
|
|
assign {dinp, din} = DI;
|
432 |
|
|
|
433 |
|
|
// FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO /w ECC
|
434 |
|
|
// Virtex-5
|
435 |
|
|
// Xilinx HDL Libraries Guide, version 8.2.2
|
436 |
|
|
FIFO36_72 #(
|
437 |
|
|
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
|
438 |
|
|
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
|
439 |
|
|
.DO_REG(DO_REG), // Enable output register (0 or 1)
|
440 |
|
|
// Must be 1 if EN_SYN = "FALSE
|
441 |
|
|
.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE
|
442 |
|
|
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE
|
443 |
|
|
.EN_SYN(EN_SYN), // Specifies FIFO as Asynchronous ("FALSE")
|
444 |
|
|
// or Synchronous ("TRUE")
|
445 |
|
|
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
|
446 |
|
|
) FIFO36_72_width_72 (
|
447 |
|
|
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
448 |
|
|
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
449 |
|
|
.DBITERR(), // 1-bit double bit error status output
|
450 |
|
|
.DO(dout), // 32-bit data output
|
451 |
|
|
.DOP(doutp), // 4-bit parity data output
|
452 |
|
|
.ECCPARITY(), // 8-bit generated error correction parity
|
453 |
|
|
.EMPTY(EMPTY), // 1-bit empty output flag
|
454 |
|
|
.FULL(FULL), // 1-bit full output flag
|
455 |
|
|
.RDCOUNT(), // 9-bit read count output
|
456 |
|
|
.RDERR(RDERR), // 1-bit read error output
|
457 |
|
|
.SBITERR(), // 1-bit single bit error status output
|
458 |
|
|
.WRCOUNT(), // 9-bit write count output
|
459 |
|
|
.WRERR(WRERR), // 1-bit write error
|
460 |
|
|
.DI(din), // 32-bit data input
|
461 |
|
|
.DIP(dinp), // 4-bit parity input
|
462 |
|
|
.RDCLK(RDCLK), // 1-bit read clock input
|
463 |
|
|
.RDEN(RDEN), // 1-bit read enable input
|
464 |
|
|
.RST(RST), // 1-bit reset input
|
465 |
|
|
.WRCLK(WRCLK), // 1-bit write clock input
|
466 |
|
|
.WREN(WREN) // 1-bit write enable input
|
467 |
|
|
);
|
468 |
|
|
// End of FIFO36_72_inst instantiation
|
469 |
|
|
end
|
470 |
|
|
else if ((DATA_WIDTH <= 9'd144) && (ADDR_WIDTH <= 9'd9))
|
471 |
|
|
begin
|
472 |
|
|
wire [143:0]din;
|
473 |
|
|
wire [143:0]dout;
|
474 |
|
|
assign DO = dout;
|
475 |
|
|
assign din = DI;
|
476 |
|
|
|
477 |
|
|
// FIFO144: 144x36k Synchronous/Asynchronous BlockRAM FIFO
|
478 |
|
|
// Virtex-5
|
479 |
|
|
//
|
480 |
|
|
FIFO144 #(
|
481 |
|
|
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
|
482 |
|
|
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
|
483 |
|
|
.DO_REG(DO_REG),
|
484 |
|
|
.EN_SYN(EN_SYN)
|
485 |
|
|
)
|
486 |
|
|
FIFO144_width_144 (
|
487 |
|
|
.ALMOSTEMPTY(ALMOSTEMPTY),
|
488 |
|
|
.ALMOSTFULL(ALMOSTFULL),
|
489 |
|
|
.DO(dout),
|
490 |
|
|
.EMPTY(EMPTY),
|
491 |
|
|
.FULL(FULL),
|
492 |
|
|
.RDERR(RDERR),
|
493 |
|
|
.WRERR(WRERR),
|
494 |
|
|
.DI(din),
|
495 |
|
|
.RDCLK(RDCLK),
|
496 |
|
|
.RDEN(RDEN),
|
497 |
|
|
.RST(RST),
|
498 |
|
|
.WRCLK(WRCLK),
|
499 |
|
|
.WREN(WREN)
|
500 |
|
|
);
|
501 |
|
|
end
|
502 |
|
|
else if ((DATA_WIDTH <= 9'd216) && (ADDR_WIDTH <= 9'd9))
|
503 |
|
|
begin
|
504 |
|
|
wire [215:0]din;
|
505 |
|
|
wire [215:0]dout;
|
506 |
|
|
assign DO = dout;
|
507 |
|
|
assign din = DI;
|
508 |
|
|
|
509 |
|
|
// FIFO216: 216x36k Synchronous/Asynchronous BlockRAM FIFO
|
510 |
|
|
// Virtex-5
|
511 |
|
|
//
|
512 |
|
|
FIFO216 #(
|
513 |
|
|
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
|
514 |
|
|
.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
|
515 |
|
|
.DO_REG(DO_REG),
|
516 |
|
|
.EN_SYN(EN_SYN)
|
517 |
|
|
)
|
518 |
|
|
FIFO216_width_216 (
|
519 |
|
|
.ALMOSTEMPTY(ALMOSTEMPTY),
|
520 |
|
|
.ALMOSTFULL(ALMOSTFULL),
|
521 |
|
|
.DO(dout),
|
522 |
|
|
.EMPTY(EMPTY),
|
523 |
|
|
.FULL(FULL),
|
524 |
|
|
.RDERR(RDERR),
|
525 |
|
|
.WRERR(WRERR),
|
526 |
|
|
.DI(din),
|
527 |
|
|
.RDCLK(RDCLK),
|
528 |
|
|
.RDEN(RDEN),
|
529 |
|
|
.RST(RST),
|
530 |
|
|
.WRCLK(WRCLK),
|
531 |
|
|
.WREN(WREN)
|
532 |
|
|
);
|
533 |
|
|
end
|
534 |
|
|
else
|
535 |
|
|
begin
|
536 |
|
|
/*
|
537 |
|
|
* No suitable FIFO found. Generate error.
|
538 |
|
|
*/
|
539 |
|
|
initial $display("%m: fifo parameter error. DATA_WIDTH=%0d ADDR_WIDTH=%0d ALMOST_FULL_OFFSET=%0d ALMOST_EMPTY_OFFSET=%0d", DATA_WIDTH, ADDR_WIDTH, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET);
|
540 |
|
|
assign ALMOSTEMPTY = 1'bx;
|
541 |
|
|
assign ALMOSTFULL = 1'bx;
|
542 |
|
|
assign EMPTY = 1'bx;
|
543 |
|
|
assign FULL = 1'bx;
|
544 |
|
|
assign RDERR = 1'bx;
|
545 |
|
|
assign WRERR = 1'bx;
|
546 |
|
|
assign DO = {144{1'bx}};
|
547 |
|
|
initial $stop;
|
548 |
|
|
end
|
549 |
|
|
endgenerate
|
550 |
|
|
|
551 |
|
|
`ifdef CHECK_GENERATE
|
552 |
|
|
initial
|
553 |
|
|
$display("%m: fifo parameters: DATA_WIDTH=%0d ADDR_WIDTH=%0d ALMOST_FULL_OFFSET=%0d ALMOST_EMPTY_OFFSET=%0d DO_REG=%0d EN_SYN=%s",
|
554 |
|
|
DATA_WIDTH, ADDR_WIDTH, ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET, DO_REG, EN_SYN);
|
555 |
|
|
`endif
|
556 |
|
|
|
557 |
|
|
//`ifdef CHECK_FIFO_PARAMS
|
558 |
|
|
initial #0
|
559 |
|
|
begin
|
560 |
|
|
if ( ((EN_SYN == "TRUE") && ((ALMOST_FULL_OFFSET < 13'd1) || (ALMOST_EMPTY_OFFSET < 13'd1)))
|
561 |
|
|
|| ((EN_SYN == "FALSE") && ((ALMOST_FULL_OFFSET < 13'd4) || (ALMOST_EMPTY_OFFSET < 13'd5))) )
|
562 |
|
|
begin
|
563 |
|
|
#0 $display ("%m\t*** error: inconsistent fifo parameters. ALMOST_FULL_OFFSET: %d ALMOST_EMPTY_OFFSET: %d. ***", ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET);
|
564 |
|
|
$finish;
|
565 |
|
|
end
|
566 |
|
|
end
|
567 |
|
|
//`endif
|
568 |
|
|
|
569 |
|
|
endmodule
|
570 |
|
|
/* not truncated */
|