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/*
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* xilinx_fifo144.v
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*
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* Copyright (c) 2007 Koen De Vleeschauwer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* FIFO144
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* Connect two 72-bit wide FIFO36_72 in parallel to create one 144-bit wide fifo.
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*/
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`include "timescale.v"
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module FIFO144 (ALMOSTEMPTY, ALMOSTFULL, DO, EMPTY, FULL, RDERR, WRERR, DI, RDCLK, RDEN, RST, WRCLK, WREN);
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parameter [8:0]ALMOST_FULL_OFFSET=9'h080;
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parameter [8:0]ALMOST_EMPTY_OFFSET=9'h080;
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parameter DO_REG=1;
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parameter EN_SYN="FALSE";
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output ALMOSTEMPTY;
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output ALMOSTFULL;
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output [143:0]DO;
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output EMPTY;
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output FULL;
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output reg RDERR;
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output reg WRERR;
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input [143:0]DI;
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input RDCLK;
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input RDEN;
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input RST;
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input WRCLK;
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input WREN;
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wire fifo_wren;
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wire fifo_rden;
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wire [63:0]fifo1_di;
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wire [7:0]fifo1_dip;
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wire [63:0]fifo1_do;
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wire [7:0]fifo1_dop;
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wire fifo1_empty;
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wire fifo1_full;
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wire fifo1_almost_empty;
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wire fifo1_almost_full;
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wire fifo1_rderr;
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wire fifo1_wrerr;
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wire [63:0]fifo2_di;
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wire [7:0]fifo2_dip;
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wire [63:0]fifo2_do;
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wire [7:0]fifo2_dop;
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wire fifo2_empty;
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wire fifo2_full;
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wire fifo2_almost_empty;
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wire fifo2_almost_full;
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wire fifo2_rderr;
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wire fifo2_wrerr;
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assign DO = {fifo2_dop, fifo2_do, fifo1_dop, fifo1_do};
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assign {fifo2_dip,fifo2_di, fifo1_dip, fifo1_di} = DI;
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assign EMPTY = fifo1_empty || fifo2_empty;
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assign FULL = fifo1_full || fifo2_full;
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assign ALMOSTEMPTY = fifo1_almost_empty || fifo2_almost_empty;
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assign ALMOSTFULL = fifo1_almost_full || fifo2_almost_full;
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always @(posedge RDCLK)
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if (RST) RDERR <= 1'b0;
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else RDERR <= RDEN && EMPTY;
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always @(posedge WRCLK)
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if (RST) WRERR <= 1'b0;
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else WRERR <= WREN && FULL;
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assign fifo_wren = WREN && ~FULL;
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assign fifo_rden = RDEN && ~EMPTY;
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// FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO /w ECC
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO36_72 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DO_REG(DO_REG), // Enable output register (0 or 1)
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// Must be 1 if EN_SYN = "FALSE"
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.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
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.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
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.EN_SYN(EN_SYN), // Specifies FIFO as Asynchronous ("FALSE")
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// or Synchronous ("TRUE")
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
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) FIFO36_72_slice0 (
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.ALMOSTEMPTY(fifo1_almost_empty), // 1-bit almost empty output flag
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.ALMOSTFULL(fifo1_almost_full), // 1-bit almost full output flag
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.DBITERR(), // 1-bit double bit error status output
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.DO(fifo1_do), // 32-bit data output
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.DOP(fifo1_dop), // 4-bit parity data output
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.ECCPARITY(), // 8-bit generated error correction parity
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.EMPTY(fifo1_empty), // 1-bit empty output flag
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.FULL(fifo1_full), // 1-bit full output flag
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.RDCOUNT(), // 9-bit read count output
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.RDERR(fifo1_rderr), // 1-bit read error output
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.SBITERR(), // 1-bit single bit error status output
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.WRCOUNT(), // 9-bit write count output
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.WRERR(fifo1_wrerr), // 1-bit write error
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.DI(fifo1_di), // 32-bit data input
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.DIP(fifo1_dip), // 4-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(fifo_rden), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(fifo_wren) // 1-bit write enable input
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);
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// FIFO36_72: 72x36k Synchronous/Asynchronous BlockRAM FIFO /w ECC
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// Virtex-5
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// Xilinx HDL Libraries Guide, version 8.2.2
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FIFO36_72 #(
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.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), // Sets almost full threshold
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.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), // Sets the almost empty threshold
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.DO_REG(DO_REG), // Enable output register (0 or 1)
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// Must be 1 if EN_SYN = "FALSE"
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.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
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.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
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.EN_SYN(EN_SYN), // Specifies FIFO as Asynchronous ("FALSE")
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// or Synchronous ("TRUE")
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.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE
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) FIFO36_72_slice1 (
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.ALMOSTEMPTY(fifo2_almost_empty), // 1-bit almost empty output flag
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.ALMOSTFULL(fifo2_almost_full), // 1-bit almost full output flag
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.DBITERR(), // 1-bit double bit error status output
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.DO(fifo2_do), // 32-bit data output
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.DOP(fifo2_dop), // 4-bit parity data output
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.ECCPARITY(), // 8-bit generated error correction parity
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.EMPTY(fifo2_empty), // 1-bit empty output flag
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.FULL(fifo2_full), // 1-bit full output flag
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.RDCOUNT(), // 9-bit read count output
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.RDERR(fifo2_rderr), // 1-bit read error output
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.SBITERR(), // 1-bit single bit error status output
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.WRCOUNT(), // 9-bit write count output
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.WRERR(fifo2_wrerr), // 1-bit write error
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.DI(fifo2_di), // 32-bit data input
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.DIP(fifo2_dip), // 4-bit parity input
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.RDCLK(RDCLK), // 1-bit read clock input
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.RDEN(fifo_rden), // 1-bit read enable input
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.RST(RST), // 1-bit reset input
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.WRCLK(WRCLK), // 1-bit write clock input
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.WREN(fifo_wren) // 1-bit write enable input
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);
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`ifdef CHECK_GENERATE
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initial
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$display("%m: fifo parameters: ALMOST_FULL_OFFSET=%0d ALMOST_EMPTY_OFFSET=%0d DO_REG=%0d EN_SYN=%s",
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ALMOST_FULL_OFFSET, ALMOST_EMPTY_OFFSET, DO_REG, EN_SYN);
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`endif
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endmodule
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/* not truncated */
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