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[/] [mpmc8/] [trunk/] [rtl/] [mpcm8_read_cache.sv] - Blame information for rev 5

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Line No. Rev Author Line
1 2 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_read_cache(rst, wclk, wr, wadr, wdat, inv,
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        rclk0, radr0, rdat0, hit0,
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        rclk1, radr1, rdat1, hit1,
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        rclk2, radr2, rdat2, hit2,
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        rclk3, radr3, rdat3, hit3,
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        rclk4, radr4, rdat4, hit4,
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        rclk5, radr5, rdat5, hit5,
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        rclk6, radr6, rdat6, hit6,
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        rclk7, radr7, rdat7, hit7
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);
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input rst;
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input wclk;
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input wr;
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input [31:0] wadr;
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input [127:0] wdat;
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input inv;
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input rclk0;
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input [31:0] radr0;
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output reg [127:0] rdat0;
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output reg hit0;
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input rclk1;
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input [31:0] radr1;
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output reg [127:0] rdat1;
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output reg hit1;
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input rclk2;
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input [31:0] radr2;
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output reg [127:0] rdat2;
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output reg hit2;
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input rclk3;
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input [31:0] radr3;
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output reg [127:0] rdat3;
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output reg hit3;
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input rclk4;
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input [31:0] radr4;
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output reg [127:0] rdat4;
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output reg hit4;
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input rclk5;
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input [31:0] radr5;
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output reg [127:0] rdat5;
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output reg hit5;
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input rclk6;
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input [31:0] radr6;
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output reg [127:0] rdat6;
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output reg hit6;
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input rclk7;
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input [31:0] radr7;
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output reg [127:0] rdat7;
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output reg hit7;
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(* ram_style="block" *)
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reg [127:0] lines [0:1023];
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(* ram_style="block" *)
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reg [27:0] tags [0:1023];
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(* ram_style="distributed" *)
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reg [1023:0] vbit;
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reg [31:0] radrr0;
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reg [31:0] radrr1;
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reg [31:0] radrr2;
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reg [31:0] radrr3;
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reg [31:0] radrr4;
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reg [31:0] radrr5;
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reg [31:0] radrr6;
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reg [31:0] radrr7;
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reg [27:0] tago0;
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reg [27:0] tago1;
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reg [27:0] tago2;
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reg [27:0] tago3;
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reg [27:0] tago4;
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reg [27:0] tago5;
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reg [27:0] tago6;
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reg [27:0] tago7;
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reg vbito0;
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reg vbito1;
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reg vbito2;
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reg vbito3;
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reg vbito4;
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reg vbito5;
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reg vbito6;
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reg vbito7;
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always_ff @(posedge rclk0)
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        radrr0 <= radr0;
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always_ff @(posedge rclk1)
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        radrr1 <= radr1;
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always_ff @(posedge rclk2)
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        radrr2 <= radr2;
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always_ff @(posedge rclk3)
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        radrr3 <= radr3;
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always_ff @(posedge rclk4)
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        radrr4 <= radr4;
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always_ff @(posedge rclk5)
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        radrr5 <= radr5;
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always_ff @(posedge rclk6)
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        radrr6 <= radr6;
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always_ff @(posedge rclk7)
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        radrr7 <= radr7;
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always_ff @(posedge wclk)
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        if (wr) lines[wadr[13:4]] <= wdat;
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always_ff @(posedge rclk0)
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        rdat0 <= lines[radrr0[13:4]];
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always_ff @(posedge rclk1)
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        rdat1 <= lines[radrr1[13:4]];
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always_ff @(posedge rclk2)
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        rdat2 <= lines[radrr2[13:4]];
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always_ff @(posedge rclk3)
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        rdat3 <= lines[radrr3[13:4]];
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always_ff @(posedge rclk4)
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        rdat4 <= lines[radrr4[13:4]];
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always_ff @(posedge rclk5)
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        rdat5 <= lines[radrr5[13:4]];
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always_ff @(posedge rclk6)
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        rdat6 <= lines[radrr6[13:4]];
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always_ff @(posedge rclk7)
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        rdat7 <= lines[radrr7[13:4]];
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always_ff @(posedge rclk0)
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        tago0 <= tags[radrr0[13:4]];
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always_ff @(posedge rclk1)
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        tago1 <= tags[radrr1[13:4]];
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always_ff @(posedge rclk2)
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        tago2 <= tags[radrr2[13:4]];
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always_ff @(posedge rclk3)
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        tago3 <= tags[radrr3[13:4]];
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always_ff @(posedge rclk4)
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        tago4 <= tags[radrr4[13:4]];
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always_ff @(posedge rclk5)
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        tago5 <= tags[radrr5[13:4]];
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always_ff @(posedge rclk6)
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        tago6 <= tags[radrr6[13:4]];
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always_ff @(posedge rclk7)
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        tago7 <= tags[radrr7[13:4]];
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always_ff @(posedge rclk0)
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        vbito0 <= vbit[radrr0[13:4]];
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always_ff @(posedge rclk1)
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        vbito1 <= vbit[radrr1[13:4]];
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always_ff @(posedge rclk2)
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        vbito2 <= vbit[radrr2[13:4]];
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always_ff @(posedge rclk3)
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        vbito3 <= vbit[radrr3[13:4]];
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always_ff @(posedge rclk4)
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        vbito4 <= vbit[radrr4[13:4]];
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always_ff @(posedge rclk5)
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        vbito5 <= vbit[radrr5[13:4]];
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always_ff @(posedge rclk6)
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        vbito6 <= vbit[radrr6[13:4]];
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always_ff @(posedge rclk7)
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        vbito7 <= vbit[radrr7[13:4]];
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always_ff @(posedge wclk)
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        if (wr) tags[wadr[13:4]] <= wadr[31:4];
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always_ff @(posedge wclk)
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if (rst)
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        vbit <= 256'b0;
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else begin
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        if (wr)
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                vbit[wadr[13:4]] <= 1'b1;
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        else if (inv)
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                vbit[wadr[13:4]] <= 1'b0;
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end
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always_comb
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        hit0 = (tago0==radrr0[31:4]) && (vbito0==1'b1);
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always_comb
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        hit1 = (tago1==radrr1[31:4]) && (vbito1==1'b1);
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always_comb
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        hit2 = (tago2==radrr2[31:4]) && (vbito2==1'b1);
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always_comb
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        hit3 = (tago3==radrr3[31:4]) && (vbito3==1'b1);
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always_comb
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        hit4 = (tago4==radrr4[31:4]) && (vbito4==1'b1);
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always_comb
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        hit5 = (tago5==radrr5[31:4]) && (vbito5==1'b1);
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always_comb
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        hit6 = (tago6==radrr6[31:4]) && (vbito6==1'b1);
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always_comb
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        hit7 = (tago7==radrr7[31:4]) && (vbito7==1'b1);
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endmodule

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