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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2015-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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import mpmc8_pkg::*;
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module mpmc8_spr_read_cache(rst, wclk, spr_num, wr, wadr, wdat, inv,
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rclk, radr, rdat, hit
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);
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input rst;
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input wclk;
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input [4:0] spr_num;
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input wr;
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input [31:0] wadr;
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input [127:0] wdat;
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input inv;
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input rclk;
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input [31:0] radr;
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output reg [127:0] rdat;
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output reg hit;
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(* ram_style="block" *)
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reg [127:0] lines [0:511];
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(* ram_style="block" *)
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reg [27:0] tags [0:511];
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(* ram_style="distributed" *)
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reg [511:0] vbit;
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reg [31:0] radrr;
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reg [27:0] tago;
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reg vbito;
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wire [8:0] wadrs = {spr_num,wadr[7:4]};
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wire [8:0] radrs = {spr_num,radrr[7:4]};
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always_ff @(posedge rclk)
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radrr <= radr;
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always_ff @(posedge wclk)
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if (wr) lines[wadrs] <= wdat;
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always_ff @(posedge rclk)
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rdat <= lines[radrs];
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always_ff @(posedge rclk)
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tago <= tags[radrs];
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always_ff @(posedge rclk)
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vbito <= vbit[radrs];
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always_ff @(posedge wclk)
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if (wr) tags[wadrs] <= wadr[31:4];
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always_ff @(posedge wclk)
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if (rst)
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vbit <= 'b0;
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else begin
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if (wr)
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vbit[wadrs] <= 1'b1;
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else if (inv)
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vbit[wadrs] <= 1'b0;
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end
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always_comb
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hit = (tago==radrr[31:4]) && (vbito==1'b1);
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endmodule
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